NEC 78014Y Series, User Manual

Page: 373 / 547

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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78014Y Subseries)
373
Symbol <7> <6> <5> 4 3 2 1 0 Address When Reset R/W
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W Note 1
R/W
CSIM01 CSIM02
Serial Interface Channel 0 Clock Selection
0
×
Input clock to SCK0 pin from off-chip
1 0 8-bit timer register 2 (TM2) output
1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Start Bit
SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/
04 03 02 Mode
P25 Pin Function P26 Pin Function P27 Pin Function
0
×
3-wire serial I/O mode (Refer to 16.4.2 3-wire serial I/O mode operation)
1 0 SBI mode (Refer to 16.4.3 SBI mode operation)
Note 2 Note 2
2-wire serial MSB P25 SB1/SDA1 SCK0/SCL
1 1 0
× ×
0 0 0 1 I/O mode (CMOS (N-ch open-drain (N-ch open-
or I 2 C input/output) input/output) drain
Note 2 Note 2
bus mode SB0/SDA0 P26 input/output)
1 0 0
× ×
0 1 (N-ch open-drain (CMOS
input/output) input/output)
R/W WUP Wake-up Function Control Note 3
0 Interrupt request signal generation with each serial transfer in all modes
1 Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1
when the SBI mode is used or when CMDD = 1 when the I 2 C bus mode is used) matches the slave address
register (SVA) data in the SBI mode and I 2 C bus mode
R COI Slave Address Comparison Result Flag Note 4
0 Slave address register (SVA) not equal to serial I/O shift register 0 (SIC0) data
1 Slave address register (SVA) equal to serial I/O shift register 0 (SIC0) data
R/W CSIE0 Serial Interface Channel 0 Operation Control
0 Operation stopped
1 Operation enable
Notes 1. Bit 6 (COI) is a Read-Only bit.
2. Can be used freely as port function.
3. When 2-wire serial I/O mode is used, be sure to set WUP to 0.
4. When CSIE0 = 0, COI becomes 0.
Remark
×
: don’t care
PM
××
: Port mode register
P
××
: Output latch of port