NEC 78014Y Series, User Manual

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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78014Y Subseries)
390
(4) Various signals
A list of signals in the I
2
C bus mode is given in Table 16-6.
Table 16-6. Signals in the I
2
C Bus Mode
Signal name Signaled by Definition Signaled when Affected flag(s) Function
Start condition Master SDA0 (SDA1) falling edge CMDT is set. CMDD is set. Indicates that serial
when SCL is high
Note 1
communication starts and
subsequent data are
address data.
Stop condition Master SDA0 (SDA1) rising edge RELT is set. RELD is set and Indicates end of serial
when SCL is high
Note 1
CMDD is cleared transmission.
Acknowledge Master or Low level of SDA0 (SDA1) • ACKE = 1. ACKD is set. Indicates completion of
signal (ACK) slave pin during one SCL clock • ACKT is set. reception of 1 byte.
cycle after serial reception
Wait (WAIT) Slave Low-level signal output WAT1, — Indicates state in which
to SCL WAT0 = 1
×
. serial reception is not
possible.
Serial Clock Master Synchronization clock for Execution of data CSIIF0 is Serial communication
(SCL) output of various signals write instruction set.
Note 3
synchronization signal.
Address Master 7-bit data synchronized with to SIO0 when Indicates address value
(A6 to A0) SCL immediately after start CSIE0 = 1 for specification of slave
condition signal (instruction of on serial bus.
Transfer Master 1-bit data output in synchro- serial transfer Indicates whether data
direction nization with SCL after start)
Note 2
transmission or reception
(R/W) address output is to be performed.
Data Master or 8-bit data synchronized with Contains data actually to
(D7 to D0) slave SCL, not immediately after be sent.
start condition
Notes 1. The level of the serial clock can be controlled by bit 3 (CLC) of the interrupt timing specification register
(SINT).
2. In the wait state, the serial transfer operation will be started after the wait state is released.
3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle of
SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock cycle
of SCL.
If WUP = 1, CSIIF0 is set only when an address is received and the address matches the slave address
register (SVA) value.