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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78014Y Subseries)
335
R/W
ACKE
Acknowledge Signal Automatic Output Control (in SBI mode)
0
Acknowledge signal automatic output disable (output with ACKT enable)
1
Before completion
Acknowledge signal is output in synchronization with the 9th clock falling edge of
of transfer
SCK0 (automatically output when ACKE = 1).
After completion
Acknowledge signal is output in synchronization with the falling edge of SCK0 clock
of transfer
immediately after execution of the instruction to be set to 1 (automatically output when
ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
R/W
ACKE
Acknowledge Signal Automatic Output Control
Note 1
(in the I
2
C bus mode)
0
Disables acknowledge signal automatic output. (However, output with ACKT possible)
Use for reception when 8-clock wait mode is selected or for transmission
Note 2
.
1
Enables acknowledge signal automatic output.
Outputs acknowledge signal in synchronization with the 9th clock falling edge of SCL (automatically output
when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
Used in reception with 9-clock wait mode selected.
R
ACKD
Acknowledge Detection
Clear Conditions (ACKD = 0)
Set Conditions (ACKD = 1)
• At the falling edge of SCK0 clock immediately after the
• When acknowledge signal is detected at the rising
busy mode has been released when a transfer start
edge of SCK0/SCL clock after completion of transfer
instruction is executed
• Upon execution of transfer start instruction in the I
2
C
bus mode
• When CSIE0 = 0
• When RESET input is applied
R/W
Note 3
Synchronizing Busy Signal Output Control
BSYE
0
When the SBI mode is used, disables busy signal which is output in synchronization with the falling edge of
SCK0 clock immediately after
execution of the instruction to be cleared to 0. Be sure to set BSYE
to 0 in the I
2
C bus mode.
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal when the SBI mode
is used.
Figure 16-7. Serial Bus Interface Control Register Format (2/2)
Notes
1. Setting should be performed before transfer.
2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT.
3. The busy mode can be cancelled by start of serial interface.
However, the BSYE flag is not cleared to 0.
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Summary of Contents for 78014Y Series
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Page 62: ...www DataSheet4U com CHAPTER 2 OUTLINE PD78014Y Subseries 62 MEMO...
Page 78: ...www DataSheet4U com CHAPTER 3 PIN FUNCTION PD78014 Subseries 78 MEMO...
Page 94: ...www DataSheet4U com CHAPTER 4 PIN FUNCTION PD78014Y Subseries 94 MEMO...
Page 170: ...www DataSheet4U com CHAPTER 7 CLOCK GENERATOR 170 MEMO...
Page 222: ...www DataSheet4U com CHAPTER 9 8 BIT TIMER EVENT COUNTER 222 MEMO...
Page 230: ...www DataSheet4U com CHAPTER 10 WATCH TIMER 230 MEMO...
Page 262: ...www DataSheet4U com CHAPTER 14 A D CONVERTER 262 MEMO...
Page 318: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 PD78014 Subseries 318 MEMO...
Page 408: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 PD78014Y Subseries 408 MEMO...
Page 446: ...www DataSheet4U com CHAPTER 17 SERIAL INTERFACE CHANNEL 1 446 MEMO...
Page 472: ...www DataSheet4U com CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 472 MEMO...
Page 502: ...www DataSheet4U com CHAPTER 22 PD78P014 78P014Y 502 MEMO...
Page 520: ...www DataSheet4U com CHAPTER 23 INSTRUCTION SET 520 MEMO...