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CHAPTER 5 CPU ARCHITECTURE
113
5.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate
data of an operation code are transferred to the program counter (PC) and branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer
to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.
[Illustration]
7
0
High Addr.
PC
15
0
8
7
Low Addr.
Effective Address
15
0
8
7
Operation Code
7
0
0
0
0
0
0
0
0
0
1
0
6
5
1
1
ta
4-0
1
Memory (Table)
1
Effective 1
6
5
1
0
Summary of Contents for 78014Y Series
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Page 78: ...www DataSheet4U com CHAPTER 3 PIN FUNCTION PD78014 Subseries 78 MEMO...
Page 94: ...www DataSheet4U com CHAPTER 4 PIN FUNCTION PD78014Y Subseries 94 MEMO...
Page 170: ...www DataSheet4U com CHAPTER 7 CLOCK GENERATOR 170 MEMO...
Page 222: ...www DataSheet4U com CHAPTER 9 8 BIT TIMER EVENT COUNTER 222 MEMO...
Page 230: ...www DataSheet4U com CHAPTER 10 WATCH TIMER 230 MEMO...
Page 262: ...www DataSheet4U com CHAPTER 14 A D CONVERTER 262 MEMO...
Page 318: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 PD78014 Subseries 318 MEMO...
Page 408: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 PD78014Y Subseries 408 MEMO...
Page 446: ...www DataSheet4U com CHAPTER 17 SERIAL INTERFACE CHANNEL 1 446 MEMO...
Page 472: ...www DataSheet4U com CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 472 MEMO...
Page 502: ...www DataSheet4U com CHAPTER 22 PD78P014 78P014Y 502 MEMO...
Page 520: ...www DataSheet4U com CHAPTER 23 INSTRUCTION SET 520 MEMO...