NEC 78014Y Series, User Manual

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CHAPTER 2 OUTLINE (
µ
PD78014Y Subseries)
49
CHAPTER 2 OUTLINE (
µ
PD78014Y Subseries)
2.1 Features
•
On-chip large-capacity ROM and RAM
Item Program Memory Data Memory
Part (ROM) Internal high-speed RAM Buffer RAM
Number
µ
PD78011BY 8 Kbytes 512 bytes 32 bytes
µ
PD78012BY 16 Kbytes
µ
PD78013Y 24 Kbytes 1024 bytes
µ
PD78014Y 32 Kbytes
µ
PD78P014Y 32 Kbytes
Note 1
1024 bytes
Note 2
Notes 1. 8, 16, 24, or 32 Kbytes can be selected by memory size switching register (IMS).
2. 512 or 1024 bytes can be selected by IMS.
•
External memory expanded space: 64 Kbytes
•
Minimum instruction execution time changeable from high speed (0.4
µ
s: @ 10 MHz with main system clock)
to ultra-low speed (122
µ
s: @ 32.768 kHz with subsystem clock)
•
Instruction set suitable for system control
• Bit manipulation enable in all the address space
• Multiplication/division instruction
•
53 I/O ports (N-ch open-drain: 4)
•
8-bit resolution A/D converter: 8 channels
• Low-voltage operation (AV
DD
= 2.7 to 6.0 V: operable at the same supply voltage range as CPU)
•
Serial interface: 2 channels
• 3-wire serial I/O, SBI, 2-wire serial I/O, I
2
C bus mode: 1 channel
• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel
•
Timer: 5 channels
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
•
14 vectored interrupt sources
•
2 test inputs
•
2 types of on-chip clock oscillator (main system clock and subsystem clock)
•
Power supply voltage: V
DD
= 2.7 to 6.0 V