NEC 78014Y Series, User Manual

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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
185
(6) Sampling clock select register (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Caution f
X
/2
N+1
is the clock supplied to the CPU, and f
X
/2
6
and f
X
/2
7
are clocks supplied to peripheral
hardware. f
X
/2
N+1
is stopped in HALT mode.
Remarks 1. N: Value set in bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0
to 4)
2. f
X
: Main system clock oscillation frequency
3. Values in parentheses apply to operation with f
X
= 10.0 MHz.
Symbol 7 6 5 4 3 2 1 0 Address When Reset R/W
SCS 0 0 0 0 0 0 SCS1 SCS0 FF47H 00H R/W
SCS1 SCS0 INTP0 Sampling Clock Selection
0 0 f
X
/2 N+1
0 1 Setting prohibited
1 0 f
X
/2 6 (156 kHz)
1 1 f
X
/2 7 (78.1 kHz)