NEC 78014Y Series, User Manual

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16
3.2.14 V
DD
...................................................................................................................................... 73
3.2.15 V
SS
....................................................................................................................................... 73
3.2.16 V
PP
(
µ
PD78P014 only) ....................................................................................................... 73
3.2.17 IC (Mask ROM version only) ............................................................................................. 73
3.3 Input/Output Circuit and Recommended Connection of Unused Pins .................. 74
CHAPTER 4 PIN FUNCTION (
µ
PD78014Y Subseries) ............................................................ 79
4.1 Pin Function List ............................................................................................................ 79
4.1.1 Normal operating mode pins ............................................................................................. 79
4.1.2 PROM programming mode pins (
µ
PD78P014Y only) ...................................................... 82
4.2 Description of Pin Functions ....................................................................................... 83
4.2.1 P00 to P04 (Port 0) ............................................................................................................ 83
4.2.2 P10 to P17 (Port 1) ............................................................................................................ 84
4.2.3 P20 to P27 (Port 2) ............................................................................................................ 85
4.2.4 P30 to P37 (Port 3) ............................................................................................................ 86
4.2.5 P40 to P47 (Port 4) ............................................................................................................ 87
4.2.6 P50 to P57 (Port 5) ............................................................................................................ 87
4.2.7 P60 to P67 (Port 6) ............................................................................................................ 88
4.2.8 AV
REF
................................................................................................................................... 88
4.2.9 AV
DD
.................................................................................................................................... 88
4.2.10 AV
SS
.................................................................................................................................... 88
4.2.11 RESET ................................................................................................................................ 88
4.2.12 X1 and X2 ........................................................................................................................... 88
4.2.13 XT1 and XT2 ...................................................................................................................... 89
4.2.14 V
DD
...................................................................................................................................... 89
4.2.15 V
SS
....................................................................................................................................... 89
4.2.16 V
PP
(
µ
PD78P014Y only) ..................................................................................................... 89
4.2.17 IC (Mask ROM versions only) ........................................................................................... 89
4.3 Input/Output Circuit and Recommended Connection of Unused Pins .................. 90
CHAPTER 5 CPU ARCHITECTURE ........................................................................................... 95
5.1 Memory Spaces .............................................................................................................. 95
5.1.1 Internal program memory space ....................................................................................... 100
5.1.2 Internal data memory space .............................................................................................. 101
5.1.3 Special function register (SFR) area ................................................................................. 101
5.1.4 External memory space ..................................................................................................... 101
5.2 Processor Registers ...................................................................................................... 102
5.2.1 Control registers ................................................................................................................. 102
5.2.2 General registers ................................................................................................................ 106
5.2.3 Special function register (SFR) ......................................................................................... 108
5.3 Instruction Address Addressing ................................................................................. 111
5.3.1 Relative addressing ............................................................................................................ 111
5.3.2 Immediate addressing ........................................................................................................ 112
5.3.3 Table indirect addressing ................................................................................................... 113
5.3.4 Register addressing ........................................................................................................... 114