NEC 78014Y Series, User Manual

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CHAPTER 23 INSTRUCTION SET
508
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
Instruc- Mnemonic Operands Byte Clock Operation Flag
tion
Note 1 Note 2 Z AC CY
Group
8-bit ADD A, #byte 2 8 — A, CY
←
A+byte
× × ×
Ope- saddr, #byte 3 12 16 (saddr), CY
←
(saddr)+byte
× × ×
ration A, r
Note 3
2 8 — A, CY
←
A+r
× × ×
r, A 2 8 — r, CY
←
r+A
× × ×
A, saddr 2 8 10 A, CY
←
A+(saddr)
× × ×
A, !addr16 3 16 18 + 2n A, CY
←
A+(addr16)
× × ×
A, [HL] 1 8 10 + 2n A, CY
←
A+(HL)
× × ×
A, [HL + byte] 2 16 18 + 2n A, CY
←
A+(HL+byte)
× × ×
A, [HL + B] 2 16 18 + 2n A, CY
←
A+(HL+B)
× × ×
A, [HL + C] 2 16 18 + 2n A, CY
←
A+(HL+C)
× × ×
ADDC A, #byte 2 8 — A, CY
←
A+byte+CY
× × ×
saddr, #byte 3 12 16 (saddr), CY
←
(saddr)+byte+CY
× × ×
A, r
Note 3
2 8 — A, CY
←
A+r+CY
× × ×
r, A 2 8 — r, CY
←
r+A+CY
× × ×
A, saddr 2 8 10 A, CY
←
A+(saddr)+CY
× × ×
A, !addr16 3 16 18 + 2n A, CY
←
A+(CY
× × ×
A, [HL] 1 8 10 + 2n A, CY
←
A+(HL)+CY
× × ×
A, [HL+byte] 2 16 18 + 2n A, CY
←
A+(HL+byte)+CY
× × ×
A, [HL+B] 2 16 18 + 2n A, CY
←
A+(HL+B)+CY
× × ×
A, [HL+C] 2 16 18 + 2n A, CY
←
A+(HL+C)+CY
× × ×
SUB A, #byte 2 8 — A, CY
←
A–byte
× × ×
saddr, #byte 3 12 16 (saddr), CY
←
(saddr)–byte
× × ×
A, r Note 3 2 8 — A, CY
←
A–r
× × ×
r, A 2 8 — r, CY
←
r–A
× × ×
A, saddr 2 8 10 A, CY
←
A–(saddr)
× × ×
A, !addr16 3 16 18 + 2n A, CY
←
A–(addr16)
× × ×
A, [HL] 1 8 10 + 2n A, CY
←
A–(HL)
× × ×
A, [HL+byte] 2 16 18 + 2n A, CY
←
A–(HL+byte)
× × ×
A, [HL+B] 2 16 18 + 2n A, CY
←
A–(HL+B)
× × ×
A, [HL+C] 2 16 18 + 2n A, CY
←
A–(HL+C)
× × ×