NEC 78014Y Series, User Manual

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CHAPTER 21 RESET FUNCTION
491
CHAPTER 21 RESET FUNCTION
21.1 Reset Function
The following two operations are available to generate the reset function.
(1) External reset input with RESET pin
(2) Internal reset by watchdog timer inadvertent program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status as shown in Table 21-1. Each pin has high impedance during reset input or during oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of
oscillation stabilization time (2
18
/f
X
). The reset applied by watchdog timer overflow is automatically cleared after a
reset and program execution starts after the lapse of oscillation stabilization time (2
18
/f
X
) (see Figures 21-2 to
21-4).
Cautions 1. For an external reset, input a low level for 10 ms or more to the RESET pin.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pin becomes high-impedance.
Figure 21-1. Block Diagram of Reset Function
RESET
Count Clock
Reset Control Circuit
Watchdog Timer
Stop
Overflow
Reset
Signal
Interrupt
Function