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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (

PD78014Y Subseries)

361

Table 16-5. Various Signals in SBI Mode (1/2)

Signal Name

Output

Definition

Timing Chart

Output Condition

Effects on Flag

Meaning of Signal

Device

Bus release

Master

SB0 (SB1) rising edge

• RELT set

• RELD set

CMD signal is output to

signal (REL)

when SCK0 = 1

• CMDD clear

indicate that transmit

data is an address.

Command signal

Master

SB0 (SB1) falling edge

• CMDT set

• CMDD set

i) Transmit data is an

(CMD)

when SCK0 = 1

address after REL

signal output.

ii) REL signal is not

output, and transmit

data is a command.

Acknowledge

Master/

Low-level signal to be

(1) ACKE = 1

• ACKD set

Completion of reception

signal (ACK)

slave

output to SB0 (SB1)

(2) ACKT set

during one-clock period

of SCK0 after completion

of serial reception

Busy signal

Slave

[Synchronous BUSY signal]

• BSYE = 1

—

Serial receive disable

(BUSY)

Low-level signal to be

because of processing

output to SB0 (SB1)

following acknowledge

signal

Ready signal

Slave

High-level signal to be

(1) BSYE = 0

—

Serial receive enable

(READY)

output to SB0 (SB1) before

(2) Execution of

serial transfer start and

instruction data

after completion of serial

write SIO0

transfer

(transfer start

instruction)

SCK0

“H”

SB0 (SB1)

“H”

SB0 (SB1)

SCK0

SB0 (SB1)

[Synchronous BUSY output]

SB0 (SB1)

READY

SCK0

ACK

BUSY

ACK

BUSY

Summary of Contents for 78014Y Series

Page 1: ...CHIP MICROCONTROLLERS PD78011B PD78011BY PD78012B PD78012BY PD78013 PD78013Y PD78014 PD78014Y PD78P014 PD78P014Y PD78011B A PD78012B A PD78013 A PD78014 A User s Manual Printed in Japan Document No U1...

Page 2: ...www DataSheet4U com 2 MEMO...

Page 3: ...ection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing mal...

Page 4: ...Real time Operating system Nucleus ITRON is an abbreviation of Industrial TRON License not needed PD78P014DW 78P014YDW The customer must judge the need for license PD78011BCW 78011BGC AB8 PD78011BCW A...

Page 5: ...fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices develope...

Page 6: ...ven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel...

Page 7: ...l Interface Channel 0 Control Register 2 Serial operating mode register 0 CSIM0 p 287 310 348 371 Cautions were added in sections 15 4 3 and 16 4 3 2 a Bus release signal REL b Command signal CMD 11 C...

Page 8: ...www DataSheet4U com 8 MEMO...

Page 9: ...is manual and Instructions common to the 78K 0 Series PD78014 78014Y SUBSERIES 78K 0 SERIES USER S MANUAL USER S MANUAL This manual Instructions Pin functions CPU functions Internal block functions In...

Page 10: ...EU1372 For the electrical specifications of the PD78014 78014Y Subseries Refer to Data Sheet For the application examples of PD78014 78014Y Subseries functions Refer to Application Note Caution The us...

Page 11: ...PD78014Y Subseries Chapter 5 CPU Architecture Chapter 6 Port Functions Chapter 7 Clock Generator Chapter 8 16 bit Timer Event Counter Chapter 9 8 bit Timer Event Counter Chapter 10 Watch Timer Chapte...

Page 12: ...adecimal H Document Name Document Number Japanese Version English Version PD78014 78014Y Subseries User s Manual U10085J This manual PD78011B 78012B 78013 78014 Data Sheet IC 8201 IC 3179 PD78P014 Dat...

Page 13: ...805 EEU 1400 IE 78014 R EM A EEU 962 EEU 1487 EP 78240 EEU 986 U10332E SM78K0 System Simulator Windows Reference U10181J U10181E SM78 Series System Simulator External Part User U10092J U10092E Open In...

Page 14: ...emiconductor Devices C11531J C11531E Reliability and Quality Control of NEC Semiconductor Devices C10983J C10983E Electrostatic Discharge ESD Test MEM 539 Guide to Quality Assurance of Semiconductor D...

Page 15: ...50 2 3 Ordering Information 50 2 4 Quality Grade 50 2 5 Pin Configurations Top View 51 2 6 78K 0 Series Expansion 56 2 7 Block Diagram 58 2 8 Outline of Function 59 2 9 Mask Options 61 CHAPTER 3 PIN...

Page 16: ...88 4 2 8 AVREF 88 4 2 9 AVDD 88 4 2 10 AVSS 88 4 2 11 RESET 88 4 2 12 X1 and X2 88 4 2 13 XT1 and XT2 89 4 2 14 VDD 89 4 2 15 VSS 89 4 2 16 VPP PD78P014Y only 89 4 2 17 IC Mask ROM versions only 89 4...

Page 17: ...ort 6 144 6 3 Port Function Control Registers 146 6 4 Port Function Operations 152 6 4 1 Writing to input output port 152 6 4 2 Reading from input output port 152 6 4 3 Operations on input output port...

Page 18: ...ter mode 202 9 2 8 Bit Timer Event Counter Configuration 204 9 3 8 Bit Timer Event Counter Control Registers 207 9 4 8 Bit Timer Event Counter Operations 212 9 4 1 8 bit timer event counter mode 212 9...

Page 19: ...2 Serial Interface Channel 0 Configuration 267 15 3 Serial Interface Channel 0 Control Registers 271 15 4 Serial Interface Channel 0 Operations 277 15 4 1 Operation stop mode 277 15 4 2 3 wire serial...

Page 20: ...2 Maskable interrupt request acknowledge operation 462 18 4 3 Software interrupt request acknowledge operation 465 18 4 4 Multiple interrupt servicing 465 18 4 5 Interrupt request reserve 468 18 5 Te...

Page 21: ...d by Addressing Type 516 APPENDIX A DIFFERENCES BETWEEN PD78014 78014H AND 78018F SUBSERIES 521 APPENDIX B DEVELOPMENT TOOLS 523 B 1 Language Processing Software 525 B 2 PROM Programming Tools 526 B 2...

Page 22: ...www DataSheet4U com 22 MEMO...

Page 23: ...5 16 Data Memory Addressing PD78P014 78P014Y 119 6 1 Port Types 129 6 2 P00 Block Diagram 134 6 3 P01 to P03 Block Diagrams 135 6 4 P04 Block Diagram 135 6 5 P10 to P17 Block Diagrams 136 6 6 P20 P21...

Page 24: ...er 190 8 15 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified 191 8 16 Timing of Pulse Width Measurement Operation by Means of Restart with Both Edges Speci...

Page 25: ...mat 246 14 1 A D Converter Block Diagram 248 14 2 A D Converter Mode Register Format 252 14 3 A D Converter Input Select Register Format 253 14 4 A D Converter Basic Operation 255 14 5 Relationship be...

Page 26: ...ion from Slave Device to Master Device 308 15 32 Example of Serial Bus Configuration with 2 Wire Serial I O 310 15 33 2 Wire Serial I O Mode Timings 315 15 34 RELT and CMDT Operations 316 15 35 SCK0 P...

Page 27: ...t Condition 380 16 39 Address 381 16 40 Transfer Direction Specification 381 16 41 Acknowledge Signal 382 16 42 Stop Condition 382 16 43 Wait Signal 383 16 44 Pin Configuration 391 16 45 Data Transmis...

Page 28: ...lag Register Format 453 18 4 Priority Specify Flag Register Format 454 18 5 External Interrupt Mode Register Format 455 18 6 Sampling Clock Select Register Format 456 18 7 Noise Eliminator Input Outpu...

Page 29: ...upon RESET Input 490 21 1 Block Diagram of Reset Function 491 21 2 Timing of Reset by RESET Input 492 21 3 Timing of Reset due to Watchdog Timer Overflow 492 21 4 Timing of Reset in STOP Mode by RESET...

Page 30: ...www DataSheet4U com 30 MEMO...

Page 31: ...truction Execution Time 159 7 3 Maximum Time Required for CPU Clock Switchover 168 8 1 Timer Event Counter Operation 172 8 2 16 Bit Timer Event Counter Interval Times 172 8 3 16 Bit Timer Event Counte...

Page 32: ...nfiguration 267 15 4 Various Signals in SBI Mode 300 16 1 Differences between Channels 0 and 1 319 16 2 Difference of Serial Interface Channel 0 Mode 320 16 3 Serial Interface Channel 0 Configuration...

Page 33: ...set 493 22 1 Differences between PD78P014 78P014Y and Mask ROM Version 495 22 2 Internal Memory Size Switching Register Value at Reset 496 22 3 PROM Programming Operating Modes 497 23 1 Operand Identi...

Page 34: ...www DataSheet4U com 34 MEMO...

Page 35: ...MHz with main system clock to ultra low speed 122 s 32 768 KHz with subsystem clock Instruction set suitable for system control Bit manipulation can be enabled in all the address space Multiplication...

Page 36: ...P 750 mils Mask ROM PD78013GC AB8 64 pin plastic QFP 14 14 mm Mask ROM PD78014CW 64 pin plastic shrink DIP 750 mils Mask ROM PD78014GC AB8 64 pin plastic QFP 14 14 mm Mask ROM PD78P014CW 64 pin plasti...

Page 37: ...GC AB8 64 pin plastic QFP 14 14 mm Standard PD78011BCW A 64 pin plastic shrink DIP 750 mils Special PD78011BGC AB8 64 pin plastic QFP 14 14 mm Special PD78012BCW A 64 pin plastic shrink DIP 750 mils S...

Page 38: ...D78P014 P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 A...

Page 39: ...16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 V SS P56 A14 P57 A15 P60 P61 P62 P63 P64 RD P65 WR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 40: ...trobe X1 X2 Crystal Main System Clock XT1 XT2 Crystal Subsystem Clock A8 to A15 Address Bus AD0 to AD7 Address Data Bus ANI0 to ANI7 Analog Input ASTB Address Strobe AVDD Analog Power Supply AVREF Ana...

Page 41: ...a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open No connection required D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A10 A11 A12 A13 VSS 64 63 62 61 60 5...

Page 42: ...14 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40...

Page 43: ...pin 100 pin PD780308Y PD78064Y PD78098 80 pin PD78P0914 64 pin 78K 0 Series An N ch open drain I O was added to the PD78044F Display output total 34 Basic subseries for driving FIP Display output tota...

Page 44: ...V time division PD780024 8ch 3 wire 1ch PD78014H 2ch 53 1 8 V PD78018F 8K to 60K PD78014 8K to 32K 2 7 V PD780001 8K 1ch 39 PD78002 8K to 16K 1ch 53 PD78083 8ch 1ch UART 1ch 33 1 8 V Inverter PD78096...

Page 45: ...VDD AVSS AVREF INTP0 P00 to INTP3 P03 BUZ P36 CLOCK OUTPUT CONTROL PCL P35 BUZZER OUTPUT INTERRUPT CONTROL A D CONVERTER SERIAL INTERFACE 1 SERIAL INTERFACE 0 WATCH TIMER WATCHDOG TIMER 8 bit TIMER EV...

Page 46: ...eset test and Boolean operation BCD adjust and other related operations I O ports Total 53 I O port pins CMOS input 2 inputs CMOS I O 47 inputs outputs on chip pull up resistor can be turned on off by...

Page 47: ...kHz 625 kHz 1 25 MHz 10 0 MHz with main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz 10 0 MHz with main system clock Vectored Maskable Internal 8 exter...

Page 48: ...PD78014 have the mask options By specifying the mask options when ordering the pull up resistors and pull down resistors listed in Table 1 2 can be incorporated When these resistors are necessary the...

Page 49: ...th main system clock to ultra low speed 122 s 32 768 kHz with subsystem clock Instruction set suitable for system control Bit manipulation enable in all the address space Multiplication division instr...

Page 50: ...uality Grade PD78011BYCW 64 pin plastic shrink DIP 750 mils Standard PD78011BYGC AB8 64 pin plastic QFP 14 14 mm Standard PD78012BYCW 64 pin plastic shrink DIP 750 mils Standard PD78012BYGC AB8 64 pin...

Page 51: ...2 SCK1 P23 STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P...

Page 52: ...37 36 35 34 33 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 V SS P56 A14 P57 A15 P60 P61 P62 P63 P64 RD P65 WR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P30 TO0 P31 TO1 P32 TO2 P33 TI1...

Page 53: ...17 Port1 P20 to P27 Port2 P30 to P37 Port3 P40 to P47 Port4 P50 to P57 Port5 P60 to P67 Port6 PCL Programmable Clock RD Read Strobe RESET Reset SB0 SB1 Serial Bus SCK0 SCK1 Serial Clock SCL Serial Clo...

Page 54: ...a a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open No connection required L D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 L A10 A11 A12 A13 VSS 64 63 62 61...

Page 55: ...4 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 3...

Page 56: ...pin 100 pin PD780308Y PD78064Y PD78098 80 pin PD78P0914 64 pin 78K 0 Series An N ch open drain I O was added to the PD78044F Display output total 34 Basic subseries for driving FIP Display output tota...

Page 57: ...c transmit receive function 1ch 3 wire time division UART 1ch PD78058FY 48K to 60K 3 wire 2 wire I2 C 1ch 69 2 7 V 3 wire with automatic transmit receive function 1ch PD78054Y 16K to 60K 3 wire UART 1...

Page 58: ...I7 P17 AVDD AVSS AVREF INTP0 P00 to INTP3 P03 BUZ P36 CLOCK OUTPUT CONTROL PCL P35 BUZZER OUTPUT INTERRUPT CONTROL A D CONVERTER SERIAL INTERFACE 1 SERIAL INTERFACE 0 WATCH TIMER WATCHDOG TIMER 8 bit...

Page 59: ...reset test and Boolean operation BCD adjust and other related operations I O ports Total 53 I O ports CMOS input 2 inputs CMOS I O 47 inputs outputs on chip pull up resistor can be turn on off by soft...

Page 60: ...main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz 10 0 MHz with main system clock Vectored Maskable Internal 8 external 4 interrupt Non maskable Inter...

Page 61: ...ull up resistors and pull down resistors listed in Table 2 1 can be incorporated When these resistors are necessary the number of external components and mounting space can be saved by utilizing the m...

Page 62: ...www DataSheet4U com CHAPTER 2 OUTLINE PD78014Y Subseries 62 MEMO...

Page 63: ...tor can be connected by softwareNote 2 P20 Input Port 2 Input SI1 P21 Output 8 bit input output port SO1 P22 Input output specifiable bit wise SCK1 P23 If used as an input port an on chip pull up resi...

Page 64: ...lling edge detection P50 to P57 Input Port 5 Input A8 to A15 Output 8 bit input output port Input output specifiable in 8 bit wise LED can be driven directly When used as an input port an on chip pull...

Page 65: ...erface automatic transmit receive busy input Input P24 TI0 Input External count clock input to 16 bit timer TM0 Input P00 INTP0 TI1 External count clock input to 8 bit timer TM1 P33 TI2 External count...

Page 66: ...T2 VDD Positive power supply VPP High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Connect directly to VSS...

Page 67: ...register 0 PM0 When they are used as input ports a pull up resistor can be connected to them with an on chip pull up resistor option register PUO 2 Control mode In this mode these ports function as an...

Page 68: ...se 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 1 PM1 When used as an input port an on chip pull up resi...

Page 69: ...hem with a pull up resistor option register PUO 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output a S...

Page 70: ...ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports an on chip pull up resistor can be co...

Page 71: ...s low order address data bus pins in external memory expansion mode When they are used as address data bus an on chip pull up resistor is automatically unused 3 2 6 P50 to P57 Port 5 These are 8 bit i...

Page 72: ...e ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as control signal output the on chip pull up resistor is automatically disabled Caut...

Page 73: ...write verify Connect directly to VSS in normal operating mode 3 2 17 IC Mask ROM version only The IC Internally Connected pin sets a test mode in which the PD78011B 78012B 78013 and 78014 are tested...

Page 74: ...t output Independently connect to VSS via a resistor P02 INTP2 P03 INTP3 P04 XT1 16 Input Connect to VDD or VSS P10 ANI0 to P17 ANI7 11 Input output Independently connect to VDD or VSS via a resistor...

Page 75: ...in Input Output Circuit Types 2 2 Pin Name Input Output Input Output Recommended Connection for Unused Pins Circuit Type RESET 2 Input XT2 16 Leave open AVREF Connect to VSS AVDD Connect to VDD AVSS C...

Page 76: ...ll up enable data output disable VDD P ch N ch P ch IN OUT VDD Type 5 A input enable Type 5 E pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Schmitt triggered input with hysteresis c...

Page 77: ...77 Figure 3 1 Pin Input Output Circuit List 2 2 Type 13 Type 16 Type 13 B data output disable N ch IN OUT VDD VDD RD Mask Option Middle High Voltage Input Buffer XT1 XT2 P ch feedback cut off P ch dat...

Page 78: ...www DataSheet4U com CHAPTER 3 PIN FUNCTION PD78014 Subseries 78 MEMO...

Page 79: ...ll up resistor can be connected by softwareNote 2 P20 Input Port 2 Input SI1 P21 Output 8 bit input output port SO1 P22 Input output specifiable bit wise SCK1 P23 If used as an input port an on chip p...

Page 80: ...falling edge detection P50 to P57 Input Port 5 Input A8 to A15 Output 8 bit input output port LED can be driven directly Input output specifiable bit wise When used as an input port an on chip pull u...

Page 81: ...tput Input P23 BUSY Input Serial interface automatic transmit receive busy input Input P24 TI0 Input External count clock input to 16 bit timer TM0 Input P00 INTP0 TI1 External count clock input to 8...

Page 82: ...T2 VDD Positive power supply VPP High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Directly connect to VSS...

Page 83: ...register 0 PM0 When they are used as input ports a pull up resistor can be connected to them with an on chip pull up resistor option register PUO 2 Control mode In this mode these ports function as an...

Page 84: ...ise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 1 PM1 When used as input ports an on chip pull up resis...

Page 85: ...pull up resistor option register PUO 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output a SI0 SI1 SO0...

Page 86: ...ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports an on chip pull up resistor can be co...

Page 87: ...order address data bus pins in external memory expansion mode When they are used as address data bus the on chip pull up resistor is automatically disabled 4 2 6 P50 to P57 Port 5 These are 8 bit inp...

Page 88: ...ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as control signal output the on chip pull up resistor is automatically disabled Cautio...

Page 89: ...write verify Connect directly to VSS in normal operating mode 4 2 17 IC Mask ROM versions only The IC Internally Connected pin sets a test mode in which the PD78011BY 78012BY 78013Y and 78014Y are tes...

Page 90: ...ut Independently connect to VSS via a resistor P02 INTP2 P03 INTP3 P04 XT1 16 Input Connect to VDD or VSS P10 ANI0 to P17 ANI7 11 Input output Independently connect to VDD or VSS via a resistor P20 SI...

Page 91: ...Pin Input Output Circuit Types 2 2 Pin Name Input Output Input Output Recommended Connection for Unused Pins Circuit Type RESET 2 Input XT2 16 Leave open AVREF Connect to VSS AVDD Connect to VDD AVSS...

Page 92: ...ull up enable data output disable VDD P ch N ch P ch IN OUT VDD Type 5 A input enable Type 5 E pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Schmitt triggered input with hysteresis...

Page 93: ...93 Figure 4 1 Pin Input Output Circuit List 2 2 Type 13 Type 16 Type 13 B data output disable N ch IN OUT VDD VDD RD Mask Option Middle High Voltage Input Buffer XT1 XT2 P ch feedback cut off P ch dat...

Page 94: ...www DataSheet4U com CHAPTER 4 PIN FUNCTION PD78014Y Subseries 94 MEMO...

Page 95: ...ed Buffer RAM 32 8 bits Use Prohibited External Memory 55936 8 bits Internal ROM 8192 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector T...

Page 96: ...4 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Inte...

Page 97: ...8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Intern...

Page 98: ...8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Intern...

Page 99: ...8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Inter...

Page 100: ...FH is reserved as vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address the low o...

Page 101: ...ack memory area 2 Buffer RAM Buffer RAM is allocated to the 32 byte area from FAC0H to FADFH Buffer RAM is used for storing transmit receive data of serial interface channel 1 3 wire serial I O mode w...

Page 102: ...uction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program count...

Page 103: ...flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If...

Page 104: ...FD00H to FEFFH PD78013 78013Y 78014 78014Y 78P014 78P014Y FB00H to FEFFH Figure 5 8 Stack Pointer Configuration The SP is decremented ahead of write save to the stack memory and is incremented after...

Page 105: ...n PC7 to PC0 PC15 to PC8 RET Instruction Register Pair Lower Register Pair Upper POP rp Instruction SP SP 1 SP SP 2 SP SP 1 SP SP 2 SP SP 1 SP 2 SP SP 3 PC7 to PC0 PC15 to PC8 PSW Interrupt and BRK In...

Page 106: ...ntrol instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt request fo...

Page 107: ...1 R0 8 Bit Processing 16 Bit Processing RP3 RP2 RP1 RP0 BANK0 BANK1 BANK2 BANK3 15 0 7 0 F E F F H F E F 8 H F E F 7 H F E F 0 H F E E F H F E E 8 H F E E 7 H F E E 0 H H L D E B C A X HL DE BC AX BAN...

Page 108: ...instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp W...

Page 109: ...imer register 2 TM2 FF1AH Serial I O shift register 0 SIO0 R W Undefined FF1BH Serial I O shift register 1 SIO1 FF1FH A D conversion result register ADCR R FF20H Port mode register 0 PM0 R W 1FH FF21H...

Page 110: ...register 1 CSIM1 FF69H Automatic data transmit receive control register ADTC FF6AH Automatic data transmit receive address pointer ADTP FF80H A D converter mode register ADM 01H FF84H A D converter i...

Page 111: ...3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to...

Page 112: ...he CALL addr16 BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the memory spaces CALLF addr11 instruction branches to the area from 0800H to...

Page 113: ...de are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in the...

Page 114: ...egister addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instru...

Page 115: ...ity In particular specific types of addressing can be used which match the functions of the special function registers SFRs general registers etc Data memory addressing is shown in Figures 5 12 to 5 1...

Page 116: ...AM 32 8 bits Use Prohibited External Memory 47744 8 bits Internal ROM 16384 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addre...

Page 117: ...AM 32 8 bits Use Prohibited External Memory 39552 8 bits Internal ROM 24576 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addre...

Page 118: ...AM 32 8 bits Use Prohibited External Memory 31360 8 bits Internal ROM 32768 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addre...

Page 119: ...AM 32 8 bits Use Prohibited External Memory 31360 8 bits Internal PROM 32768 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addr...

Page 120: ...and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values subject to decimal adjustment ROR4 ROL4 A register for sto...

Page 121: ...owing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H r...

Page 122: ...mediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Inst...

Page 123: ...o FF1FH where short direct addressing is applied is a part of all SFR areas In this area ports which are frequently accessed in a program and a compare register of the timer event counter and a captur...

Page 124: ...nd immediate data to 50H Instruction code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration 7 0 Effective address 15 0 8 OP code saddr offset 1 1...

Page 125: ...CFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit m...

Page 126: ...gister bank select flag RBS0 and RBS1 and the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE H...

Page 127: ...ster pair to be accessed is in the register bank specified with the register bank select flags RBS0 and RBS1 The offset data as a positive number is expanded to 16 bits to be added A carry from the 16...

Page 128: ...be added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL...

Page 129: ...t output ports Figure 6 1 shows the port types Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also...

Page 130: ...put specifiable bit wise SCK1 P23 If used as an input port on chip pull up resistor is enabled by software STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 Port 3 TO0 P31 8 bit input output port TO1...

Page 131: ...P60 Port 6 N ch open drain input output port On chip P61 8 bit input output port pull up resistor can be specified by mask P62 Input output specifiable bit wise option only for mask ROM versions P63 L...

Page 132: ...port on chip pull up resistor is enabled by software STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 Port 3 TO0 P31 8 bit input output port TO1 P32 Input output specifiable bit wise TO...

Page 133: ...chip P61 8 bit input output port pull up resistor can be specified by mask P62 Input output specifiable bit wise option only for mask ROM versions P63 LED can be driven directly P64 When used as an i...

Page 134: ...put mode output mode bit wise with the port mode register 0 PM0 P00 and P04 pins are input only ports When P01 to P03 pins are used as input ports a pull up resistor can be connected to them in 3 bit...

Page 135: ...rt mode register RD Port 0 read signal WR Port 0 write signal Figure 6 4 P04 Block Diagram Figure 6 3 P01 to P03 Block Diagrams RD Port 0 read signal WRPUO RD WRPORT WRPM PUO0 Output Latch P01 to P03...

Page 136: ...ith a pull up resistor option register PUO Alternate functions include an A D converter analog input RESET input sets port 1 to input mode Figure 6 5 shows a block diagram of port 1 Caution On chip pu...

Page 137: ...nd 6 7 show a block diagram of port 2 Cautions 1 If used as alternate function pin set the input output latch according to the functions Refer to Figure 15 5 Serial Operating Mode Register 0 Format an...

Page 138: ...P27 Block Diagrams PD78014 Subseries PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal WRPUO RD WRPORT WRPM PUO2 Output Latch P22 P27 PM22 PM27 S...

Page 139: ...9 show a block diagram of port 2 Cautions 1 If used as alternate function pin set the input output latch according to the functions Refer to Figure 16 6 Serial Operating Mode Register 0 Format and Fig...

Page 140: ...27 Block Diagrams PD78014Y Subseries PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal WRPUO RD WRPORT WRPM PUO2 Output Latch P22 P27 PM22 PM27 Se...

Page 141: ...nits with a pull up resistor option register PUO Alternate functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 10 shows a block diagram o...

Page 142: ...unctions include address data bus in external memory expansion mode RESET input sets port 4 to input mode Figure 6 11 shows a block diagram of port 4 Figure 6 12 shows a block diagram of the falling e...

Page 143: ...to them in 8 bit units with a pull up resistor option register PUO Port 5 can drive LEDs directly Alternate functions include address bus in external memory expansion mode RESET input sets port 5 to i...

Page 144: ...d PUO6 Bit 6 of the pull up resistor option register P60 to P63 pins can drive LEDs directly The alternate function of the P60 to P63 pins is control signal output in external memory expansion mode RE...

Page 145: ...up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal RD WRPORT WRPM Output Latch P60 to P63 PM60 to PM63 Selector VDD P60 to P63 Mask Option resistors Mask RO...

Page 146: ...ith a 1 bit or 8 bit memory manipulation instruction RESET input sets PM0 to 1FH and other registers to FFH When a port pin is used as its alternate function pin set the port mode register and the out...

Page 147: ...P67 ASTB Output Note 2 P35 PCL Output 0 0 P36 BUZ Output 0 0 Notes 1 Read data will be undefined if the read instruction is executed for the port when used as alternate function pin 2 When pins P40 t...

Page 148: ...PM14 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50...

Page 149: ...O is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 P00 and P04 pins do not incorporate a pull up resistor 2 When port 1 port 4 port 5 or P6...

Page 150: ...0 1 1 Memory 256 bytes AD0 to Port mode P64 RD expansion mode AD7 P65 WR 1 0 0 mode 4 Kbytes A8 to A11 Port mode P66 WAIT mode P67 ASTB 1 0 1 16 Kbytes A12 A13 Port mode mode 1 1 1 Full address A14 A1...

Page 151: ...nput sets KRM to 02H Figure 6 19 Key Return Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W KRM 0 0 0 0 0 0 KRMK KRIF FFF6H 02H R W KRIF Key Return Signal Detection Flag 0 Undetecte...

Page 152: ...since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memor...

Page 153: ...tch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the...

Page 154: ...T FUNCTIONS 154 6 5 Mask Options Mask ROM versions can contain a pull up resistor in P60 to P63 pins bit wise with the mask option The PD78P014 and 78P014Y have no mask option and do not contain a pul...

Page 155: ...the processor clock control register PPC 2 Subsystem clock oscillator Oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the on chip fe...

Page 156: ...ator circuit Main system clock oscil lator circuit fXT fX STOP Internal bus Processor clock control register MCC FRC CLS CSS PCC2 PCC1 PCC0 3 Prescaler fX 2 fX 22 fX 23 fX 24 To INTP0 sampling clock S...

Page 157: ...PCC The PCC sets CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator on chip feedback resistor enable disable The PCC is set with a 1...

Page 158: ...CLS CPU Clock Status 0 Main system clock 1 Subsystem clock R W FRC Subsystem Clock Feedback Resistor Selection 0 On chip feedback resistor used 1 On chip feedback resistor not used R W MCC Main Syste...

Page 159: ...CPU and minimum instruction execution time is as shown in Table 7 2 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock fCPU Minimum Instruction Execution Time 4...

Page 160: ...clock Caution The STOP mode cannot be set while an external clock is being input This is because the X1 pin is short circuited to VSS in the STOP mode 7 4 2 Subsystem clock oscillator The subsystem cl...

Page 161: ...the capacitor of the oscillator circuit at the same potential as VSS Do not connect the power source pattern through which a high current flows Do not extract signals from the oscillator Take special...

Page 162: ...gnal extracted Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Further insert resistors in series on the side of XT2 Cautions 2 When XT2 and X1 are wired parallel X...

Page 163: ...on operations and watch operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD or VSS XT2 Open In this state however some current may leak via the on chip feedback resistor of the subsy...

Page 164: ...em clock selected two standby modes the STOP and HALT modes are available With the subsystem clock unused the current consumption in STOP mode can be further decreased by disabling the subsystem clock...

Page 165: ...execution time can be changed by bits 0 to 2 PCC0 to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop Whe...

Page 166: ...MCC is set with main system clock operation c Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Cl...

Page 167: ...ocessor clock control register PCC set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 s when operated at 32 768 kHz irrespective of bits 0...

Page 168: ...ns 16 instructions 16 instructions 16 instructions fX 4fXT instructions 77 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions fX 8fXT instructions 39 instructions 0 1 0 4 i...

Page 169: ...ster PCC is rewritten and maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system clock is switched to the subsystem...

Page 170: ...www DataSheet4U com CHAPTER 7 CLOCK GENERATOR 170 MEMO...

Page 171: ...and to output square waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This time...

Page 172: ...er function 8 2 16 Bit Timer Event Counter Functions The 16 bit timer event counter TM0 has the following functions Interval timer PWM output Pulse width measurement External event counter Square wave...

Page 173: ...800 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 24 1 fX 1 6 s 219 1 fX 52 4 ms 23 1 fX 800 ns Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz 8...

Page 174: ...it compare register CR00 Match Match fX 2 fX 22 fX 23 TI0 P00 INTP0 Selector Note 1 TCL06 TCL05 TCL04 Timer clock select register 0 16 bit capture register CR01 16 bit timer register lower 8 bits TM0L...

Page 175: ...ed line is included in the output control circuit Internal bus Internal bus 16 bit compare register CR00 16 bit timer register TM0 16 bit capture register CR01 PWM pulse generator Selector 3 TCL06 TCL...

Page 176: ...Block Diagram Remark The circuitry enclosed by the dotted line is the output control circuit LVR0 LVS0 TOC01 INTTM0 TI0 P00 INTP0 PWM pulse generator Edge detector circuit 2 ES10 ES11 3 Selector R S I...

Page 177: ...ion is less than the value of the 16 bit timer register TM0 TM0 keeps on counting and resumes counting from 0 after an overflow When the value of CR00 posterior to alteration is less than the value pr...

Page 178: ...t timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register INTM0 Sampling clock select register SCS 1 Timer clock select register 0 TCL0 This register is used to se...

Page 179: ...1 Output enabled Cautions 1 Setting of the INTP0 P00 TI0 pin valid edge is performed by external interrupt mode register INTM0 and selection of the sampling clock frequency is performed by the sampli...

Page 180: ...timer register clear mode and output timing and detects an overflow TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC0 value to 00H Caution The 16 bit timer regis...

Page 181: ...een TM0 and edge CR00 1 0 1 Match between TM0 and CR00 or TI0 valid edge 1 1 0 Clear start on match Match between TM0 and between TM0 and CR00 CR00 1 1 1 Match between TM0 and CR00 or TI0 valid edge C...

Page 182: ...Bit Timer Output Control Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TOC0 0 0 0 0 LVS0 LVR0 TOC01 TOE0 FF4EH 00H R W Cautions 1 Timer operation must be stopped before setting TOC0 2...

Page 183: ...30 and output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address...

Page 184: ...en Reset R W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 0 0 FFECH 00H R W ES11 ES10 INTP0 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edge ES21 ES...

Page 185: ...9 Sampling Clock Select Register Format Caution fX 2N 1 is the clock supplied to the CPU and fX 26 and fX 27 are clocks supplied to peripheral hardware fX 2N 1 is stopped in HALT mode Remarks 1 N Valu...

Page 186: ...lue of the 16 bit timer register TM0 matches the value set to CR00 counting continues with the TM0 value cleared to 0 and the interrupt request signal INTTM0 is generated Count clock of the 16 bit tim...

Page 187: ...fX 13 1 ms 2 1 fX 200 ns 0 1 1 23 1 fX 800 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 1 0 0 24 1 fX 1 6 s 219 1 fX 52 4 ms 23 1 fX 800 ns Other than above Setting prohibited Remarks 1 fX Main system clock os...

Page 188: ...register TOC0 This PWM pulse has a 14 bit resolution The pulse can be converted to an analog voltage by integrating it with an external low pass filter LPF The PWM pulse has a combination of the basi...

Page 189: ...bit compare register CR00 value VAN VREF 216 VREF External switching circuit reference voltage Figure 8 12 Example of D A Converter Configuration with PWM Output Figure 8 13 shows an example in which...

Page 190: ...register INTM0 is input the value of TM0 is taken into 16 bit capture register CR01 and an external interrupt request signal INTP0 is set Any of three edge specifications can be selected rising falli...

Page 191: ...ER Figure 8 15 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified Count Clock TM0 Count Value 0000 0001 D0 D1 FFFF 0000 D2 D3 TI0 Pin Input CR01 Captured Val...

Page 192: ...can be selected from three types rising falling and both edges by bit 2 and bit 3 ES10 and ES11 of the external interrupt mode register INTM0 In a valid edge detection the sampling is performed by a...

Page 193: ...interrupt request signal INTTM0 is generated The 16 bit compare register CR00 must be set to a value other than 0000H 1 pulse count operation is prohibited The rising edge the falling edge or both ed...

Page 194: ...194 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 18 External Event Counter Operation Timings with Rising Edge Specified TI0 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 N 1 N 0000 0001 000...

Page 195: ...Output Ranges TCL06 TCL05 TCL04 Minimum Pulse Width Maximum Pulse Width Resolution 0 0 0 2 TI0 input cycle 216 TI0 input cycle TI0 input edge cycle 0 1 0 22 1 fX 400 ns 217 1 fX 13 1 ms 2 1 fX 200 ns...

Page 196: ...g the 16 bit compare register as event counter one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit comp...

Page 197: ...igure 8 22 Capture Register Data Retention Timings 5 Valid edge set Set the valid edge of the TI0 INTP0 P00 pin after setting bits 1 to 3 TMC01 to TMC03 of the 16 bit timer mode control register TMC0...

Page 198: ...F0 flag operation OVF0 flag is set to 1 When clear start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH TM0 is counted up from FFFFH to 0000H Figure 8 23 OVF0 Flag Operation Timin...

Page 199: ...following two modes are available 8 bit timer event counter mode two channel 8 bit timer event counters to be used separately 16 bit timer event counter mode two channel 8 bit timer event counters to...

Page 200: ...fX 204 8 s 23 1 fX 800 ns 24 1 fX 1 6 s 212 1 fX 409 6 s 24 1 fX 1 6 s 25 1 fX 3 2 s 213 1 fX 819 2 s 25 1 fX 3 2 s 26 1 fX 6 4 s 214 1 fX 1 64 ms 26 1 fX 6 4 s 27 1 fX 12 8 s 215 1 fX 3 28 ms 27 1 f...

Page 201: ...3 28 ms 27 1 fX 12 8 s 28 1 fX 25 6 s 216 1 fX 6 55 ms 28 1 fX 25 6 s 29 1 fX 51 2 s 217 1 fX 13 1 ms 29 1 fX 51 2 s 210 1 fX 102 4 s 218 1 fX 26 2 ms 210 1 fX 102 4 s 212 1 fX 409 6 s 220 1 fX 104 9...

Page 202: ...X 26 2 ms 22 1 fX 400 ns 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 24 1 fX 1 6 s 220 1 fX 104 9 ms 24 1 fX 1 6 s 25 1 fX 3 2 s 221 1 fX 209 7 ms 25 1 fX 3 2 s 26 1 fX 6 4 s 222 1 fX 419 4 ms 26 1...

Page 203: ...on 22 1 fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 24 1 fX 1 6 s 220 1 fX 104 9 ms 24 1 fX 1 6 s 25 1 fX 3 2 s 221 1 fX 209 7 ms 25 1 fX 3 2 s 26 1 fX 6 4...

Page 204: ...5 8 Bit Timer Event Counter Configuration Item Configuration Timer register 8 bits 2 TM1 TM2 Register 8 bit compare register 2 CR10 CR20 Timer output 2 TO1 TO2 Control registers Timer clock select re...

Page 205: ...1 TM1 Clear 4 TCL 17 TCL 16 TCL 15 TCL 14 TCL 13 TCL 12 TCL 11 TCL 10 Timer Clock Select Register 1 TMC12 TCE2 TCE1 8 Bit Timer Mode Control Register 8 Bit Timer Register 1 TM2 Clear Note Note 8 Bit...

Page 206: ...n output control circuit Figure 9 3 8 Bit Timer Event Counter Output Control Circuit 2 Block Diagram Note Bit 2 of the port mode register 3 PM3 Remarks 1 The section in the broken line is an output co...

Page 207: ...f CR10 and CR20 posterior to alteration are less than the values of the 8 bit timer registers TM1 and TM2 TM1 and TM2 keep on counting and resume counting from 0 after an overflow When the values of C...

Page 208: ...1 1 1 1 fX 212 2 4 kHz Other than above Setting prohibited TCL17 TCL16 TCL15 TCL14 8 bit Timer Register 2 Clock Selection 0 0 0 0 TI2 falling edge 0 0 0 1 TI2 rising edge 0 1 1 0 fX 22 2 5 MHz 0 1 1...

Page 209: ...er Format Cautions 1 Switch the operating mode after stopping timer operation 2 When used as 16 bit timer register TMS TCE1 should be used for operation enable stop Symbol 7 6 5 4 3 2 1 0 Address When...

Page 210: ...ontrol 0 Output disable port mode 1 Output enable TOC11 8 Bit Timer Event Counter 1 Timer Output F F Control 0 Inverted operation disable 1 Inverted operation enable LVS1 LVR1 8 Bit Timer Event Counte...

Page 211: ...et output latches PM31 PM32 and P31 P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0...

Page 212: ...d to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to 3 TCL10 toTCL13 of the timer clock select register 1 TCL1 Count clock of TM2...

Page 213: ...Interval Time Resolution 0 0 0 0 TI2 input cycle 28 TI2 input cycle TI2 input edge cycle 0 0 0 1 TI2 input cycle 28 TI2 input cycle TI2 input edge cycle 0 1 1 0 22 1 fX 400 ns 210 1 fX 102 4 s 22 1 fX...

Page 214: ...he valid edge specified with the timer clock select register 1 TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare reg...

Page 215: ...theses apply to operation with fX 10 0 MHz Figure 9 10 Square Wave Output Operation Timings TCL13 TCL12 TCL11 TCL10 Minimum Pulse Width Maximum Pulse Width Resolution 0 1 1 0 22 1 fX 400 ns 210 1 fX 1...

Page 216: ...count value the upper 8 bit value is set as CR20 and the lower 8 bit value as CR10 For the count value interval time which can be set refer to Table 9 9 When the 8 bit timer register 1 TM1 and CR10 v...

Page 217: ...tion 0 0 0 0 TI1 input cycle 28 TI1 input cycle TI1 input edge cycle 0 0 0 1 TI1 input cycle 28 TI1 input cycle TI1 input edge cycle 0 1 1 0 22 1 fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 0 1 1 1 23 1...

Page 218: ...it compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified Cau...

Page 219: ...aximum Pulse Width Resolution 0 1 1 0 22 1 fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 0 1 1 1 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 1 0 0 0 24 1 fX 1 6 s 220 1 fX 104 9 ms 24 1 fX 1 6 s 1 0 0...

Page 220: ...mpare registers 1 and 2 sets The 8 bit compare registers CR10 and CR20 can be set to 00H Therefore when the 8 bit compare register is used as event counter one pulse count operation can be carried out...

Page 221: ...hose of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value after CR10 and CR20 M change is smaller than that before change N it...

Page 222: ...www DataSheet4U com CHAPTER 9 8 BIT TIMER EVENT COUNTER 222 MEMO...

Page 223: ...ency other than above is used a flag WTIF is not set at 0 5 0 25 or 0 5 1 0 intervals Caution When 8 38 MHz or 4 19 MHz frequency is used a time interval has a little error 2 Interval timer Interrupt...

Page 224: ...10 3 Watch Timer Control Registers The following two types of registers are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock sele...

Page 225: ...m fX 28 fXT fW TMC21 Clear Prescaler TCL24 Timer Clock Select Register 2 5 Bit Counter Clear INTWT INTTM3 3 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Control Register Internal Bus Sel...

Page 226: ...z 1 1 0 fX 210 9 8 kHz 1 1 1 fX 212 2 4 kHz TCL24 Watch Timer Count Clock Selection 0 fX 28 39 1 kHz 1 fXT 32 768 kHz TCL27 TCL26 TCL25 Buzzer Output Frequency Selection 0 Buzzer output disable 1 0 0...

Page 227: ...0 0 0 24 fW 488 s 0 0 1 25 fW 977 s 0 1 0 26 fW 1 95 ms 0 1 1 27 fW 3 91 ms 1 0 0 28 fW 7 81 ms 1 0 1 29 fW 15 6 ms Other than above Setting prohibited Note Do not frequently clear the prescaler when...

Page 228: ...5005136 second fX 8 38 106 When fX 4 19 MHz frequency is used 28 213 221 0 5005136 second fX 4 19 106 When fXT 32 768 MHz frequency is used 1 214 214 0 50000 second fXT 32 768 103 When fX 10 0 MHz fr...

Page 229: ...operated at When operated at When operated at at fX 10 0 MHz fX 8 38 MHz fX 4 19 MHz fXT 32 768 kHz 0 0 0 24 1 fW 409 6 s 489 s 978 s 488 s 0 0 1 25 1 fW 819 2 s 978 s 1 96 ms 977 s 0 1 0 26 1 fW 1 64...

Page 230: ...www DataSheet4U com CHAPTER 10 WATCH TIMER 230 MEMO...

Page 231: ...Timer Inadvertent Program Loop Detection Time Inadvertent Program Loop When operated at Inadvertent Program Loop When operated at Detection Time fX 10 0 MHz Detection Time fX 10 0 MHz 212 1 fX 409 6...

Page 232: ...IMER 232 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Item Configuration Control register Timer clock select register...

Page 233: ...nal Bus Internal Bus fX 24 8 Bit Prescaler fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Selector 3 8 Bit Counter RUN Clear TMIF4 TMMK4 TCL22 RUN TCL21 TCL20 Timer Clock Select Register 2 Watchdog Timer...

Page 234: ...Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with an 8 bit memory manipulati...

Page 235: ...kHz 1 1 0 fX 210 9 8 kHz 1 1 1 fX 212 2 4 kHz TCL24 Watch Timer Count Clock Selection 0 fX 28 39 1 kHz 1 fXT 32 768 kHz TCL27 TCL26 TCL25 Buzzer Output Frequency Selection 0 Buzzer output disable 1 0...

Page 236: ...timer mode 2 Reset operation is activated upon generation of an overflow RUN Watchdog Timer Operation SelectionNote 3 0 Count stop 1 Counter is cleared and counting starts Notes 1 Once set to 1 WDTM3...

Page 237: ...kable interrupt request is generated according to the WDTM bit 3 WDTM3 value Watchdog timer can be cleared by setting RUN to 1 The watchdog timer continues operating in the HALT mode but it stops in t...

Page 238: ...ity The interval timer continues operating in the HALT mode but it stops in the STOP mode Thus set WDTM bit 7 RUN to 1 before the STOP mode is set clear the interval timer and then execute the STOP in...

Page 239: ...w the procedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bi...

Page 240: ...ontrol Registers The following two types of registers are used to control the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 Thi...

Page 241: ...ust be stopped first Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 TI0 16 bit timer event counter input pin 4 TM0 16 bit timer register 5 Values in...

Page 242: ...ion set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 12 4 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Ad...

Page 243: ...to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 Set to output mode Caution Buzzer output cannot be used if P36 output latch is set to 1 1...

Page 244: ...zer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory man...

Page 245: ...MHz or fXT 32 768 kHz Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TCL2 TCL27 TCL26 TCL25 TCL24 0 TCL22 TCL21 TCL20 FF42H 00H R W TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection 0 0 0 fX 24 6...

Page 246: ...ion set PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 3 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Ad...

Page 247: ...converter mode register ADM One channel of analog input is selected from ANI0 to ANI7 and A D conversion is carried out In the case of hardware start A D conversion operation stops when it terminates...

Page 248: ...r ADIS3 ADIS2 ADIS1 ADIS0 4 ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 3 ADM1 to ADM3 Sample and Hold Circuit Voltage Comparator Series Resistor String AVREF AVSS Successi...

Page 249: ...s resistor string is connected to among AVREF to AVSS and generates a voltage to be compared to the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to un...

Page 250: ...ies resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin Therefore if the output impedance of the reference voltage source is high this will result in parallel con...

Page 251: ...l the A D converter A D converter mode register ADM A D converter input select register ADIS 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion...

Page 252: ...tion Remark fX Main system clock oscillation frequency Symbol 7 6 5 4 3 2 1 0 Address When Reset R W ADM CS TRG FR1 FR0 ADM3 ADM2 ADM1 1 FF80H 01H R W ADM3 ADM2 ADM1 Analog Input Channel Selection 0 0...

Page 253: ...h is set for analog input with ADIS 2 On chip pull up resistor is not used for the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option regist...

Page 254: ...r string voltage tap and analog input is compared with a voltage comparator If the analog input is larger than 1 2 AVREF the MSB of SAR remains set If the input is smaller than 1 2 AVREF the MSB is re...

Page 255: ...eset 0 by software If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning A...

Page 256: ...VREF or AVREF AVREF ADCR 0 5 VIN ADCR 0 5 256 256 where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result reg...

Page 257: ...rts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result r...

Page 258: ...and terminated the next A D conversion operation starts immediately The A D conversion operation continues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again...

Page 259: ...me this current must be cut in order to minimize the overall system power dissipation In this example the power dissipation can be reduced if a low level is output to the output port in the standby mo...

Page 260: ...log input should be specified to the input mode When A D conversion is performed with any of pins ANI0 to ANI7 selected be sure not to execute a PORT1 input instruction while conversion is in progress...

Page 261: ...er to Figure 14 10 When the A D conversion is stopped the ADIF must be cleared before restarting Figure 14 10 A D Conversion End Interrupt Request Generation Timing 7 AVDD pin The AVDD pin is the anal...

Page 262: ...www DataSheet4U com CHAPTER 14 A D CONVERTER 262 MEMO...

Page 263: ...on a board High speed serial interface to be complianced with the NEC standard bus format Address and command information onto the serial bus 2 wire serial I O SCK0 SB0 or Enables to configure serial...

Page 264: ...h peripheral I O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface mode...

Page 265: ...of serial clock SCK0 and serial data bus SB0 or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the...

Page 266: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 PD78014 Subseries 266 Figure 15 2 Serial Bus Configuration Example with 2 Wire Serial I O VDD VDD Master CPU Slave SCK0 SB0 SB1 SCK0 SB0 SB1...

Page 267: ...ation Item Configuration Register Serial I O shift register 0 SIO0 Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus inte...

Page 268: ...ch Selector Selector P26 Output Latch P27 Output Latch Slave Address Register SVA SVAM Match Serial I O Shift Register 0 SIO0 Bus Release Command Acknowledge Detector Serial Clock Counter Serial Clock...

Page 269: ...gister does not be used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave addres...

Page 270: ...al generation It generates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight s...

Page 271: ...manipulation instruction RESET input sets TCL3 to 88H Remark TCL3 has functions to set the serial clock of serial interface channel 1 besides setting the serial clock of serial interface channel 0 2 S...

Page 272: ...8 39 1 kHz 1 1 0 1 fX 29 19 5 kHz Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Serial Interface Channel 1 Serial Clock Selection 0 1 1 0 fX 22 Note 0 1 1 1 fX 23 1 25 MHz 1 0 0 0 fX 24...

Page 273: ...in CMOS input input output output Note 3 Note 3 2 wire MSB P25 SB1 SCK0 1 1 0 0 0 0 1 serial I O CMOS N ch open drain N ch open mode input output input output drain Note 3 Note 3 SB0 P26 input output...

Page 274: ...After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is execut...

Page 275: ...ynchronization with the falling edge of SCK0 clock of transfer immediately after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 aft...

Page 276: ...AM 0 0 0 0 FF63H 00H R WNote 1 R W SVAM SVA Bit to be Used as Slave Address 0 Bit 0 to Bit 7 1 Bit 1 to Bit 7 R W SIC INTCSI0 Interrupt Factor SelectionNote 2 0 CSIIF0 is set 1 upon termination of ser...

Page 277: ...op mode 3 wire serial I O mode SBI mode 2 wire serial I O mode 15 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power dissipation can be reduced The serial...

Page 278: ...locked serial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting T...

Page 279: ...Note 2 SO0 SCK0 1 serial I O LSB Input CMOS CMOS mode output input output 1 0 SBI mode Refer to 15 4 3 SBI mode operation 1 0 2 wire serial I O mode Refer to 15 4 4 2 wire serial I O mode operation R...

Page 280: ...0H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance aut...

Page 281: ...on termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 15 8 3 Wire Serial I O Mode Timings The SO0 pin serves for CMOS output and gener...

Page 282: ...bus As shown in the figure MSB LSB can be read written in inverted form MSB LSB switching as the start bit can be specified with bit 2 CSIM02 of the serial operating mode register 0 CSIM0 Figure 15 10...

Page 283: ...e single master high speed serial bus Thus when making up a serial bus with two or more microcontrollers and peripheral ICs the number of ports to be used and the number of wires on the board can be d...

Page 284: ...master CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and s...

Page 285: ...and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address reception chip select ju...

Page 286: ...BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit d...

Page 287: ...determined as the bus release signal even if data is sent Therefore perform wiring carefully b Command signal CMD The command signal is generated when the SCK0 line is in high level a serial clock is...

Page 288: ...slave detects the condition and checks by hardware if 8 bit data matches its specified number the slave address When 8 bit data matches the slave address which means the slave is selected the slave co...

Page 289: ...dress Figure 15 17 Command Figure 15 18 Data 8 bit data following the command signal is defined as a command 8 bit data wihtout the command signal is defined as data How to use the command and data ca...

Page 290: ...tes the READY state The acknowledge signal is a one shot pulse synchronous with SCK0 falling whose position can be synchronized with SCK0 in any clock The sending side that has transferred 8 bit data...

Page 291: ...inates automatically to output the serial clock SCK0 when the busy signal is cleared The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state Cautio...

Page 292: ...1 N ch open drain CMOS input input output output 1 1 2 wire serial I O mode Refer to 15 4 4 2 wire serial I O mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generati...

Page 293: ...cuted When bus release signal REL is detected If SIO0 and SVA values do not match in address reception only if WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions...

Page 294: ...R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 At the falling edge of SCK0 clock immediately after the When acknowledge signal ACK is detected at the busy mode has been re...

Page 295: ...to set bits 0 to 3 to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag supports the INTCSI0 CSIE0 Bit 7 of the serial operating mode register 0 CSIM0 R W SVAM SVA Bit to be Used as Sl...

Page 296: ...lists various signals in SBI Figure 15 21 RELT CMDT RELD and CMDD Operations Master Figure 15 22 RELD and CMDD Operations Slave SIO0 SCK0 SB0 SB1 RELT CMDT RELD CMDD Slave address write to SIO0 Trans...

Page 297: ...HANNEL 0 PD78014 Subseries 297 Figure 15 23 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 SB0 SB1 ACKT D2 D1 D0 ACK ACK signal is output a period of one clock immediately...

Page 298: ...D0 ACK ACK signal is output at 9th clock When ACKE 1 at this point 1 2 7 8 9 SCK0 SB0 SB1 ACKE D2 D1 D0 ACK ACK signal is output a period of one clock immediately after setting If set during this per...

Page 299: ...ansfer start is instructed in BUSY SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1...

Page 300: ...ter Low level signal to be 1 ACKE 1 ACKD set Completion of reception signal ACK slave output to SB0 SB1 2 ACKT set during one clock period of SCK0 after completion of serial reception Busy signal Slav...

Page 301: ...ock to serial data bus data ACK signal instruction for of SCK0 Note 1 synchronization BUSY data write to SIO0 signal etc Address serial transfer command data are start instruction transferred with the...

Page 302: ...on The serial clock pin SCK0 and serial data bus pin SB0 SB1 have the following configurations a SCK0 Serial clock input output pin 1 Master CMOS and push pull output 2 Slave Schmitt input b SB0 SB1 S...

Page 303: ...ss to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt request...

Page 304: ...en determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 15 28 to 15 31 show data communication timing charts Shift op...

Page 305: ...sion INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 BUSY READY WUP 0 ACKT Set BUSY Clear CMDD Set CMDD Clear CMDD Set RELD Set Serial Reception INTCSI0 Generation ACK...

Page 306: ...r Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 C7 C6 C5 C4 C3 C2 C1 C0 BUSY READY Command analysis ACKT Set BUSY Clear CMDD Set Serial Reception INTCSI0 Generation ACK O...

Page 307: ...rocessing Receiver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY ACKT Set BUSY Clear Serial Reception INTCSI0 Generation ACK Output BUS...

Page 308: ...4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation ACK Data FFH Write to SIO0 Receive Data Processing Seri...

Page 309: ...utput be sure to carry out the following settings before serial transfer of the 1st byte after RESET input 1 Set the P25 and P26 output latches to 1 2 Set bit 0 RELT of the serial bus interface contro...

Page 310: ...l register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to 0 e The bus release signal or the command signal is acknowledged when the SCK0 line is in high level and the SB0 SB1 line changes...

Page 311: ...serial I O mode is set with the serial operating mode register 0 CSIM0 the serial bus interface control register SBIC and the interrupt timing specification register SINT a Serial operating mode regi...

Page 312: ...ch open drain N ch open input output input output drain Note 2 Note 2 SB0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 3 0 Interrupt...

Page 313: ...0H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance aut...

Page 314: ...ransfer 1 CSIIF0 is set 1 upon bus release detection R CLD SCK0 P27 Pin LevelNote 2 0 Low Level 1 High Level Notes 1 Bit 6 CLD is a Read Only bit 2 When CSIE0 0 CLD becomes 0 Caution Be sure to set bi...

Page 315: ...y and the interrupt request flag CSIIF0 is set Figure 15 33 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus serves for N ch open drain input output and thus it must...

Page 316: ...g two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock is stopped or SCK0 is at high level after 8 bit serial transfer Cautions 1 If CSIE0 is set...

Page 317: ...to have been carried out If it is 0 a transmit error is judged to have occurred 15 4 5 SCK0 P27 pin output manipulation Because the SCK0 P27 pin incorporates an output latch static output is also pos...

Page 318: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 PD78014 Subseries 318 MEMO...

Page 319: ...and 1 Serial Transfer Mode Channel 0 Channel 1 3 wire serial I O Clock selection fX 22Note fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 external clock TO2 output clock Transfer method MSB LSB switchable...

Page 320: ...before SBI mode SCK0 SB0 or Enables configuration of serial bus with two signal SB1 lines thus even when connected to some microcontrollers the number of ports can be cut and wiring and routing on a...

Page 321: ...tion of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface...

Page 322: ...lines of the serial clock SCK0 and serial data bus SB0 or SB1 This mode supports any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the h...

Page 323: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 PD78014Y Subseries 323 Figure 16 2 Serial Bus Configuration Example with 2 Wire Serial I O VDD VDD Master CPU Slave SCK0 SB0 SB1 SCK0 SB0 SB1...

Page 324: ...ata bus SDA0 or SDA1 This mode complies with the NEC I2C bus format In this mode the transmitter outputs three kinds of data onto the serial data bus start condition data and stop condition The receiv...

Page 325: ...ation Item Configuration Register Serial I O shift register 0 SIO0 Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus inte...

Page 326: ...or Selector P26 Output Latch P27 Output Latch Slave Address Register SVA SVAM Match Serial I O Shift Register 0 SIO0 Bus Release Command Acknowledge Detector Serial Clock Counter Serial Clock Control...

Page 327: ...tion of a slave device to the serial bus SVA is set with an 8 bit memory manipulation instruction This register does not be used in the 3 wire serial I O mode The master device outputs a slave address...

Page 328: ...clock supply to the serial I O shift register 0 SIO0 When the internal system clock is used the circuit also controls clock output to the SCK0 SCL P27 pin 6 Interrupt request signal generator This ci...

Page 329: ...ftware ACK information is generated by the receiving side thus ACKE should be set to 0 disable 1 1 0 An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK inf...

Page 330: ...is register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memor...

Page 331: ...fX 26 156 kHz 1 0 1 1 fX 211 4 9 kHz fX 27 78 1 kHz 1 1 0 0 fX 212 2 4 kHz fX 28 39 1 kHz 1 1 0 1 fX 213 1 2 kHz fX 29 19 5 kHz Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Serial Inte...

Page 332: ...nput output drain Note 4 Note 4 Mode SB0 SDA0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 5 0 Interrupt request signal generation wit...

Page 333: ...ve address register SVA not equal to serial I O shift register 0 SIO0 data 1 Slave address register SVA equal to serial I O shift register 0 SIO0 data R W CSIE0 Serial Interface Channel 0 Operation Co...

Page 334: ...0 Set Conditions CMDD 1 When transfer start instruction is executed When command signal CMD is detected in the SBI mode When bus release signal REL is detected When stop condition is detected in the...

Page 335: ...o 0 after acknowledge signal output Used in reception with 9 clock wait mode selected R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 At the falling edge of SCK0 clock immed...

Page 336: ...state after output In the case of slave device makes SCL output low to request waits pulses are input R W WREL Wait State Cancellation Control 0 Wait state has been cancelled 1 Cancels wait state Aut...

Page 337: ...nsfer 1 CSIIF0 is set to 1 upon stop condition detection in the I2 C bus mode or termination of serial interface in the SBI mode R CLD SCK0 SCL P27 Pin LevelNote 2 0 Low level 1 High level Figure 16 8...

Page 338: ...rial I O mode SBI mode 2 wire serial I O mode I2C Inter IC bus mode 16 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power dissipation can be reduced The s...

Page 339: ...locked serial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting T...

Page 340: ...ut input output 1 0 SBI mode Refer to 16 4 3 SBI mode operation 1 1 2 wire serial I O mode Refer to 16 4 4 2 wire serial I O mode operation or I2 C bus mode Refer to 16 4 5 I2 C bus mode operation R W...

Page 341: ...egister SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0...

Page 342: ...pon termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 16 9 3 Wire Serial I O Mode Timings The SO0 pin serves for CMOS output and gene...

Page 343: ...bus As shown in the figure MSB LSB can be read written in inverted form MSB LSB switching as the start bit can be specified with bit 2 CSIM02 of the serial operating mode register 0 CSIM0 Figure 16 1...

Page 344: ...single master high speed serial bus Thus when making up a serial bus with two or more microcomputers and peripheral ICs the number of ports to be used and the number of wires on the board can be decr...

Page 345: ...master CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and...

Page 346: ...d into addresses commands and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address...

Page 347: ...BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit d...

Page 348: ...determined as the bus release signal even if data is sent Therefore perform wiring carefully b Command Signal CMD The command signal is generated when the SCK0 line is in high level a serial clock is...

Page 349: ...slave detects the condition and checks by hardware if 8 bit data matches its specified number the slave address When 8 bit data matches the slave address which means the slave is selected the slave co...

Page 350: ...ss Figure 16 18 Command Figure 16 19 Data 8 bit data following the command signal is defined as a command 8 bit data without the command signal is defined as data How to use the command and data can b...

Page 351: ...SCK0 in 9th clock Remark The broken line indicates the READY state The acknowledge signal is a one shot pulse synchronous with SCK0 falling whose position can be synchronized with SCK0 in any clock Th...

Page 352: ...es automatically to output the serial clock SCK0 when the busy signal is cleared The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state Caution In...

Page 353: ...put 1 1 2 wire serial I O mode Refer to 16 4 4 2 wire serial I O mode operation or I2 C bus mode Refer to 16 4 5 I2 C bus mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request sign...

Page 354: ...us Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When bus release signal REL is detected in the SBI mode If SIO0 and SVA values do not mat...

Page 355: ...on Clear Conditions ACKD 0 Set Conditions ACKD 1 In the SBI mode at the falling edge of SCK0 clock When acknowledge signal ACK is detected at the immediately after the busy mode has been released risi...

Page 356: ...CSIIF0 is set 1 upon bus release detection in SBI mode R CLD SCK0 SCL P27 Pin LevelNote 3 0 Low Level 1 High Level c Interrupt timing specification register SINT SINT is set with a 1 bit or 8 bit memo...

Page 357: ...6 5 lists various signals in SBI Figure 16 22 RELT CMDT RELD and CMDD Operations Master Figure 16 23 RELD and CMDD Operations Slave SIO0 SCK0 SB0 SB1 RELT CMDT RELD CMDD Slave address write to SIO0 Tr...

Page 358: ...EL 0 PD78014Y Subseries 358 Figure 16 24 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 SB0 SB1 ACKT D2 D1 D0 ACK ACK signal is output during a period of one clock immediat...

Page 359: ...D0 ACK ACK signal is output at 9th clock When ACKE 1 at this point 1 2 7 8 9 SCK0 SB0 SB1 ACKE D2 D1 D0 ACK ACK signal is output a period of one clock immediately after setting If set during this per...

Page 360: ...rt is instructed in BUSY Figure 16 27 BSYE Operation SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer St...

Page 361: ...transmit data is a command Acknowledge Master Low level signal to be 1 ACKE 1 ACKD set Completion of reception signal ACK slave output to SB0 SB1 2 ACKT set during one clock period of SCK0 after compl...

Page 362: ...of slave A7 to A0 in synchronization with device on the serial bus SCK0 after output of REL and CMD signals Address Master 8 bit data to be transferred Instruction messages to C7 to C0 in synchronizat...

Page 363: ...us line has an N ch open drain output an external pull up resistor is necessary Figure 16 28 Pin Configuration Caution Because the N ch open drain output must be set to high impedance at the time of d...

Page 364: ...dress to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt reque...

Page 365: ...en determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 16 29 to 16 32 show data communication timing charts Shift op...

Page 366: ...sion INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 BUSY READY WUP 0 ACKT Set BUSY Clear CMDD Set CMDD Clear CMDD Set RELD Set Serial Reception INTCSI0 Generation ACK...

Page 367: ...r Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 C7 C6 C5 C4 C3 C2 C1 C0 BUSY READY Command analysis ACKT Set BUSY Clear CMDD Set Serial Reception INTCSI0 Generation ACK O...

Page 368: ...Processing Receiver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY ACKT Set BUSY Clear Serial Reception INTCSI0 Generation ACK Output BU...

Page 369: ...4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation ACK Data FFH Write to SIO0 Receive Data Processing Seria...

Page 370: ...ot lost When the busy state is cleared and SB0 or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatically stops and the interrup...

Page 371: ...USY release indication If WUP 1 is set by mistake during this period BUSY will not be released Thus after releasing BUSY be sure to check that the SB0 SB1 has become high level before setting WUP 1 d...

Page 372: ...input output SB0 or SB1 Figure 16 33 Example of Serial Bus Configuration with 2 Wire Serial I O 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIM0 th...

Page 373: ...output input output drain Note 2 Note 2 bus mode SB0 SDA0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 3 0 Interrupt request signal g...

Page 374: ...0H Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0...

Page 375: ...AT1 WAT0 FF63H 00H R WNote 1 R W SIC INTCSI0 Interrupt Factor Selection 0 CSIIF0 is set 1 upon termination of serial channel 0 transfer 1 CSIIF0 is set 1 upon bus release detection R CLD SCK0 SCL P27...

Page 376: ...ally and the interrupt request flag CSIIF0 is set Figure 16 34 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus serves for N ch open drain input output and thus it m...

Page 377: ...bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched...

Page 378: ...2C bus specification the master sends start condition data and stop condition signals to slave devices through the serial data bus Slave devices automatically detect and distinguish the type of signal...

Page 379: ...ration Therefore CPUs other than the selected slave device on the I2C bus can perform independent operations during the serial communication d Acknowledge signal ACK control function The master device...

Page 380: ...om the master device a Start condition When the SDA0 SDA1 pin level is changed from high to low while the SCL pin is high this transition is recognized as the start condition signal This start conditi...

Page 381: ...device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master device sends a start condition or stop condition...

Page 382: ...he sending side device receives the acknowledge signal which means a successful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that t...

Page 383: ...asing operation of slave devices see section 16 4 6 Cautions on use of I2C bus mode Figure 16 43 Wait Signal a Wait of 8 Clock Cycles b Wait of 9 Clock Cycles D2 D1 D0 ACK D7 Output by manipulating AC...

Page 384: ...outputNote 2 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 R W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operating Start Bit SI0 SB0 SDA0 SO0 SBI SDA1 SCK0 SCL 04 03 02 Mo...

Page 385: ...transfer in all modes 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 when the SBI mode is used or when CMDD 1 when the I2 C bus mode is used matche...

Page 386: ...itions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When start condition is detected in the I2 C bus mode When stop condition is detected in the I2 C bus mode When CSIE0 0...

Page 387: ...edge of SCL automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait mode selected R ACKD Acknowledge Detection Clea...

Page 388: ...input 1 1 Used in the I2 C bus mode 9 clock wait Generates interrupt service request at rising edge of 9th SCL clock cycle In the case of master device makes SCL output low to enter wait state after...

Page 389: ...termination of serial interface channel 0 transfer 1 CSIIF0 is set to 1 upon stop condition detection in I2 C bus mode R CLD SCK0 SCL P27 Pin LevelNote 2 0 Low level 1 High level Notes 1 When using t...

Page 390: ...ial communication SCL output of various signals write instruction set Note 3 synchronization signal Address Master 7 bit data synchronized with to SIO0 when Indicates address value A6 to A0 SCL immedi...

Page 391: ...ata bus require the external pull up resistors to be output by N ch open drain Figure 16 44 Pin Configuration Caution Because the N ch open drain output must be set to high impedance at the time of da...

Page 392: ...SDA1 status during transmission is also taken into the serial I O shift register 0 SIO0 of the transmitting device a Comparison of SIO0 data before and after transmission In this case a transmission e...

Page 393: ...art Condition to Address Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Address SIO0 Addr...

Page 394: ...Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Data SIO0 Data L H L L L L L 2 D7 1 3 4 5...

Page 395: ...ns described in 16 4 7 2 Avoidance Refer to 16 4 7 2 Limitation when used as the slave device in the I2C bus mode for details Master device operation Transfer line Slave device operationNote Write SIO...

Page 396: ...Start Condition to Address Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Address SIO0 F...

Page 397: ...Master device operation Transfer line Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 FFH SIO0 FFH L H L H L L L 2 D7 1 3 4 5 6 7 8 9 1 2 3 4 5 D6 D5...

Page 398: ...k Wait 3 3 c Stop Condition Master device operation Transfer line Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 FFH SIO0 Address H L L L 2 D6 1 3 4 5...

Page 399: ...on 2 Because the N ch open drain output must be set to high impedance at the time of data reception write FFH to the serial I O shift register 0 SIO0 in advance However when wake up function is used t...

Page 400: ...a start condition signal Set 1 in bit 3 CLC of the interrupt timing specification register SINT to drive the SCL pin high After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains...

Page 401: ...rogram At this time control the low level width a in Figure 16 48 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction In add...

Page 402: ...use if SCL line is being high impedance state during execution of write instruction to the SIO0 until next instruction execution SIO0 does not start the operation Therefore receive the data by manipul...

Page 403: ...wake up function 16 4 7 Restrictions on use of I2C bus mode The PD78014Y subseries devices have the following restrictions 1 Restriction on master device operation in the I2C bus mode Applied device P...

Page 404: ...ing FFH into SIO0 of the PD78014Y Subseries device if the master device drives the SCL line to high level to output the start condition or stop condition signals then SIO0 shift operation is carried o...

Page 405: ...l operating mode register 0 CSIM0 and serial I O shift register 0 SIO0 of the slave device to 1 and FFH respectively before a stop condition signal is output Then the wake up function is enabled for t...

Page 406: ...IC The SCK0 SCL P27 pin output should be manipulated as described below 1 In the 3 wire serial I O mode and the 2 wire serial I O mode Output level of SCK0 SCL P27 pin is manipulated by the P27 output...

Page 407: ...T by executing the bit manipulation instruction Figure 16 51 SCK0 SCL P27 Pin Configuration Remarks 1 This figure shows the relationship between each signal and does not show the internal circuit 2 CL...

Page 408: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 PD78014Y Subseries 408 MEMO...

Page 409: ...the data transfer processing time is fast The start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB so it is possible to connect to devices of any start bit 3 wire seri...

Page 410: ...ration Item Configuration Register Serial I O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP Control register Timer clock select register 3 TCL3 Serial operating mode regis...

Page 411: ...1 P22 PM22 DIR DIR Internal Bus Serial I O Shift Register 1 SIO1 Hand shake P22 Output Latch Q R S Clear ARLD Serial Clock Counter SIO1 Write Internal Bus Timer Clock Select Register 3 TCL37 TCL36 TCL...

Page 412: ...O1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register st...

Page 413: ...ster 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface ch...

Page 414: ...ation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection 0 1 1 0 fX 22 Note 0 1 1 1 fX 23 1 25 MHz 1 0 0 0...

Page 415: ...l I O mode 1 3 wire serial I O mode with automatic transmit receive function DIR Start Bit SI1 Pin Function SO1 Pin Function 0 MSB SI1 P20 Input SO1 CMOS output 1 LSB CSIE CSIM PM20 P20 PM21 P21 PM22...

Page 416: ...This register sets automatic receive enable disable the operating mode strobe output enable disable busy input enable disable error check enable disable and displays automatic transmit receive executi...

Page 417: ...obe output disable 1 Strobe output enable R TRF Status of Automatic Transmit Receive FunctionNote 2 0 Detection of termination of automatic transmission reception This bit is set to 0 upon suspension...

Page 418: ...h the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol 7 6 5 4 3 2 1 0 Address When Reset R W CSIM1 CSIE1...

Page 419: ...0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is used Set bit 7 RE of ADTC to 0 Remark don t care PMxx Port mode register Pxx Output latch of...

Page 420: ...clock SCK1 The transmit data is held in the SO1 latch and is output from the SO1 pin The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1 Upon termination of 8 bit tra...

Page 421: ...write to SIO1 The SIO1 shift order remains unchanged Thus switch the MSB LSB start bit before writing data to the shift register 4 Start of transfer A serial transfer is started by setting transfer d...

Page 422: ...tored in the RAM by the set number of bytes Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD co...

Page 423: ...0 SO1 P21 SCK1 P22 1 11 1 Operation Operation Pin Function Pin Function Pin Function Control Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Operation stop Clear P20 P21 P22 0 CMOS CMOS CMOS input output in...

Page 424: ...ror in automatic transmission reception This bit is set to 0 when data is written to SIO1 1 Error occurred in automatic transmission reception R W ERCE Error Check Control of Automatic Transmit Receiv...

Page 425: ...gister ADTC to 1 3 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the wri...

Page 426: ...ormal input output ports Figure 17 7 shows the basic transmit receive mode operation timings and Figure 17 8 shows the operation flowchart In addition Figure 17 9 shows the buffer RAM operation in 6 b...

Page 427: ...control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 start trigger...

Page 428: ...e transmission reception point Refer to Figure 17 9 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the f...

Page 429: ...mission reception point c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 R4 Transmit data 5 R5 Transmit data 6 R6 FADFH FAC0H FAC5H Receive...

Page 430: ...can be used as normal input output ports Figure 17 10 shows the basic transmission mode operation timings and Figure 17 11 shows the operation flowchart In addition Figure 17 12 shows the buffer RAM o...

Page 431: ...c data transmit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any dat...

Page 432: ...T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission point Refer to Figure 17 12 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer...

Page 433: ...transmission point c Completion of transmission Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 2 0 SIO1 ADTP CSIIF...

Page 434: ...sy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as normal input output ports The repeat transmission mode operation timing is shown in Figure 17 13 an...

Page 435: ...rial I O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 Start trig...

Page 436: ...M to SIO1 ii Upon completion of transmission of 6 bytes Refer to Figure 17 15 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The ADTP is set with the i...

Page 437: ...of transmission of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 0 0 SIO1 AD...

Page 438: ...nsmission reception can be restarted and the remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 If the HALT instruction is...

Page 439: ...the slave device to the BUSY P24 pin The master device samples the input busy signal in synchronization with the falling of the serial clock Even if the busy signal becomes active while 8 bit data is...

Page 440: ...ignal was sampled To accurately release waiting the slave must keep the busy signal inactive at least for the duration of 1 5 clock Figure 17 19 shows the timing of the busy signal and releasing the w...

Page 441: ...isfied Bit 5 ATE of the serial operation mode register 1 CSIM1 is set to 1 Bit 2 STRB of the automatic data transmission reception control register ADTC is set to 1 Usually the busy control and strobe...

Page 442: ...n 2 clocks The master samples the busy signal in synchronization of the falling of the leading side of the serial clock If a bit shift does not occur all the eight serial clocks that have been sampled...

Page 443: ...performed by an internal clock since the read write operations from to the buffer RAM are done in parallel with CPU processing the interval depends on the CPU processing at the moment of serial clock...

Page 444: ...nal clock performs In this case the interval is determined as follows by CPU processing Table 17 2 Interval by CPU Processing in Internal Clock Operation TSCK 1 fSCK fSCK Serial clock frequency TCPU 1...

Page 445: ...mit receive function is performed by an external clock When bit 1 CSIM11 of the serial operation mode register 1 CSIM1 is cleared to 0 the external clock performs When the automatic data transmit rece...

Page 446: ...www DataSheet4U com CHAPTER 17 SERIAL INTERFACE CHANNEL 1 446 MEMO...

Page 447: ...interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H Multiple high priority interrupts can be applied to low priority interrupts If two o...

Page 448: ...SI0 End of serial interface channel 0 transfer Internal 000EH B 6 INTCSI1 End of serial interface channel 1 transfer 0010H 7 INTTM3 Reference time interval signal from watch 0012H timer 8 INTTM0 16 bi...

Page 449: ...rrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus MK IE PR ISP IF Interrupt Request Priority Control Circuit Vector Table Address Generator Stan...

Page 450: ...IF Interrupt request flag IE Interrupt enabled flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag Internal Bus MK IE PR ISP IF Interrupt Request Priority Control Circuit...

Page 451: ...es a listing of interrupt request flags interrupt mask flags and priority specify flag names corresponding to interrupt request sources Table 18 2 Various Flags Corresponding to Interrupt Request Sour...

Page 452: ...th a 16 bit memory manipulation instruction RESET input sets these registers to 00H Figure 18 2 Interrupt Request Flag Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W IF0L TMIF3 CSIIF1 C...

Page 453: ...PMK3 PMK2 PMK1 PMK0 TMMK4 FFE4H FFH R W 7 6 5 4 3 2 1 0 MK0H 1 1 WTMKNote 1 ADMK TMMK2 TMMK1 TMMK0 FFE5H FFH R W MK Interrupt Servicing Standby Mode Control 0 Interrupt servicing standby mode clear en...

Page 454: ...ter PR0 they are set with a 16 bit memory manipulation instruction RESET input sets these registers to FFH Figure 18 4 Priority Specify Flag Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R...

Page 455: ...ss When Reset R W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 0 0 FFECH 00H R W ES11 ES10 INTP0 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges E...

Page 456: ...18 6 Sampling Clock Select Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SCS 0 0 0 0 0 0 SCS1 SCS0 FF47H 00H R W SCS1 SCS0 INTP0 Sampling Clock Selection 0 0 fX 2N 1 0 1 Setting prohib...

Page 457: ...s detected a When input is less than the sampling cycle tSMP b When input is equal to or twice the sampling cycle tSMP c When input is twice or more than the sampling cycle tSMP tSMP INTP0 PIF0 Sampli...

Page 458: ...to a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The con...

Page 459: ...into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable inter...

Page 460: ...ag Start WDTM4 1 with watchdog timer mode selected Overflow in WDT WDTM3 0 with non maskable interrupt request selected Interrupt request generation WDT interrupt servicing Interrupt control register...

Page 461: ...on maskable interrupt servicing program execution NMI request 2 NMI request 1 Execution of one instruction Main Routine NMI request 1 executed NMI request 2 kept pending Pending NMI request 2 is servi...

Page 462: ...Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged fi...

Page 463: ...n Interrupt with low priority is being serviced Start IF 1 MK 0 PR 0 Any simul taneously generated PR 0 interrupt requests Any simul taneously generated high priority interrupt requests IE 1 ISP 1 Int...

Page 464: ...quest Acknowledge Timing Maximum Time Remark 1 clock 1 fCPU fCPU CPU clock CPU Processing IF PR 1 IF PR 0 Instruction Instruction PSW PC Save Jump to Interrupt Servicing Interrupt Servicing Program 12...

Page 465: ...pt nesting is controlled by using the programmable priority If an interrupt with the same level of priority as or the higher priority than the interrupt currently serviced occurs that interrupt can be...

Page 466: ...R 0 High priority level PR 1 Low priority level IE 0 Interrupt request acknowledge disabled During interrupt INTxx servicing two interrupt requests INTyy and INTzz are acknowledged and a multiple inte...

Page 467: ...in interrupt INTxx servicing an EI instruction is not issued interrupt request INTyy is not acknowledged and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after...

Page 468: ...MK0L MK0H PR0L PR0H and INTM0 registers Caution BRK instruction is not an interrupt request reserve instruction described above However in a software interrupt started by the execution of BRK instruct...

Page 469: ...e 18 5 Basic configuration is shown in Figure 18 17 Table 18 5 Test Input Source Figure 18 17 Basic Configuration of Test Function IF Test Input Flag MK Test Mask Flag 18 5 1 Test function control reg...

Page 470: ...W IF0H 0 0 WTIF 0 ADIF TMIF2 TMIF1 TMIF0 FFE1H 00H R W WTIF Watch timer overflow detection flag 0 Non detection 1 Detection Caution Be sure to set bits 4 6 and 7 to 0 2 Interrupt mask flag register 0H...

Page 471: ...se signal is generated if it is not masked by the interrupt mask flag WTMK By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer the watch function can be effected 2...

Page 472: ...www DataSheet4U com CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 472 MEMO...

Page 473: ...AD0 to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 19 2...

Page 474: ...sion mode when MM2 to MM0 100 256 bytes expansion mode when MM2 to MM0 011 Single chip mode SFR Internal High speed RAM Reserved Buffer RAM Reserved Full address mode when MM2 to MM0 111 16 Kbytes exp...

Page 475: ...56 bytes expansion mode when MM2 to MM0 011 Single chip mode SFR Internal High speed RAM Reserved Buffer RAM Reserved Full address mode when MM2 to MM0 111 16 Kbytes expansion mode when MM2 to MM0 101...

Page 476: ...67 Pins Condition Expansion Mode Selection P40 to P47 P50 to P53 P54 P55 P56 P57 P64 to P67 0 0 0 Single chip mode Port Input Port mode 0 0 1 mode Output 0 1 1 Memory 256 bytes AD0 to AD7 Port mode P6...

Page 477: ...t output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait function is not used the WAIT pin can be used as an input output port During inter...

Page 478: ...When with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 Low order address Instruction code High order address ASTB RD AD0 to AD7 A8 to A15 Internal wait s...

Page 479: ...tup b When with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 Low order address Read data High order address ASTB RD AD0 to AD7 A8 to A15 Internal wait sig...

Page 480: ...n with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB WR AD0 to AD7 A8 to A15 Hi Z Low order address Write data High order address ASTB WR AD0 to AD7 A8 to A15 Internal wait signal...

Page 481: ...Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 WR Low order address Read data Write data High order address ASTB WR AD0 to AD7 A8 to A15 Internal wait sign...

Page 482: ...19 7 Example of Memory Connection with PD78014 Caution At the external memory read modify write timing the time from RD signal rising to write data output is very short so that the write data sometime...

Page 483: ...ffective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a...

Page 484: ...l the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H Therefore...

Page 485: ...Operation enabled Operation stop 8 bit timer event counter Operation enabled Operation enabled when TI1 and TI2 are selected for the count clock Watchdog timer Operation enabled Operation stop A D con...

Page 486: ...rupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When branched to the vector 16 5 to 17 5 clocks When not branched to the vector 4 5 to 5 5 clocks b Cle...

Page 487: ...ce execution 1 HALT mode hold Non maskable interrupt request Interrupt service execution Test input 0 Next address instruction execution 1 HALT mode hold RESET input Reset processing Remark don t care...

Page 488: ...al A8 to A15 Status before STOP instruction execution is held Expansion ASTB Low level WR RD High level WAIT High impedance 20 2 2 STOP mode 1 STOP mode set and operating status The STOP mode is set b...

Page 489: ...ext address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby sta...

Page 490: ...pt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 STOP mode hold Test input 0 Next address instruction execution 1 STOP mode hold RESET input...

Page 491: ...tabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 218 fX The rese...

Page 492: ...High Impedance Reset Period Oscillation Stop Oscillation Stabilization Time Wait X1 Watchdog Timer Overflow Internal Reset Signal Port Pin Normal Operation Normal Operation Reset Processing High Imped...

Page 493: ...ct register OSTS 04H 16 bit timer event counter Timer register TM0 0000H Compare register CR00 Undefined Capture register CR01 Undefined Clock select register TCL0 00H Mode control register TMC0 00H O...

Page 494: ...ster SVA Undefined Automatic data transmit receive control register ADTC 00H Automatic data transmit receive address pointer ADTP 00H Interrupt timing specify register SINT 00H A D converter Mode regi...

Page 495: ...between PD78P014 78P014Y and Mask ROM Version Note When RESET is input the internal PROM capacity is set to 32 Kbytes internal high speed RAM capacity to 1024 bytes Caution The noise resistance and no...

Page 496: ...tting prohibited RAM2 RAM1 RAM0 Internal High Speed RAM Capacity Selection 0 0 0 768 bytes 0 0 1 640 bytes 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes 1 0 1 Setting prohibited 1 1 0 1024 bytes 1 1...

Page 497: ...is applied to the VPP pin and a low level signal is applied to the RESET pin the PD78P014 and 78P014Y are set to the PROM programming mode This is one of the operating modes shown in Table 22 3 below...

Page 498: ...lse active low to the CE pin 6 Verify mode If written proceed to step 8 If not written repeat steps 4 through 6 If you repeat 25 times and it can t be written proceed to 7 7 Stop the write operation a...

Page 499: ...7 Last Address Start Supply Power Voltage Supply Initial Address Supply Write Data Supply Program Pulse Verify Mode Additional Write 3Xms pulse Increment Address Last Address End of Write Defective d...

Page 500: ...to the VPP pin Unused pins are handled as shown in 1 5 or 2 5 Pin Configurations Top View 2 PROM programming mode 2 Supply 5 V to the VDD and VPP pins 3 Input address of data to be read to pins A0 to...

Page 501: ...amp If a filter has been attached to the ultraviolet ray lamp remove the filter before erasing 22 4 Opaque Film on Erasure Window for PD78P014DW 78P014YDW When erasing EPROM contents be sure to cover...

Page 502: ...www DataSheet4U com CHAPTER 22 PD78P014 78P014Y 502 MEMO...

Page 503: ...23 INSTRUCTION SET The instruction sets for the PD78014 and 78014Y Subseries are described in the following pages For the details of operations and mnemonics instruction codes of each instruction ref...

Page 504: ...er function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Methods Identifier Descrip...

Page 505: ...xiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in pa...

Page 506: ...m DE A A HL 1 8 10 2n A HL HL A 1 8 10 2m HL A A HL byte 2 16 18 2n A HL byte HL byte A 2 16 18 2m HL byte A A HL B 1 12 14 2n A HL B HL B A 1 12 14 2m HL B A A HL C 1 12 14 2n A HL C HL C A 1 12 14 2...

Page 507: ...2 12 16 saddrp AX AX sfrp 2 16 AX sfrp sfrp AX 2 16 sfrp AX AX rp Note 4 1 8 AX rp rp AX Note 4 1 8 rp AX AX addr16 3 20 24 4n AX addr16 addr16 AX 3 20 24 4m addr16 AX XCHW AX rp Note 4 1 8 AX rp Note...

Page 508: ...ration A r Note 3 2 8 A CY A r r A 2 8 r CY r A A saddr 2 8 10 A CY A saddr A addr16 3 16 18 2n A CY A addr16 A HL 1 8 10 2n A CY A HL A HL byte 2 16 18 2n A CY A HL byte A HL B 2 16 18 2n A CY A HL...

Page 509: ...r byte 3 12 16 saddr CY saddr byte CY ration A r Note 3 2 8 A CY A r CY r A 2 8 r CY r A CY A saddr 2 8 10 A CY A saddr CY A addr16 3 16 18 2n A CY A addr16 CY A HL 1 8 10 2n A CY A HL CY A HL byte 2...

Page 510: ...g tion Note 1 Note 2 Z AC CY Group 8 bit XOR A byte 2 8 A A byte Ope saddr byte 3 12 16 saddr saddr byte ration A r Note 3 2 8 A A r r A 2 8 r r A A saddr 2 8 10 A A saddr A addr16 3 16 18 2n A A addr...

Page 511: ...Accumulator after Subtract Bit MOV1 CY saddr bit 3 12 14 CY saddr bit Manipu CY sfr bit 3 14 CY sfr bit lation CY A bit 2 8 CY A bit CY PSW bit 3 14 CY PSW bit CY HL bit 2 12 14 2n CY HL bit saddr bit...

Page 512: ...CY CY HL bit SET1 saddr bit 2 8 12 saddr bit 1 sfr bit 3 16 sfr bit 1 A bit 2 8 A bit 1 PSW bit 2 12 PSW bit 1 HL bit 2 12 16 2n 2m HL bit 1 CLR1 saddr bit 2 8 12 saddr bit 0 sfr bit 3 16 sfr bit 0 A...

Page 513: ...C CY Group Call CALL addr16 3 14 SP 1 PC 3 H SP 2 PC 3 L Return PC addr16 SP SP 2 CALLF addr11 2 10 SP 1 PC 2 H SP 2 PC 2 L PC15 11 00001 PC10 0 addr11 SP SP 2 CALLT addr5 1 12 SP 1 PC 1 H SP 2 PC 1 L...

Page 514: ...6 PC PC 3 jdisp8 if A bit 0 PSW bit addr16 4 22 PC PC 4 jdisp8 if PSW bit 0 HL bit addr16 3 20 22 2n PC PC 3 jdisp8 if HL bit 0 BTCLR saddr bit addr16 4 20 24 PC PC 4 jdisp8 if saddr bit 1 then reset...

Page 515: ...saddr 0 CPU SEL RBn 2 8 RBS1 0 n Control NOP 1 4 No Operation EI 2 12 IE 1 Enable Interrupt DI 2 12 IE 0 Disable Interrupt HALT 2 12 Set HALT Mode STOP 2 12 Set STOP Mode Notes 1 When the internal hig...

Page 516: ...heet4U com CHAPTER 23 INSTRUCTION SET 516 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH...

Page 517: ...ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV...

Page 518: ...W addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None...

Page 519: ...ions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound instruction BT BF...

Page 520: ...www DataSheet4U com CHAPTER 23 INSTRUCTION SET 520 MEMO...

Page 521: ...ytes PD78015F 1024 bytes PD78016F 1024 bytes PD78018F 1024 bytes PD78P018F 1024 bytes Internal expansion RAM size None PD78011F None PD78012F None PD78013F None PD78014F None PD78015F 512 bytes PD7801...

Page 522: ...signal from falling edge of SCK0 following acknowledge signal in SBI mode Automatic data transmission None Provided reception interval specification register ADTI Package 64 pin plastic shrink DIP 64...

Page 523: ...B DEVELOPMENT TOOLS 523 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78014 and 78014Y Subseries Figure B 1 shows the dev...

Page 524: ...r Host machine PC or EWS Language processing software Target system Embedded software Real time OS OS Fuzzy inference development support system In circuit emulator Emulation probe Emulation board Int...

Page 525: ...A78K0 CC78K 0 This is a program to convert a program written in C language into an object code executable with C Compiler Package a microcontroller Use CC78K 0 C compiler package in combination with R...

Page 526: ...Y and is connected PA 78P014GC to the PG 1500 PROM programmer adapter PA 78P014CW 64 pin plastic shrink DIP CW type PA 78P014GC 64 pin plastic QFP GC AB8 type Remark Part number changes by the host ma...

Page 527: ...in circuit emulator for debugging hardware and or software when a system is In circuit emulator developed with 78K 0 Series devices This emulator is designed to be used with the For screen debugger sc...

Page 528: ...ality will thus be improved This is used together with the separately sold device file DF78014 Part Number S SM78K0 B 3 2 Software 1 3 Remark Part number changes by the host machine or OS to be used S...

Page 529: ...orating function extension modules such as task debugger and system performance analyzer This is used together with the separately sold device file DF78014 Part Number S ID78K0 Host Machine Operating...

Page 530: ...sed together with the separately sold device file RA78K 0 CC78K 0 SM78K0 ID78K0 SD78K 0 Part Number S DF78014 Host Machine Operating System Supply Medium 5A13 PC 9800 series MS DOS 3 5 inch 2HD 5A10 V...

Page 531: ...0 VNote to 6 2 VNote B 4 OS for IBM PC The following OSs for IBM PC are supported When operating SM78K0 ID78K0 FE9200 See C 2 Fuzzy Inference Development Support System Windows Ver 3 0 to Ver 3 1 is...

Page 532: ...K 78K I Series IE 78130 R IE 78140 R 78K II Series IE 78230 RNote IE 78230 R A IE 78240 RNote IE 78240 R A 78K III Series IE 78320 RNote IE 78327 R IE 78330 R IE 78350 R Note Available for maintenance...

Page 533: ...1 E EV 9200GC 64 B D C M N L K R Q I H P O S T J G No 1 pin index EV 9200GC 64 G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18 8 14 1 14 1 18 8 4 C 3 0 0 8 6 0 15 8 18 5 6 0 15...

Page 534: ...02 2 36 0 03 2 2 0 1 1 57 0 03 0 768 0 583 0 583 0 768 0 236 0 236 0 197 0 093 0 087 0 062 0 8 0 02 15 12 0 0 05 0 8 0 02 15 12 0 0 05 0 002 0 001 0 003 0 002 0 002 0 001 0 003 0 002 0 004 0 003 0 00...

Page 535: ...aSheet4U com APPENDIX C EMBEDDED SOFTWARE 535 APPENDIX C EMBEDDED SOFTWARE The following embedded software are available for efficient program development and maintenance of the PD78014 and 78014Y Sub...

Page 536: ...utline Maximum number for use in mass production 001 Evaluation object Do not use for mass producing product 100K Mass production object 100 000 001M 1 000 000 010M 10 000 000 S01 Source program Sourc...

Page 537: ...ape QIC 24 3P16 HP9000 series 700 HP UX Rel9 01 Digital audio tape DAT 3K15 SPARCstation SunOS Rel4 1 1 Cartridge tape QIC 24 3M15 EWS4800 series RISC EWS UX V Rel4 0 C 1 Real time OS 2 2 MX78K0 MX78K...

Page 538: ...nce is executed by linking fuzzy knowledge data Fuzzy converted by translator Inference Module Part Number S FI78K0 PC 9800 series IBM PC AT and compatible machine FD78K0 Support software evaluating a...

Page 539: ...register 1 TM1 207 8 bit timer register 2 TM2 207 External interrupt mode register INTM0 184 455 I Internal memory size switching register IMS 495 Interrupt mask flag register 0H MK0H 453 470 Interru...

Page 540: ...0 SIO0 269 327 Serial I O shift register 1 SIO1 412 Serial operating mode register 0 CSIM0 271 277 278 291 311 330 338 339 352 372 384 Serial operating mode register 1 CSIM1 415 418 419 422 16 bit ca...

Page 541: ...384 CSIM1 Serial operating mode register 1 415 418 419 422 I IF0H Interrupt request flag register 0H 452 470 IF0L Interrupt request flag register 0L 452 IMS Internal memory size switching register 495...

Page 542: ...register 0 269 327 SIO1 Serial I O shift register 1 412 SVA Slave address register 269 327 T TCL0 Timer clock select register 0 178 240 TCL1 Timer clock select register 1 207 TCL2 Timer clock select r...

Page 543: ...ng port 1 as A D converter input was added CHAPTER 4 Cautions on port mode register setting when port 2 is used in the SBI mode was PORT FUNCTIONS added Cautions on port mode register setting was adde...

Page 544: ...slave device is in the busy state or not when device is in the master mode was added in section 13 4 2 Cautions on SBI mode Section 13 4 4 I2 C bus mode operation was added Block diagram for serial i...

Page 545: ...it release slave reception 4 Reception completion CHANNEL 0 processing by a slave PD78014Y Subseries Section 16 4 7 Restrictions on Use of I2 C Bus Mode was added Sections 20 2 Operation Codes and 20...

Page 546: ...erface Channel 0 Control Register SERIAL INTERFACE 2 Serial operating mode register 0 CSIM0 CHANNEL 0 PD78014Y Cautions were added in section 16 4 3 2 a Bus release signal REL b Subseries Command sign...

Page 547: ...719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 S...

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