NEC 78014Y Series, User Manual

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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
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(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is removed with sampling clocks.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS to 00H.
Figure 18-6. Sampling Clock Select Register Format
Symbol 7 6 5 4 3 2 1 0 Address When Reset R/W
SCS 0 0 0 0 0 0 SCS1 SCS0 FF47H 00H R/W
SCS1 SCS0 INTP0 Sampling Clock Selection
0 0 f
X
/2 N+1
0 1 Setting prohibited
1 0 f
X
/2
6
(156 kHz)
1 1 f
X
/2 7 (78.1 kHz)
Caution f
X
/2
N+1
is a clock to be supplied to the CPU and f
X
/2
6
and f
X
/2
7
are clocks to be supplied to the
peripheral hardware. f
X
/2
N+1
stops in the HALT mode.
Remarks 1. N: Value (N = 0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC)
2. f
X
: Main system clock oscillation frequency
3. Values in parentheses apply to operation with f
X
= 10.0 MHz.