NEC 78014Y Series, User Manual

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23
LIST OF FIGURES (1/7)
Figure No. Title, Page
3-1 Pin Input/Output Circuit List .............................................................................................................. 76
4-1 Pin Input/Output Circuit List .............................................................................................................. 92
5-1 Memory Map (
µ
PD78011B, 78011BY) ............................................................................................. 95
5-2 Memory Map (
µ
PD78012B, 78012BY) ............................................................................................. 96
5-3 Memory Map (
µ
PD78013, 78013Y) .................................................................................................. 97
5-4 Memory Map (
µ
PD78014, 78014Y) .................................................................................................. 98
5-5 Memory Map (
µ
PD78P014, 78P014Y) ............................................................................................. 99
5-6 Program Counter Configuration ........................................................................................................ 102
5-7 Program Status Word Configuration ................................................................................................. 102
5-8 Stack Pointer Configuration .............................................................................................................. 104
5-9 Data to be Saved to Stack Memory .................................................................................................. 105
5-10 Data to be Reset from Stack Memory ............................................................................................... 105
5-11 General Register Configuration ........................................................................................................ 107
5-12 Data Memory Addressing (
µ
PD78011B, 78011BY) .......................................................................... 115
5-13 Data Memory Addressing (
µ
PD78012B, 78012BY) .......................................................................... 116
5-14 Data Memory Addressing (
µ
PD78013, 78013Y) .............................................................................. 117
5-15 Data Memory Addressing (
µ
PD78014, 78014Y) .............................................................................. 118
5-16 Data Memory Addressing (
µ
PD78P014, 78P014Y) .......................................................................... 119
6-1 Port Types ......................................................................................................................................... 129
6-2 P00 Block Diagram ........................................................................................................................... 134
6-3 P01 to P03 Block Diagrams .............................................................................................................. 135
6-4 P04 Block Diagram ........................................................................................................................... 135
6-5 P10 to P17 Block Diagrams .............................................................................................................. 136
6-6 P20, P21, P23 to P26 Block Diagrams (
µ
PD78014 Subseries) ........................................................ 137
6-7 P22 and P27 Block Diagrams (
µ
PD78014 Subseries) ..................................................................... 138
6-8 P20, P21, P23 to P26 Block Diagrams (
µ
PD78014Y Subseries) ..................................................... 139
6-9 P22 and P27 Block Diagrams (
µ
PD78014Y Subseries) ................................................................... 140
6-10 P30 to P37 Block Diagrams .............................................................................................................. 141
6-11 P40 to P47 Block Diagrams .............................................................................................................. 142
6-12 Block Diagram of Falling Edge Detector ........................................................................................... 142
6-13 P50 to P57 Block Diagrams .............................................................................................................. 143
6-14 P60 to P63 Block Diagrams .............................................................................................................. 145
6-15 P64 to P67 Block Diagrams .............................................................................................................. 145
6-16 Port Mode Register Format ............................................................................................................... 148
6-17 Pull-Up Resistor Option Register Format .......................................................................................... 149
6-18 Memory Expansion Mode Register Format ...................................................................................... 150
6-19 Key Return Mode Register Format ................................................................................................... 151
7-1 Clock Generator Block Diagram ....................................................................................................... 156
7-2 Feedback Resistor of Subsystem Clock ........................................................................................... 157
7-3 Processor Clock Control Register Format ........................................................................................ 158