NEC 78014Y Series, User Manual

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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
179
Figure 8-4. Timer Clock Select Register 0 Format
Symbol <7> 6 5 4 3 2 1 0 Address When Reset R/W
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H 00H R/W
TCL03 TCL02 TCL01 TCL00 PCL Output
Clock Selection
0 0 0 0 f
XT
(32.768 kHz)
0 1 1 1 f
X
/2 3 (1.25 MHz)
1 0 0 0 f
X
/2 4 (625 kHz)
1 0 0 1 f
X
/2
5
(313 kHz)
1 0 1 0 f
X
/2 6 (156 kHz)
1 0 1 1 f
X
/2 7 (78.1 kHz)
1 1 0 0 f
X
/2
8
(39.1 kHz)
Other than above Setting prohibited
TCL06 TCL05 TCL04 16-bit Timer Register
Count Clock Selection
0 0 0 TI0 (Valid edge specifiable)
0 1 0 f
X
/2 (5.0 MHz)
0 1 1 f
X
/2 2 (2.5 MHz)
1 0 0 f
X
/2 3 (1.25 MHz)
Other than above Setting prohibited
CLOE PCL Output Control
0 Output disabled
1 Output enabled
Cautions 1. Setting of the INTP0/P00/TI0 pin valid edge is performed by external interrupt mode register
(INTM0), and selection of the sampling clock frequency is performed by the sampling clock
selection register (SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI0 has been specified as the TM0 count clock, the value should
be read from TM0, not from the 16-bit capture register CR01.
4. If data other than identical data is to be rewritten to TCL0, the timer operation must be stopped
first.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. TI0 : 16-bit timer/event counter input pin
4. TM0: 16-bit timer register
5. Value in parentheses apply to operation with f
X
= 10.0 MHz or f
XT
= 32.768 kHz.
6. See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT for PCL.