NEC 78014Y Series, User Manual

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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
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18.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt
mask flag for that interrupt is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state
(with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt
service (with ISP flag reset to 0).
Wait times from maskable interrupt request generation to interrupt servicing are shown in Table 18-3.
Refer to Figures 18-3 and 18-4 for the interrupt request acknowledge timing.
Table 18-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Note If an interrupt request is generated just before a divide
instruction, the wait time is maximized.
Remark 1 clock: 1/f
CPU
(f
CPU
: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. If two or more requests are specified for the same priority with
the priority specify flag, the interrupt request with the higher default priority is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 18-12 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, program status
word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the contents of acknowledged
interrupt request priority specify flag contents are transferred to the ISP flag. Further, the vector table data determined
for each interrupt request is loaded into PC and branched.
Return from the interrupt is possible with the RETI instruction.
Minimum Time Maximum Time Note
When XXPR = 0 13 clocks 63 clocks
When XXPR = 1 15 clocks 65 clocks