NEC 78014Y Series, User Manual

Page: 354 / 547

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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78014Y Subseries)
354
Note Bits 2, 3 and 6 (RELD, CMDD, and ACKD) are Read-Only bits.
Remarks 1. Zeros will be returned form bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these
bits after data setting is completed.
2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address When Reset R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R/W Note
R/W RELT Use for bus release signal output when the SBI mode is used.
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W CMDT Use for command signal output when the SBI mode is used.
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R RELD Bus Release Detection
Clear Conditions (RELD = 0) Set Conditions (RELD = 1)
• When transfer start instruction is executed • When bus release signal (REL) is detected in the SBI mode
• If SIO0 and SVA values do not match in address
reception (only if WUP = 1)
• When CSIE0 = 0
• When RESET input is applied
R CMDD Command Detection
Clear Conditions (CMDD = 0) Set Conditions (CMDD = 1)
• When transfer start instruction is executed • When command signal (CMD) is detected in the SBI mode
• When bus release signal (REL) is detected in the SBI mode
• When CSIE0 = 0
• When RESET input is applied
R/W ACKT When the SBI mode is used, acknowledge signal is output in synchronization with the falling edge of SCK0
clock immediately after execution of the instruction to be set to 1, and after acknowledge signal output,
automatically cleared to 0. Used as ACKE = 0.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
(continued)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.