NEC 78014Y Series, User Manual

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CHAPTER 20 STANDBY FUNCTION
488
STOP Mode Setting With subsystem clock Without subsystem clock
Item
Clock generator Only main system clock stops oscillation.
CPU Operation stop.
Output port (output latch) Status before STOP instruction execution is held.
16-bit timer/event counter Operation stop.
8-bit timer/event counter Operation enabled when TI1 and TI2 are selected for the count clock.
Watchdog timer Operation stop.
A/D converter
Watch timer Operation enabled when f
XT
is selected Operation stop.
for the count clock.
Serial Other than auto- Operation enabled only when external input clock is selected as serial clock.
Interface matic transmit/
receive function
Automatic Operation stop.
transmit/receive
function
External INTP0 Operation disabled.
interrupt INTP1 to INTP3 Operation enabled.
Bus line in AD0 to AD7 High-impedance
External A8 to A15 Status before STOP instruction execution is held.
Expansion ASTB Low level
WR, RD High level
WAIT High-impedance
20.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, X1 input is internally short-circuited to V
SS
(ground potential)
to suppress the leakage at the crystal oscillator. Thus, do not use the STOP mode in a
system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode
immediately after execution of the STOP instruction. After the wait set using the oscillation
stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Table 20-3. STOP Mode Operating Status