NEC 78014Y Series, User Manual

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CHAPTER 7 CLOCK GENERATOR
169
7.6.2 System clock and CPU clock switching procedure
This section describes switching procedure between system clock and CPU clock.
Figure 7-8. System Clock and CPU Clock Switching
(1)The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation
stabilization time (2
18
/f
X
) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4
µ
s when
operated at 10.0 MHz).
(2)After the lapse of a sufficient time for the V
DD
voltage to increase to enable operation at maximum speed, the
processor clock control register (PCC) is rewritten and maximum-speed operation is carried out.
(3)Upon detection of a decrease of the V
DD
voltage due to an interrupt request signal, the main system clock is
switched to the subsystem clock (which must be in an oscillation stabilization state).
(4)Upon detection of V
DD
voltage reset due to an interrupt request signal, 0 is set to PCC bit 7 (MCC) and oscillation
of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC is
rewritten and maximum-speed operation is resumed.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to
the main system clock.
V
DD
RESET
Interrupt
Request
Signal
System Clock
CPU Clock
f
X
f
X
f
XT
f
X
Minimum
Speed
Operation
Maximum Speed
Operation
Subsystem Clock
Operation
High-Speed
Operation
Wait (26.2 ms : @ 10.0 MHz)
Internal Reset Operation