Motorola CMOS Logic Manual Download Page 95

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MOTOROLA CMOS LOGIC DATA

6–57

MC14017B

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

Vout

VSS

VDD

VSS

EXTERNAL

POWER

SUPPLY

CLOCK
ENABLE

RESET

CLOCK Cout

Q1
Q2

Q3
Q4
Q5

Q6
Q7
Q8

Output

Sink Drive

Output

Source Drive

Decode

Outputs

Clock to

desired
outputs

(S1 to B)

(S1 to A)

Carry

Clock to 5

thru 9

(S1 to B)

S1 to A

VGS =

– VDD

VDD

VDS =

Vout – VDD

Vout

Figure 2. Typical Power Dissipation Test Circuit

VDD

VSS

CLOCK
ENABLE

RESET

CLOCK

Cout

Q0
Q1

Q2
Q3
Q4

Q5
Q6

Q8
Q9

500

0.01

CERAMIC

PULSE

GENERATOR

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-

quential within each stage and from stage to stage, with no dead time (except propagation delay).

Figure 3. Counter Expansion

RESET

CLOCK

MC14017B

Q0 Q1

Q8 Q9

• • •

9 DECODED

OUTPUTS

CLOCK

FIRST STAGE

INTERMEDIATE STAGES

LAST STAGE

RESET

CLOCK

MC14017B

Q0Q1

Q8 Q9

• • •

RESET

CLOCK

MC14017B

Q8 Q9

• • •

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

Summary of Contents for CMOS Logic

Page 1: ......

Page 2: ...Packaging Information Including Surface Mounts Equivalent Gate Count Data Sheets CMOS Handling and Design Guidelines B and UB Series Family Data The Better Program Product Selection Guide Master Index 1 2 3 4 6 7 9 8 5 ...

Page 3: ...is heading on a data sheet indicates that the device is in sampling preproduction or first production stages The disclaimer at the bottom of the first page reads This document contains information on a new product Specifications and information herein are subject to change without notice Fully Released A fully released data sheet contains neither a classification heading nor a disclaimer at the bo...

Page 4: ...ed or authorized for use as compo nents in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer sh...

Page 5: ...iv MOTOROLA CMOS LOGIC DATA ...

Page 6: ...Master Index 1 ...

Page 7: ...4 Input NAND Gate 6 14 MC14013B Dual D Flip Flop 6 33 MC14014B 8 Bit Static Shift Register 6 37 MC14015B Dual 4 Bit Static Shift Register 6 41 MC14016B Quad Analog Switch Multiplexer 6 47 MC14017B Decade Counter 6 54 MC14018B Presettable Divide by N Counter 6 59 MC14020B 14 Bit Binary Counter 6 63 MC14021B 8 Bit Static Shift Register 6 37 MC14022B Octal Counter 6 67 MC14023B Triple 3 Input NAND Ga...

Page 8: ...MC14076B Quad D Type Register with Tri State Outputs 6 162 MC14077B Quad Exclusive NOR Gate 6 160 MC14078B 8 Input NOR Gate 6 5 MC14081B Quad 2 Input AND Gate 6 5 MC14082B Dual 4 Input AND Gate 6 5 MC14093B Quad 2 Input NAND Schmitt Trigger 6 166 MC14094B 8 Stage Shift Store Register with Tri State Outputs 6 170 MC14097B Dual 8 Channel Analog Multiplexer Demultiplexer 6 150 MC14099B 8 Bit Addressa...

Page 9: ... Control Unit 6 217 MC14501UB Triple Gate 6 223 MC14502B Strobed Hex Inverter Buffer 6 227 MC14503B Hex 3 State Buffer 6 231 MC14504B TTL or CMOS to CMOS Hex Level Shifter 6 235 MC14506UB Dual Expandable AOI Gate 6 238 MC14508B Dual 4 Bit Latch 6 243 MC14510B Presettable BCD Up Down Counter 6 248 MC14511B BCD to 7 Segment Latch Decoder Driver 6 256 MC14512B 8 Channel Data Selector 6 262 MC14513B B...

Page 10: ...Successive Approximation Registers 6 398 MC14551B Quad 2 Channel Analog Multiplexer Demultiplexer 6 405 MC14553B 3 Digit BCD Counter 6 412 MC14554B 2 X 2 Bit Parallel Binary Multiplier 6 418 MC14555B Dual Binary to 1 of 4 Decoder Active High Outputs 6 422 MC14556B Dual Binary to 1 of 4 Decoder Active Low Outputs 6 422 MC14557B 1 to 64 Bit Variable Length Shift Register 6 425 MC14558B BCD to 7 Segm...

Page 11: ...r Not Recommended for New Designs SF MC145106 PLL Frequency Synthesizer SF MC145107 PLL Frequency Synthesizer Not Recommended for New Designs SF MC145109 PLL Frequency Synthesizer Not Recommended for New Designs SF MC145112 PLL Frequency Synthesizer Not Recommended for New Designs SF MC145143 PLL Frequency Synthesizer Not Recommended for New Designs SF MC145144 4 Bit Data Bus Input PLL Frequency S...

Page 12: ...Product Selection Guide 2 ...

Page 13: ... NOR Gate 6 5 AND Gates MC14081B Quad 2 Input AND Gate 6 5 MC14073B Triple 3 Input AND Gate 6 5 MC14082B Dual 4 Input AND Gate 6 5 OR Gates MC14071B Quad 2 Input OR Gate 6 5 MC14075B Triple 3 Input OR Gate 6 5 MC14072B Dual 4 Input OR Gate 6 5 Complex Gates MC14070B Quad Exclusive OR Gate 6 160 MC14077B Quad Exclusive NOR Gate 6 160 MC14501UB Triple Gate 6 223 MC14506UB Dual Expandable AOI Gate 6 ...

Page 14: ...r 6 405 MC14053B Triple 2 Channel Analog Multiplexer Demultiplexer 6 133 MC14052B Dual 4 Channel Analog Multiplexer Demultiplexer 6 133 MC14097B Dual 8 Channel Analog Multiplexer Demultiplexer 6 150 MC14529B Dual 4 Channel Analog Data Selector 6 327 MC14539B Dual 4 Channel Data Selector Multiplexer 6 373 MC14067B 16 Channel Analog Multiplexer Demultiplexer 6 150 MC14051B 8 Channel Analog Multiplex...

Page 15: ...6 72 MC14029B Presettable Binary BCD Up Down Counter 6 86 MC14040B 12 Bit Binary Counter 6 108 MC14060B 14 Bit Binary Counter and Oscillator 6 140 MC14160B Synchronous Presettable BCD Counter 6 184 MC14161B Synchronous Presettable 4 Bit Binary Counter 6 184 MC14162B Synchronous Presettable BCD Counter 6 184 MC14163B Synchronous Presettable 4 Bit Binary Counter 6 184 MC14510B Presettable BCD Up Dow...

Page 16: ...parator 6 507 ALU Rate Multipliers MC14527B BCD Rate Multiplier 6 315 MC14554B 2 X 2 Bit Parallel Binary Multiplier 6 418 MC14581B 4 Bit Arithmetic Logic Unit 6 489 Parity Checker MC14531B 12 Bit Parity Tree 6 338 Memory MC14580B 4 X 4 Multiport Register 6 484 Microprocessor Industrial Control MC14500B Industrial Control Unit 6 217 Other Complex Functions MC14046B Phase Locked Loop 6 120 MC14415 Q...

Page 17: ...The Better Program 3 ...

Page 18: ...uoted as an adder to standard commercial product price RAP Reliability Audit Program For Logic Integrated Circuits 1 0 INTRODUCTION The Reliability Audit Program developed in March 1977 is the Motorola internal reliability audit which is designed to as sess outgoing product performance under accelerated stress conditions Logic Reliability Engineering has overall respon sibility for RAP including u...

Page 19: ...CRAP 3 0 TEST CONDITIONS AND COMMENTS PTHB 15 psig 121 C 100 RH at rated VCC or VEE to be performed on plastic encapsulated devices only TEMP CYCLING MIL STD 883 Method 1010 Condi tion C 65 C 150 C OP LIFE MIL STD 883 Method 1005 Condition C Power plus Reverse Bias TA 145 C NOTES 1 All standard 25 C dc and functional parameters will be measured Go No Go at each readout 2 Any indicated failure is f...

Page 20: ...B and UB Series Family Data 4 ...

Page 21: ...preted as the worst case input voltage to produce an output level of 1 or 0 This 1 or 0 output level is defined as a deviation from the supply VDD and ground VSS levels For a 5 0 V supply this deviation is 0 5 V for a 10 V supply 1 0 V and for 15 V 1 5 V As an example in a device operating at a 5 0 V supply the device with the input starting at ground is guaranteed to switch on or before 3 5 V and...

Page 22: ... ÎÎÎ ÎÎÎ ÎÎÎ µAdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ GATES ÎÎÎ ÎÎÎ ÎÎÎ CommÎÎÎ ÎÎÎ ÎÎÎ 5 10 15 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ All valid input combinations ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 0 2 0 4 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 0 2 0 4 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 7 5 15 30 ÎÎÎ ÎÎÎ ÎÎÎ µAdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Mil ÎÎÎ ÎÎÎ ÎÎÎ 5 10 15 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VIN VSS or VDD ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ...

Page 25: ...CMOS Handling and Design Guidelines 5 ...

Page 26: ... tions to a PC board are connected to an input of a CMOS device a resistor should be used in series with the input This resistor helps limit accidental damage if the PC board is removed and brought into contact with static generating materials The limiting factor for the series resistor is the added delay This is caused by the time constant formed by the series resistor and input capacitance Note ...

Page 27: ...15 Do not insert or remove CMOS devices from test sockets with power applied Check all power supplies to be used for testing devices to be certain there are no voltage transients present 16 Double check test equipment setup for proper polarity of VDD and VSS before conducting parametric or func tional testing 17 Do not recycle shipping rails or trays Repeated use causes deterioration of their anti...

Page 28: ...rent of the latch up mode The value of VS was chosen so that the secondary breakdown effect may be avoided In an ideal system design a power supply should be designed to deliver only enough current to insure proper operation of all devices The obvious benefit of this type design is cost savings an added benefit is protection against the possibility of latch up related failures This system protecti...

Page 29: ...ting causing excessive current drain Due to the high gain of the inverters see Figure 7 the device may also go into oscillation from any noise in the system Since CMOS devices dissipate the most power during switching this oscillation can cause very large current drain and undesired switching Figure 6 Typical Transfer Characteristics for Buffered Devices 5 0 4 0 3 0 2 0 1 0 0 0 1 0 2 0 3 0 4 0 5 0...

Page 30: ... sheet For applications that require driving high capacitive loads where fast propagation delays are needed e g driving power MOSFETs two or more outputs on the same chip may be externally paralleled CMOS LATCH UP Latch up will not be a problem for most designs but the designer should be aware of it what causes it and how to prevent it Figure 11 shows the cross section of a typical CMOS in verter ...

Page 31: ...D P CHANNEL N CHANNEL INPUT OUTPUT P CHANNEL OUTPUT N CHANNEL OUTPUT VSS FIELD OXIDE FIELD OXIDE FIELD OXIDE N P P N N P P WELL N SUBSTRATE Figure 11 Latch Up Circuit Schematic VSS VSS N CHANNEL OUTPUT N SUBSTRATE RESISTANCE Q1 N P P CHANNEL OUTPUT P WELL RESISTANCE N P P VDD VDD N N P Q2 ...

Page 32: ...CMOS Handling and Design Guidelines 5 ...

Page 33: ... tions to a PC board are connected to an input of a CMOS device a resistor should be used in series with the input This resistor helps limit accidental damage if the PC board is removed and brought into contact with static generating materials The limiting factor for the series resistor is the added delay This is caused by the time constant formed by the series resistor and input capacitance Note ...

Page 34: ...15 Do not insert or remove CMOS devices from test sockets with power applied Check all power supplies to be used for testing devices to be certain there are no voltage transients present 16 Double check test equipment setup for proper polarity of VDD and VSS before conducting parametric or func tional testing 17 Do not recycle shipping rails or trays Repeated use causes deterioration of their anti...

Page 35: ...rent of the latch up mode The value of VS was chosen so that the secondary breakdown effect may be avoided In an ideal system design a power supply should be designed to deliver only enough current to insure proper operation of all devices The obvious benefit of this type design is cost savings an added benefit is protection against the possibility of latch up related failures This system protecti...

Page 36: ...ting causing excessive current drain Due to the high gain of the inverters see Figure 7 the device may also go into oscillation from any noise in the system Since CMOS devices dissipate the most power during switching this oscillation can cause very large current drain and undesired switching Figure 6 Typical Transfer Characteristics for Buffered Devices 5 0 4 0 3 0 2 0 1 0 0 0 1 0 2 0 3 0 4 0 5 0...

Page 37: ... sheet For applications that require driving high capacitive loads where fast propagation delays are needed e g driving power MOSFETs two or more outputs on the same chip may be externally paralleled CMOS LATCH UP Latch up will not be a problem for most designs but the designer should be aware of it what causes it and how to prevent it Figure 11 shows the cross section of a typical CMOS in verter ...

Page 38: ...D P CHANNEL N CHANNEL INPUT OUTPUT P CHANNEL OUTPUT N CHANNEL OUTPUT VSS FIELD OXIDE FIELD OXIDE FIELD OXIDE N P P N N P P WELL N SUBSTRATE Figure 11 Latch Up Circuit Schematic VSS VSS N CHANNEL OUTPUT N SUBSTRATE RESISTANCE Q1 N P P CHANNEL OUTPUT P WELL RESISTANCE N P P VDD VDD N N P Q2 ...

Page 39: ...Data Sheets 6 ...

Page 41: ...9 3 5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 7 0 14 0 35 1 1 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Inp...

Page 42: ...Propagation Delay Time tPLH tPHL 1 7 ns pF CL 30 ns tPLH tPHL 0 66 ns pF CL 22 ns tPLH tPHL 0 50 ns pF CL 15 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 115 55 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 230 110 80 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes ...

Page 43: ...ut Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values b...

Page 44: ... 5 2 10 11 12 9 5 9 10 4 3 2 11 12 8 INPUT 5 9 10 4 3 2 11 12 NC 6 8 NC 6 8 NC 6 8 NC 6 8 NC 6 8 NC 6 8 VDD PIN 14 VSS PIN 7 FOR ALL DEVICES NOR MC14001B Quad 2 Input NOR Gate MC14025B Triple 3 Input NOR Gate MC14002B Dual 4 Input NOR Gate MC14078B 8 Input NOR Gate MC14068B 8 Input NAND Gate MC14012B Dual 4 Input NAND Gate MC14023B Triple 3 Input NAND Gate NAND MC14011B Quad 2 Input NAND Gate OR M...

Page 45: ...IN 2B IN 1B 11 12 13 14 8 9 10 5 4 3 2 1 7 6 IN 2B IN 3B IN 4B OUTB VDD NC IN 1B IN 3A IN 2A IN 1A OUTA VSS NC IN 4A 11 12 13 14 8 9 10 5 4 3 2 1 7 6 OUTC IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN 1B IN 2A IN 1A VSS OUTB IN 3B 11 12 13 14 8 9 10 5 4 3 2 1 7 6 IN 6 IN 7 IN 8 OUT VDD NC IN 5 IN 3 IN 2 IN 1 NC VSS NC IN 4 11 12 13 14 8 9 10 5 4 3 2 1 7 6 OUTC IN 1C IN 2C IN 3C VDD IN 3A OUTA IN 2B IN...

Page 46: ...ÎÎ Output Drive Current VOH 2 5 Vdc Source VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VO...

Page 47: ...ÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time MC14001B MC14011B only tPLH tPHL 0 90 ns pF CL 80 ns tPLH tPHL 0 36 ns pF CL 32 ns tPLH tPHL 0 26 ns pF CL 27 ns All Other 2 3 and 4 Input Gates tPLH tPHL 0 90 ns pF CL 115 ns tPLH tPHL 0 36 ns pF CL 47 ns tPLH tPHL 0 26 ns pF CL 37 ns 8 Input Gates MC14068B MC14078B tPLH tPHL 0 90 ns pF CL 155 ns tPLH tPHL 0 36 ns pF CL 62 ns tPLH tPHL 0 26 ns pF CL 47 ns ÎÎÎÎ ...

Page 48: ... 12 VSS VDD VSS VDD Inverter omitted in MC14025B 8 5 13 14 7 1 13 VSS VDD 3 9 2 10 VSS VDD Inverter omitted in MC14002B SAME AS ABOVE 5 11 4 12 14 7 13 VSS VDD 11 12 9 10 4 5 2 3 VSS VDD SAME AS ABOVE SAME AS ABOVE SAME AS ABOVE MC14001B MC14071B One of Four Gates Shown MC14025B MC14075B One of Three Gates Shown MC14002B MC14072B One of Two Gates Shown MC14078B Eight Input Gate ...

Page 49: ... 6 8 13 2 4 12 1 3 11 VDD VDD VSS VSS 8 5 13 14 7 1 13 VSS VDD Inverter omitted in MC14012B 2 10 3 9 VDD VSS SAME AS ABOVE 4 12 5 11 14 7 13 VSS VDD VSS VDD 2 3 VDD VSS 5 4 VDD 11 12 9 10 VSS SAME AS ABOVE SAME AS ABOVE SAME AS ABOVE MC14011B MC14081B One of Four Gates Shown MC14023B MC14073B One of Three Gates Shown MC14012B MC14082B One of Two Gates Shown MC14068B Eight Input Gate ...

Page 50: ...C 40 C 25 C 85 C 125 C VDS DRAIN TO SOURCE VOLTAGE Vdc VDS DRAIN TO SOURCE VOLTAGE Vdc VDS DRAIN TO SOURCE VOLTAGE Vdc VDS DRAIN TO SOURCE VOLTAGE Vdc TA 55 C 40 C 25 C 85 C 125 C 18 20 9 0 7 0 5 0 3 0 1 0 10 8 0 6 0 4 0 2 0 9 0 7 0 40 35 30 25 20 15 10 5 0 45 50 10 6 0 2 0 20 16 12 8 0 4 0 18 14 TA 55 C 40 C 25 C 85 C 10 6 0 2 0 20 16 12 8 0 4 0 18 14 80 70 60 50 40 30 20 10 90 100 40 35 30 25 20...

Page 51: ...UT NOR OR MULTIPLE INPUT NAND AND 2 0 6 0 10 8 0 4 0 2 0 6 0 10 8 0 4 0 Vin INPUT VOLTAGE Vdc 12 14 16 V out OUTPUT VOLTAGE Vdc DC NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal 1 or 0 input level which does not produce output state change s The typical and guaranteed limit val ues of the input values VIL and VIH for the output s to be at a fixed voltage VO ar...

Page 52: ...IN 7 FOR ALL DEVICES 13 12 9 8 6 5 2 1 3 4 10 11 12 11 10 9 5 4 3 2 13 1 NC 6 8 13 12 9 8 6 5 2 1 3 4 10 11 12 11 10 9 5 4 3 2 13 1 NC 6 8 12 11 5 4 3 8 2 1 13 9 6 10 12 11 5 4 3 8 2 1 13 9 6 10 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14001UB Quad 2 Input NOR Gate MC14002UB Dual 4 Input NOR Gate MC14011UB Quad 2 Input NAND Gate MC14012UB Dual 4 Input NAND Gate MC14023UB Triple 3 Input NAND Gate MC...

Page 54: ...rce VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 2 0 25 0 62 1 8 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 0 0 2 0 5 1 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 3 5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 7 0 14 0 35 1 1 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Si...

Page 55: ...ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 80 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time tPLH tPHL 1 7 ns pF CL 30 ns tPLH tPHL 0 66 ns pF CL 22 ns tPLH tPHL 0 50 ns pF CL 15 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 90 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎ...

Page 56: ... 7 VSS 14 VDD V out OUTPUT VOLTAGE Vdc 16 14 12 10 8 0 6 0 4 0 2 0 0 0 2 0 4 0 6 0 8 0 10 12 14 16 8 0 6 0 4 0 2 0 0 I D DRAIN CURRENT mAdc Vin INPUT VOLTAGE Vdc V out OUTPUT VOLTAGE Vdc 16 14 12 10 8 0 6 0 4 0 2 0 0 0 2 0 4 0 6 0 8 0 10 12 14 16 Vin INPUT VOLTAGE Vdc I D DRAIN CURRENT mAdc 8 0 6 0 4 0 2 0 0 10 10 8 0 6 0 4 0 2 0 0 VDS DRAIN VOLTAGE Vdc I D DRAIN CURRENT mAdc 2 0 4 0 6 0 8 0 10 0 ...

Page 59: ...ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 15 5 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ µs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 0 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 50 15 8 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎ ...

Page 60: ...aveforms ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ PULSE GENERATOR 1 PULSE GENERATOR 2 VDD 14 CLOCK Q4 DP1 Q8 DP5 Q9 DP10 DP14 Q13 Q17 Q18 7 VSS CL CL CL CL CL CL CLOCK DATA 4 STAGE OUTPUT Q4 Q8 Q13 Q17 5 STAGE OUTPUT Q9 Q18 20 ns 20 ns tWL tWH 90 50 10 90 50 10 th 1 tsu 1 th 0 tsu 0 20 ns 20 ns tPLH VDD tPHL tTLH tTHL tTHL tPHL tTLH VSS VDD VSS VOH VOL VOH VOL Ou...

Page 63: ...ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 60 30 25 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125 75 55 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn On Delay Time tPHL 1 0 ns pF CL 10 ns tPHL 0 3 ns pF CL 15 ns tPHL 0 2 ns pF CL 15 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 60 30 25 Î...

Page 64: ...er which has access to all its elements offers a number of unique circuit applica tions Figures 1 5 and 6 are a few examples of the device flexibility Figure 5 3 State Buffer VDD DISABLE 3 INPUT 10 DISABLE 6 12 OUTPUT 11 1 2 9 8 7 INPUT DISABLE OUTPUT 1 0 X 0 0 1 0 1 OPEN X Don t Care Figure 6 AOI Functions Using Tree Logic VDD 14 13 11 10 3 6 B C A 9 5 4 8 7 1 2 OUTPUT OUT A B C Substrates of P c...

Page 66: ...ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ...

Page 67: ...0 66 ns pF CL 112 ns tPLH tPHL 0 5 ns pF CL 85 ns Carry In to Sum Out tPLH tPHL 1 7 ns pF CL 290 ns tPLH tPHL 0 66 ns pF CL 122 ns tPLH tPHL 0 5 ns pF CL 90 ns Carry In to Carry Out tPLH tPHL 1 7 ns pF CL 85 ns tPLH tPHL 0 66 ns pF CL 42 ns tPLH tPHL 0 5 ns pF CL 30 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Î...

Page 68: ...ENERATOR VDD 16 B4 A4 B3 A3 B2 A2 B1 A1 Cin S4 S3 S2 S1 Cout IDD 8 VSS CL CL CL CL CL 500 µF Figure 4 Switching Time Test Circuit and Waveforms PULSE GENERATOR VDD 16 B4 A4 B3 A3 B2 A2 B1 A1 Cin S4 S3 S2 S1 Cout IDD 8 VSS CL CL CL CL CL 20 ns 20 ns Cin S1 S4 Cout VDD VSS VOH VOL VOH VOL tPLH tPHL tTHL tTLH tPLH tPHL 90 50 10 90 50 10 50 ...

Page 69: ...MOTOROLA CMOS LOGIC DATA 6 31 MC14008B Figure 5 Logic Diagram Cin A1 B1 A2 B2 A3 B3 A4 B4 S1 S2 S3 S4 Cout ...

Page 70: ...4 A1 B4 A1 B4 A1 B4 S1 S4 S1 S4 S1 S4 S1 S4 Cin Cin Cin Cin Cout Cout Cout Cout CHIP 1 CHIP 2 CHIP 3 CHIP 4 SUM OUTPUTS Calculation of 16 bit adder speed tP total tP Sum to Carry tP Carry to Sum 2 tP Carry to Carry The guaranteed 16 bit adder speed at 10 V 25 C CL 50 pF is tp total 290 310 300 900 ns TYPICAL APPLICATION ...

Page 71: ...ÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin Vout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW...

Page 73: ... tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 40 20 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 20 10 7 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Times ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 40 20 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 20 10 7 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width ÎÎÎÎ ÎÎ...

Page 74: ...OH VOL tTLH tTHL tPHL tPLH 90 50 10 Inputs R and S low 1 fcl 20 ns 20 ns SET OR RESET CLOCK Q OR Q 90 50 10 VDD VSS VDD VSS VOH VOL 20 ns 20 ns trem 90 50 10 50 tPLH tPHL tw 20 ns tw TYPICAL APPLICATIONS n STAGE SHIFT REGISTER BINARY RIPPLE UP COUNTER Divide by 2n MODIFIED RING COUNTER Divide by n 1 D CLOCK nth 2 1 Q D C Q Q D C Q Q D C Q Q CLOCK nth 2 1 D C Q Q D C Q Q D C Q Q Q T FLIP FLOP nth 2...

Page 75: ...to 18 0 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin Vout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage...

Page 77: ... ÎÎÎÎ ÎÎÎÎ 150 75 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Time P S to Clock ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 80 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Time Clock to P S ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎ Î...

Page 78: ...LOCK DATA 50 1 f Figure 4 Switching Time Test Circuit and Waveforms PULSE GENERATOR 1 PULSE GENERATOR 2 VDD 1 2 2 2 1 1 VDD VSS SW 1 SW 2 CL Q8 Q7 Q6 P S C P6 P7 P8 DS P5 P4 P3 P2 P1 VDD VSS VDD VSS VOH VOL 20 ns 20 ns PARALLEL OR SERIAL DATA INPUT CLOCK OR P S INPUT Q OUTPUT 90 50 10 tsu tWH tTHL 90 50 10 tWH tWL tPLH tPHL 90 50 10 tTLH tTHL tWL tWH 50 DUTY CYCLE SWITCH POSITION 1 PARALLEL IN SWI...

Page 81: ...ÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 175 135 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 185 85 55 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ fcl ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ...

Page 82: ... CL DATA INPUT CLOCK INPUT tTLH tTHL VDD 0 V VDD 0 V tsu tTLH tTHL tWH tWL Q0 tTLH tTHL tPLH tPHL 90 50 10 90 50 10 90 50 10 tWL tWH 50 Duty Cycle tTLH tTHL 20 ns SYNC t Figure 3 Setup and Hold Time Test Circuit and Waveforms VDD CL VSS PULSE GENERATOR 2 PULSE GENERATOR 1 Q0 Q1 Q2 Q3 D C R CL CL CL SYNC CLOCK INPUT DATA INPUT 50 VDD 0 V VDD 0 V tsu th 50 ...

Page 83: ...15B CIRCUIT SCHEMATICS DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER SINGLE BIT Q VDD VSS TO D OF NEXT BIT DATA IN CLOCK RESET VDD VSS VDD VSS VDD VSS DATA IN RESET IN CLOCK IN CLOCK TO 4 BITS RESET TO 4 BITS DATA TO FIRST BIT ...

Page 84: ... NEXT BIT COMPLETE DEVICE D C R D C R 14 1 15 6 9 7 DATA INPUT BUFFER CLOCK INPUT BUFFER RESET INPUT BUFFER DATA INPUT BUFFER CLOCK INPUT BUFFER RESET INPUT BUFFER 5 4 3 10 Q0 Q1 Q2 Q3 D C R Q Q D C R Q Q D C R Q Q D C R Q Q 11 2 12 13 Q0 Q1 Q2 Q3 D C R Q Q D C R Q Q D C R Q Q D C R Q Q VDD PIN 16 VSS PIN 8 ...

Page 85: ...rol Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ Isw ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Switch Through Current ÎÎÎÎÎÎ ÎÎÎÎÎÎ 25 ÎÎÎ ÎÎÎ mA ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ 500 ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C ...

Page 88: ... 10 k ID VDD Vout VSS Vin fc TO ALL 4 CIRCUITS PD VDD x ID 50 M 10 M 1 0 M 100 k 10 k 5 0 k 10 000 1000 100 10 1 0 TA 25 C 10 Vdc 5 0 Vdc fc FREQUENCY Hz POWER DISSIPATION P D µW CONTROL INPUT VDD 15 Vdc TYPICAL RON versus INPUT VOLTAGE Figure 4 VSS 5 0 V and 7 5 V Figure 5 VSS 0 V ON RESISTANCE OHMS R ON 700 600 500 400 300 200 100 0 10 8 0 4 0 0 4 0 8 0 10 Vin INPUT VOLTAGE Vdc ON RESISTANCE OHM...

Page 89: ...ime Test Circuit and Waveforms Figure 9 Crosstalk Test Circuit VC Vout Vin RL CL VX 20 ns VC Vout Vout 10 90 10 90 90 50 10 tPZH tPHZ VDD VSS tPLZ tPZL Vin VDD Vx VSS Vin VSS Vx VDD VC Vout Vin 1 k 10 k 15 pF Figure 10 Noise Voltage Test Circuit Figure 11 Typical Noise Characteristics VC VDD OUT IN QUAN TECH MODEL 2283 OR EQUIV 100 k 10 k 1 0 k 100 10 35 30 25 20 0 10 Vdc 5 0 Vdc f FREQUENCY Hz NO...

Page 90: ...Response Test Circuit VC Vout RL Vin 2 5 Vdc 0 0 Vdc 2 5 Vdc 100 M 10 M 1 0 M 100 k 10 k 2 0 0 2 0 RL 1 MΩ AND 100 kΩ fin INPUT FREQUENCY Hz 4 0 6 0 8 0 10 12 TYPICAL INSERTION LOSS dB 10 kΩ 1 0 kΩ 3 0 dB RL 1 0 MΩ 3 0 dB RL 10 kΩ 3 0 dB RL 1 0 kΩ Figure 14 V Across Switch CONTROL SECTION OF IC SOURCE V LOAD ON SWITCH ...

Page 91: ...l which allows no margin at either peak If voltage transients above VDD and or below VSS are anticipated on the analog channels external diodes Dx are recommended as shown in Figure B These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping The absolute maximum potential difference between VDD and VSS is 18 0 V Most parameters are specified up...

Page 92: ...tput Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ...

Page 94: ...Î 1000 460 350 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn Off Delay Time Reset to Cout tPLH 1 7 ns pF CL 315 ns tPLH 0 66 ns pF CL 142 ns tPLH 0 5 ns pF CL 100 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 175 125 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 800 350 250 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ...

Page 95: ...ion Test Circuit VDD VSS ID CLOCK ENABLE RESET CLOCK Cout Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 500 µF 0 01 µF CERAMIC PULSE GENERATOR fc CL CL CL CL CL CL CL CL CL CL CL APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14017B Decoded outputs are se quential within each stage and from stage to stage with no dead time except propagation delay F...

Page 96: ... tPLH tPLH tPLH tPLH tPLH tPLH tTHL tTHL tTLH tPLH tPLH tPLH tTLH tPLH tPHL tPHL tPHL tPHL 50 tPHL tPHL 90 10 tTHL tPHL tTHL tPHL tTHL tTLH tTHL tPHL trem tsu 20 ns 20 ns 20 ns 20 ns tPLH 90 10 50 tTLH tTLH tTLH tTLH tTLH tTHL tTHL tTHL tTHL tPHL tTHL 90 50 10 20 ns tPLH tTLH VDD VSS VDD VSS VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL ...

Page 97: ...Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond w...

Page 100: ... 9 7 3 2 CLOCK 14 DATA 1 RESET 15 PRESET ENABLE 10 CLOCK SHAPER 5 4 6 11 13 Q1 Q2 Q3 Q4 Q5 S S S S S D D D D D C C C C C Q Q Q Q Q R P R P R P R P R P Q VDD PIN 16 VSS PIN 8 FUNCTION SELECTION Counter Mode Connect Data Input Pin 1 to Comments Divide by 10 Divide by 8 Divide by 6 Divide by 4 Divide by 2 Q5 Q4 Q3 Q2 Q1 No external components needed Divide by 9 Divide by 7 Divide by 5 Divide by 3 Q5 ...

Page 101: ...ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ lin lout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎ...

Page 104: ...MOTOROLA CMOS LOGIC DATA MC14020B 6 66 Figure 3 Timing Diagram CLOCK RESET Q1 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 16 384 8192 4096 1 2 4 8 16 32 64 128 256 512 1024 2048 ...

Page 107: ...ÎÎ 1000 460 350 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn Off Delay Time Reset to Cout tPLH 1 7 ns pF CL 315 ns tPLH 0 66 ns pF CL 142 ns tPLH 0 5 ns pF CL 100 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 175 125 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 800 350 250 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ...

Page 108: ...r Dissipation Test Circuit VDD VSS Cout Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CLOCK CLOCK ENABLE RESET ID PULSE GENERATOR 500 µF 0 01 µF CERAMIC fc CL CL CL CL CL CL CL CL CL APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14022B Decoded outputs are se quential within each stage and from stage to stage with no dead time except propagation delay Fig...

Page 109: ...Q7 Cout tWH tWL trem tPHL tPLH tPLH tPLH tPLH tPLH tTLH tPLH tPLH tPHL tPHL tPHL tPHL tPHL tPHL tTHL tPHL tPHL tTLH tPHL tTHL trel tsu 20 ns 20 ns 20 ns 20 ns 20 ns tPLH tTHL tPLH 50 90 50 10 tTLH tTLH tTLH tTLH tPHL tTLH tTHL tTHL tTLH tPLH 90 50 10 VDD VSS VSS VSS VOL VOL VOL VOL VOL VOL VOL VOL VOL VOH VOH VOH VOH VOH VOH VOH VOH VOH VDD VDD ...

Page 111: ...ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ...

Page 112: ... 300 500 250 180 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 600 230 175 2000 750 565 800 400 300 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 500 165 125 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 60 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ...

Page 113: ...e Characteristics Test Circuit Figure 2 Typical Output Sink Characteristics Test Circuit VDD VDD VSS IOH VOL Vout C R Qn COUNT Qn TO A LOGIC 1 LEVEL VDD VOH Vout VSS IOL C R Qn Figure 3 Power Dissipation Test Circuit VDD 500 µF 0 01 µF CERAMIC PULSE GENERATOR f C R Q7 Q6 Q5 Q4 Q3 Q2 Q1 VSS ID CL CL CL CL CL CL CL ...

Page 114: ...tTLH tTLH tTLH tTLH tTLH tTLH tTLH tPHL1 tPLH2 tPHL2 tPHL3 tPHL4 tPHL5 tPHL6 tPHL7 tPLH3 tPLH4 tPLH5 tPLH6 tPLH7 50 50 50 50 50 50 50 50 90 90 10 10 10 90 tTHL tTHL tTHL tTHL tTHL tTHL tTHL tR1 tR2 tR3 tR4 tR5 tR6 tR7 VDD 1 2 4 8 16 32 64 128 255 VSS VDD VSS VOH VOH VOH VOH VOH VOH VOH VOL VOL VOL VOL VOL VOL VOL Input t and t 20 ns TLH THL ...

Page 115: ...sipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ 260 ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C...

Page 117: ... ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Times ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 50 35 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 70 25 17 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Times ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 50 35 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 70 25 17 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ...

Page 118: ...H VOL 90 50 10 20 ns 20 ns tsu 90 50 10 tsu th 20 ns 20 ns 90 50 10 tWL tWH 1 fcl tPLH tPHL 90 50 10 tTLH tTHL Q C K J Inputs R and S low For the measurement of tWH I fcl and PD the Inputs J and K are kept high 20 ns 20 ns 90 50 10 VDD VSS VDD VSS VOH VOL trem tw 20 ns 20 ns 90 50 10 tw tPLH tPHL 50 Q or Q CLOCK SET OR RESET LOGIC DIAGRAM 1 2 of Device Shown S J K R C C C C C C C C C C C Q Q ...

Page 119: ...ansient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage ...

Page 121: ...s ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time tPLH tPHL 1 7 ns pF CL 215 ns tPLH tPHL 0 66 ns pF CL 97 ns tPLH tPHL 0 5 ns pF CL 65 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 300 130 90 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 600 260 180 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns The formulas given are for the typical characteristi...

Page 122: ...sion Circuit and Truth Table INPUTS D MC14028B C B A D C B A D C B A MC14028B Q9 Q0 Q9 Q0 15 8 15 0 OUTPUT NUMBERS Code and Redefined Output Numbers Hexadecimal Decimal Inputs Output Numbers D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 2 0 0 1 1 0 0 0 0 0...

Page 123: ...14028B Q0 Q9 A B C D MC14028B Q0 Q9 A B C D MC14028B Q0 Q9 A B C D MC14028B Q0 Q9 A B C D MC14028B Q0 Q9 A B C D MC14028B Q0 Q9 7 0 8 15 16 23 24 31 32 39 40 47 48 55 56 63 1 6 MC14069UB 64 OUTPUTS SELECTED OUTPUT IS HIGH Figure 4 Decimal Digit Display Application A Q9 MC14028B B C D Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 9 0 2 9 1 0 APPROPRIATE VOLTAGE NEON DISPLAY APPROPRIATE VOLTAGE INCANDESCENT DISPLAY OR...

Page 124: ...ÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ VDD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin Vout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎ...

Page 125: ...5 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ...

Page 126: ...60 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PE to Cout tPLH tPHL 1 7 ns pF CL 465 ns tPLH tPHL 0 66 ns pF CL 192 ns tPLH tPHL 0 5 ns pF CL 125 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 320 145 105 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 640 290 210 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ...

Page 127: ... CL CL CL VDD VSS 20 ns 20 ns CLK 50 90 10 VARIABLE WIDTH Figure 2 Switching Time Test Circuit and Waveforms PROGRAMMABLE PULSE GENERATOR VDD PE Cin B D U D CLK P0 P1 P2 P3 Cout Q3 Q2 Q1 Q0 CL VSS CL CL CL CL tW tsu trem 1 fcl 50 50 tW Cout ONLY tTLH tPLH tPLH tPHL tTHL 90 10 90 10 20 ns CARRY IN OR UP DOWN OR BINARY DECADE CLOCK PRESET ENABLE Q0 OR CARRY OUT VDD VSS VDD VSS VDD VSS VOH VOL ...

Page 128: ...vide by N BCD Down Counter and Timing Diagram Shown for N 123 Q3 Q2 Q1 Q0 P3 P2 P1 P0 CLK Cout U D B D Q3 Q2 Q1 Q0 P3 P2 P1 P0 CLK Cout U D B D Q3 Q2 Q1 Q0 P3 P2 P1 P0 CLK Cout U D B D Cin PE Cin PE Cin PE MC14029B MSD MC14029B MC14029B LSD OUTPUT INPUT CLOCK 1 2 3 VDD VDD VDD VDD CLOCK Cout 1 LSD Cout 2 Cout 3 MSD PE COUNT 123 122 121 120 119 101 100 99 11 10 9 1 0 123 122 tW 900 ns VDD 5 V ...

Page 129: ...TA 6 91 MC14029B LOGIC DIAGRAM BINARY DECADE PRESET ENABLE CARRY IN UP DOWN CLOCK 9 1 5 10 15 4 P0 12 P1 13 P2 3 P3 2 Q3 14 Q2 1 Q1 6 Q0 7 CARRY OUT PE TE CLK P3 Q3 Q3 PE TE CLK P2 Q2 Q2 PE TE CLK P1 Q1 Q1 PE TE CLK P0 Q0 Q0 ...

Page 130: ...ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 1...

Page 131: ... Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 ...

Page 132: ...ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 500 180 135 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2400 600 450 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Setup Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 10 10 10 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 10 0 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns Î...

Page 133: ... CLOCK CR S3 S2 S1 EXTERNAL POWER SUPPLY EXTERNAL POWER SUPPLY VDS VOL VOL VDD VGS VDD VSS IOL A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CR S3 S2 S1 Figure 3 Power Dissipation Test Circuit and Waveforms VDD VDD VSS 500 pF 0 01 µF CERAMIC PROGRAMMABLE PULSE GENERATOR A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CR S3 S2 S1 CL CL CL CLOCK A B 20 ns 20 ns VDD VSS VDD VSS tTLH tTHL 90 10 50 90 10 VARIABLE WIDT...

Page 134: ...SS PROGRAMMABLE PULSE GENERATOR A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CR S3 S2 S1 CL CL CL MC14038B MC14032B A B CLOCK SUM 50 50 50 tPLH tPHL tPLH tPHL tTLH tTHL VDD VSS VDD VSS VDD VSS VOH VOL tsu A B CLOCK SUM 50 50 50 tPHL tPLH tPHL tPLH tTLH tTHL tsu VDD VSS VDD VSS VDD VSS VOH VOL 90 50 10 90 50 10 ...

Page 135: ...Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ...

Page 137: ...55 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ fcl ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 5 6 0 8 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 2 3 0 4 0 ÎÎÎ ÎÎÎ ÎÎÎ MHz ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Rise ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tTLH tTHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎ...

Page 138: ...ta lines A B Input Data A or B This input controls the direc tion of data flow when high the data flows from bus A to bus B when low the data flows from bus B to bus A P S Input Parallel Serial This input controls the data input mode parallel or serial When high the data is trans ferred to the register in a parallel asynchronous mode or a parallel synchronous mode positive clock transition When lo...

Page 139: ...ION TIME TEST CIRCUITS Figure 2 A Synchronous Data Input B Parallel Data Output and Setup Time Figure 3 B Synchronous Data Input A Parallel Data Output and Setup Time PROGRAMMABLE PULSE GENERATOR PROGRAMMABLE PULSE GENERATOR CL CL VSS VDD VDD VSS A1 A2 A3 A4 A5 A6 A7 A8 A ENABLE P S DS A B A S C B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 A ENABLE P S DS A B A S C B1 B2 B3 B4 B5 B6 B7 B8 ...

Page 140: ... VDD VSS 20 ns 20 ns 90 10 50 tWH tWL 90 10 50 20 ns 20 ns DS CLOCK 1 f tWH tWL 50 DUTY CYCLE Figure 5 16 Bit Parallel In Parallel Out Parallel In Serial Out Serial In Parallel Out Serial In Serial Out Register VDD VDD SERIAL DATA VDD P S A S CLOCK SERIAL DATA SERIAL DATA VDD A ENABLE P S DS A B A S CB1 A1 B2 B3 B4 B5 B6 B7 B8 A2 A3 A4 A5 A6 A7 A8 MC14034B A ENABLE P S DS A B A S CB1 A1 B2 B3 B4 B...

Page 141: ...lel data into registers 1 and 2 Other logic schemes may be used in place of registers 3 and 4 for parallel loading When parallel inputs are not used Reg 3 and 4 and associated logic are not required Shift left input must be disabled during parallel entry A ENABLE SHIFT LEFT SHIFT RIGHT SHIFT RIGHT INPUT CLOCK A S PARALLEL ENTRY REGISTER 1 MC14034B SHIFT LEFT OUTPUT AE P S DS A B A S CB1 B8 A1 A8 A...

Page 143: ... 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎ...

Page 145: ...0 D Q R C D Q R C D Q R C D Q R C APPLICATION DIAGRAM Shift Left Shift Right Register LEFT SHIFT SERIAL INPUT RIGHT SHIFT SERIAL INPUT RESET CLOCK LEFT RIGHT SHIFT SELECT LEFT SHIFT SERIAL OUTPUT RIGHT SHIFT SERIAL OUTPUT Q0 Q1 Q2 Q3 VDD VDD 16 VDD 15 Q1 14 Q2 13 Q3 12 DP3 11 DP2 10 DP1 9 DP0 Q0 1 T C 2 K 3 J 4 R 5 C 6 P S 7 VSS 8 ...

Page 146: ...ÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ ...

Page 149: ...hm resistor connected directly to a standard 120 Vac power line is applied to the clock input of the MC14040B By selecting outputs Q5 Q10 Q11 and Q12 division by 3600 is ac complished The MC14012B decodes the counter outputs produces a single output pulse and resets the binary count er The resulting output frequency is 1 0 pulse minute VDD VSS 120 Vac 60 Hz 1 0 M 20 pF MC14040B C R Q12 Q11 Q10 Q5 ...

Page 150: ...ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin Vout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ lin loutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500...

Page 151: ...25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 36 0 9 2 4 ÎÎÎ ÎÎÎ...

Page 153: ...o output under test 20 ns 20 ns 90 10 PULSE GENERATOR 1 PULSE GENERATOR 2 VDD 16 5 6 4 7 13 14 CLOCK POLARITY D0 D1 D2 D3 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VSS 8 15 1 12 11 9 10 3 2 50 tWH 20 ns 90 50 tsu th tPLH 90 50 10 CLOCK INPUT P G 1 DATA INPUT P G 2 Q OUTPUT Input clock rise time is 20 ns except for maximum rise time test ...

Page 154: ...e Outputs Capable of Driving Two Low power TTL Loads or One Low Power Schottky TTL Load Over the Rated Temperature Range Supply Voltage Range 3 0 Vdc to 18 Vdc MC14043B TRUTH TABLE X Don t Care MC14044B S R E Q High Impedance X X 0 No Change 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 TRUTH TABLE X Don t Care S R E Q High Impedance X X 0 0 1 0 No Change 0 0 1 1 0 1 0 1 1 1 1 1 ENABLE R3 S3 R2 S2 R1 S1 R0 S0 4 3...

Page 155: ...ÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0...

Page 156: ...ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time tPLH 0 90 ns pF CL 130 ns tPLH 0 36 ns pF CL 57 ns tPLH 0 26 ns pF CL 47 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 175 75 60 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 350 175 120 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL 0 90 ns pF CL 130 ns tPHL 0...

Page 157: ...Open B VSS VDD VDD VSS tPHZ Open Closed A VDD VSS VSS VDD tPLZ Closed Open B VSS VDD VDD VSS ENABLE QA QB 50 tPZH 10 tPZL tPHZ tPLZ 10 90 VDD VSS VDD VOL VOH VSS PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 S2 NC S3 R3 VDD Q1 Q2 R2 S0 R0 Q0 Q3 VSS R1 S1 E 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 R2 Q0 R3 S3 VDD Q1 Q2 S2 R0 S0 NC Q3 VSS S1 R1 E NC NO CONNECTION MC14043B MC14044B TO OUTPUT UN...

Page 158: ... can be tolerated The inhibit input Inh when high disables the VCO and source follower to minimize standby power consumption The zener diode can be used to assist in power supply regulation Applications include FM and FSK modulation and demodulation fre quency synthesis and multiplication frequency discrimination tone decod ing data synchronization and conditioning voltage to frequency conversion ...

Page 159: ...Vdc ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ VO 0 5 or 4 5 Vdc 1 Level VO 1 0 or 9 0 Vdc VO 1 5 or 13 5 Vdc ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VIH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3 5 7 0 11 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 5 7 0 11 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 75 5 50 8 25 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3 5 7 0 11 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ...

Page 160: ...OLLED OSCILLATOR VCO ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Frequency VCOin VDD C1 50 pF R1 5 0 kΩ and R2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ fmax ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 5 1 0 1 4 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0 7 1 4 1 9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ MHz ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Temperature Frequency Stability R2 ÎÎÎÎ ÎÎÎ...

Page 162: ... Design Articles AR254 reprinted by Motorola Inc PCAin FREQUENCY f PCBin 14 3 PHASE COMPARATOR EXTERNAL LOW PASS FILTER VCO 2 OR 13 PC1out OR PC2out VCOin 9 9 10 4 EXTERNAL N COUNTER R1 R2 11 12 6 7 CIA CIB CI SFout RSF VCOout FREQUENCY Nf f a INPUT R3 OUTPUT C2 2fC 1 p 2 pfL R3 C2 Ǹ a INPUT R3 OUTPUT R4 C2 Typically R4 C2 6N fmax N 2 p D f R3 3 000W C2 100NDf fmax2 R4 C2 f fmax fmin Definitions N...

Page 163: ...ÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage DC or Transient ÎÎÎ VINÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage DC or Transient ÎÎÎ ÎÎÎ Vout ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Input Current DC or Transient per Pin ÎÎÎ ÎÎÎ Iin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Output Current DC or Transient per Pin ÎÎÎ ÎÎ...

Page 165: ...gation Delay Time tPLH 0 33 ns pF CL 63 5 ns tPLH 0 19 ns pF CL 30 5 ns tPLH 0 06 ns pF CL 27 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 80 40 30 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 80 60 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time tPHL 0 2 ns pF CL 30 ns tPHL 0 1 ns pF CL 15 ns tPHL 0 05 ns pF CL 12 5 ...

Page 166: ...0 400 300 200 100 0 175 150 125 100 75 50 25 TA AMBIENT TEMPERATURE C 260 mW L 175 mW P 120 mW D L CERAMIC P PDIP D SOIC tPHL Figure 4 Switching Time Test Circuit and Waveforms PULSE GENERATOR VDD VSS 8 1 CL Vout Vin Invert on MC14049B only 20 ns 20 ns VDD VSS VOH VOL VOH VOL 90 50 10 90 50 10 90 50 10 tPLH tTLH tPHL tTHL tPHL tPLH tTLH tTHL OUTPUT MC14049B OUTPUT MC14050B INPUT ...

Page 168: ...put Drive Current VOH 2 5 Vdc Source VOH 9 5 Vdc VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 6 1 6 4 7 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 25 1 3 3 75 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 5 2 6 10 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 0 1 0 3 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL Î...

Page 169: ...10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 40 20 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 60 40 30 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time tPLH 0 38 ns pF CL 61 ns tPLH 0 20 ns pF CL 30 ns tPLH 0 11 ns pF CL 24 5 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 80 40 30 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1...

Page 170: ...50 25 TA AMBIENT TEMPERATURE C 260 mW L 175 mW P 120 mW D L CERAMIC P PDIP D SOIC PULSE GENERATOR VDD VSS 8 1 CL Vout Vin 20 ns 20 ns VDD VSS VOH VOL 90 50 10 90 50 10 tPLH tTLH tTHL tPHL OUTPUT INPUT Figure 5 Switching Time Test Circuit and Waveforms This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin only Ex...

Page 172: ...SWITCHES IN OUT AND COMMONS OUT IN X Y Z Voltages Referenced to VEE ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Recommended Peak to Peak Voltage Into or Out of the Switch ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VI O ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Channel On or Off ÎÎÎ ÎÎÎ ÎÎÎ 0ÎÎÎ ÎÎÎ ÎÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ 0 ÎÎ ÎÎ ÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ VPP ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Recommended Static or Dynamic V...

Page 174: ... Y1 X0 0 1 1 1 X7 Z1 Y1 X1 1 x x x None None None Not applicable for MC14052 x Don t Care Figure 3 MC14052B Functional Diagram Figure 4 MC14053B Functional Diagram 16 VDD 8 VSS 7 VEE 13 X 3 Y BINARY TO 1 OF 4 DECODER WITH INHIBIT LEVEL CONVERTER INH 6 A 10 B 9 X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 BINARY TO 1 OF 2 DECODER WITH INHIBIT LEVEL CONVERTER 16 VDD 8 VSS 7 VEE 14 X 15 Y 4 Z INH 6 A ...

Page 175: ... Crosstalk Control Input to Common O I Figure 10 Off Channel Leakage CONTROL SECTION OF IC SOURCE V ON SWITCH PULSE GENERATOR INH A B C RL CL Vout VDD VEE VEE VDD INH A B C VSS Vin RL CL 50 pF Vout VDD VEE 2 INH A B C OFF ON RL RL CL 50 pF Vout Vin VDD VEE 2 INH A B C R1 RL CL 50 pF Vout CONTROL SECTION OF IC OFF CHANNEL UNDER TEST OTHER CHANNEL S COMMON VDD VEE VEE VDD VEE VDD NOTE See also Figur...

Page 176: ... 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C Figure 14 VDD 2 5 V VEE 2 5 V R ON ON RESISTANCE OHMS 700 600 500 400 300 200 0 100 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C Figure 15 Comparison at 25 C VDD VEE R ON ON RESISTANCE OHMS 350 300 250 200 150 100 0 50 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 25 C VDD 2 5 V 5 0 V 7 5 V ...

Page 177: ... to 15 V which is the recommended maximum difference between VDD and VEE Balanced supplies are not required However VSS must be greater than or equal to VEE For example VDD 10 V VSS 5 V and VEE 3 V is acceptable See the Table below Figure A Application Example 5 V 5 V VDD VSS VEE 9 Vp p ANALOG SIGNAL 0 TO 5 V DIGITAL CONTROL SIGNALS SWITCH I O INHIBIT A B C COMMON O I 9 Vp p ANALOG SIGNAL 4 5 V 4 ...

Page 178: ... V Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range Buffered Outputs Available from Stages 4 Through 10 and 12 Through 14 Common Reset Line Pin for Pin Replacement for CD4060B TRUTH TABLE Clock Reset Output State L No Change L Advance to next state X H All Outputs are low X Don t Care LOGIC DIAGRAM OUT 2 OUT 1 CLOCK RESET 12 11 10 9 Q4 ...

Page 179: ...ut Voltage 0 Level VO 4 5 Vdc For Input 11 VO 9 0 Vdc and Output 10 VO 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 0 2 0 2 5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 25 4 50 6 75 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 0 2 0 2 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1 0 2 0 2 5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VO 0 5 Vdc 1 Level VO 1 0 Vdc V...

Page 180: ...ÎÎ ÎÎÎÎ ÎÎÎÎ twH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 40 30 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 65 30 20 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ fφ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 14 17 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3 5 8 12 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ MHz ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ...

Page 181: ...1 RESET 9 OUT 2 10 OUT 1 18M RO CS CT ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Characteristic ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 500 kHz Circuit ÎÎÎ ÎÎÎ ÎÎÎ 32 kHz Circuit ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Crystal Characteristics Resonant Frequency Equivalent Resistance RS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 500 1 0 ÎÎÎ ÎÎÎ ÎÎÎ 32 6 2 ÎÎÎ ÎÎÎ ÎÎÎ kHz kΩ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ External Resistor Capacitor Values RO CT CS...

Page 183: ...ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 ÎÎÎ ÎÎÎ 7 5 ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ pF ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHES IN AND OUT Voltages Referenced to VSS ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Recommended Peak to Peak Voltage Into or Out of the Switch ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VI O ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Channel On or Off ÎÎÎ ÎÎÎ ÎÎÎ 0 ÎÎ ÎÎ ÎÎ VDD ÎÎÎ ÎÎÎ...

Page 184: ...5 Vdc Vin 1 77 Vdc RMS Centered 0 0 Vdc RL 10 kΩ f 1 0 kHz ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Bandwidth Switch ON Figure 3 VSS 5 Vdc RL 1 kΩ 20 Log Vout Vin 3 dB CL 50 pF Vin 5 Vp p ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ...

Page 185: ...Output Figure 6 Off Channel Leakage CONTROL SECTION OF IC SOURCE V LOAD ON SWITCH Vout Vout VC VC Vout Vin RL CL 20 ns VDD VSS 90 50 10 tPZH tPHZ tPZL tPLZ 10 90 10 Vx Vout CL RL VDD VSS VC Vin VDD VSS 2 VDD VSS 2 Vin VDD VSS RL CL RL CL Vin 1 k Vout RL CL 50 pF VC 5 0 V TO 5 0 V SWING VC VDD FOR BANDWIDTH TEST VC VSS FOR FEEDTHROUGH TEST OFF CHANNEL UNDER TEST VDD VSS VSS VDD A CONTROL SECTION OF...

Page 186: ... 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C R ON ON RESISTANCE OHMS 350 300 250 200 150 100 0 50 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C Figure 10 VDD 2 5 V VSS 2 5 V R ON ON RESISTANCE OHMS 700 600 500 400 300 200 0 100 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C Figure 11 Comparison at 25 C VDD VSS R ON ON R...

Page 187: ...peak signal which allows no margin at either peak If voltage transients above VDD and or below VSS are anticipated on the analog chan nels external diodes Dx are recommended as shown in Figure B These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping The absolute maximum potential difference between VDD and VSS is 18 0 volts Most parameters a...

Page 188: ...itches see MC14097 truth table Low OFF Leakage Current Matched Channel Resistance Low Quiescent Power Consumption Low Crosstalk Between Channels Wide Operating Voltage Range 3 to 18 V Low Noise Pin for Pin Replacement for CD4067B and CD4097B MC14067B 16 Channel Analog Multiplexer Demultiplexer MC14097B Dual 8 Channel Analog Multiplexer Demultiplexer CONTROLS SWITCHES IN OUT COMMON OUT IN 16 17 18 ...

Page 189: ...eramic L Packages 12 mW _C From 100_C To 125_C MC14067 TRUTH TABLE Control Inputs Selected A B C D Inh Selected Channel X X X X 1 None 0 0 0 0 0 X0 1 0 0 0 0 X1 0 1 0 0 0 X2 1 1 0 0 0 X3 0 0 1 0 0 X4 1 0 1 0 0 X5 0 1 1 0 0 X6 1 1 1 0 0 X7 0 0 0 1 0 X8 1 0 0 1 0 X9 0 1 0 1 0 X10 1 1 0 1 0 X11 0 0 1 1 0 X12 1 0 1 1 0 X13 0 1 1 1 0 X14 1 1 1 1 0 X15 MC14097 TRUTH TABLE Control Inputs Selected A B C I...

Page 190: ...ferenced to VSS ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Recommended Peak to Peak Voltage Into or Out of the Switch ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VI O ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Channel On or Off ÎÎ ÎÎ ÎÎ ÎÎ 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 ÎÎ ÎÎ ÎÎ ÎÎ VDD ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vp p ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Recommended Sta...

Page 191: ...7B ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 280 115 85 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 700 290 215 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC14097B ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Figure 10 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 250 100 75 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 625 250 190 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ...

Page 192: ...L UNDER TEST OTHER CHANNEL S VDD VSS VSS VDD VSS VDD A X3 X5 X6 X7 X X1 X2 X4 X11 X10 X9 X8 VDD INHIBIT X15 X14 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 D C X13 X12 B VSS A X0 MC14067B PIN ASSIGNMENT MC14097B PIN ASSIGNMENT X3 X5 X6 X7 X X1 X2 X4 Y3 Y2 Y1 Y0 VDD Y7 Y6 Y 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 INHIBIT C Y5 Y4 B VSS A X0 ...

Page 193: ... A B C D INH RL CL 50 pF Vout Vin VDD VSS VSS VDD VX 20 ns 20 ns 90 50 10 90 10 Vout Vout VC 50 50 tPZH tPZL tPHZ tPLZ Vin VDD VX VSS Vin VSS VX VDD Figure 5 Bandwidth and Off Channel Feedthrough Attenuation Figure 6 Channel Separation Adjacent Channels Used for Setup A B and C inputs used to turn ON or OFF the switch under test A B C D INH Vin RL CL 50 pF Vout VDD RL Vout CL 50 pF RL Vin A B C D ...

Page 194: ... OHMS 350 300 250 200 150 100 0 50 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C R ON ON RESISTANCE OHMS 350 300 250 200 150 100 0 50 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS TA 125 C 25 C 55 C Figure 12 VDD 2 5 V VSS 2 5 V R ON ON RESISTANCE OHMS 700 600 500 400 300 200 0 100 8 0 10 6 0 4 0 2 0 0 0 2 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLT...

Page 195: ... Vp p signal which allows no margin at either peak If voltage transients above VDD and or below VSS are anticipated on the analog channels external diodes Dx are recommended as shown in Figure B These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping The absolute maximum potential difference between VDD and VSS is 18 0 volts Most parameters a...

Page 196: ...r Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond...

Page 198: ...Î mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plast...

Page 202: ...Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 260 110 80 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 130 55 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Reset Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 370 150 110 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 185 75 55 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ...

Page 203: ... AND tPZL VSS FOR tPHZ AND tPZH OUTPUT DISABLE A OR B ANY Q OUTPUT ANY Q OUTPUT 20 ns 20 ns VDD VSS VOH 90 50 50 10 tPLZ tPZL 90 tPZH tPHZ 90 10 10 2 5 V VDD 5 V 10 V AND 15 V 2 V VDD 5 V 6 V VDD 10 V 10 V VDD 15 V VOL OUTPUTS CONNECTED OUTPUTS DISCONNECTED OUTPUTS CONNECTED tPLH EQUIVALENT FUNCTIONAL BLOCK DIAGRAM OUTPUT DISABLE A OUTPUT DISABLE B D0 1 2 14 DATA DISABLE A DATA DISABLE B 9 10 D1 1...

Page 204: ... Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are ...

Page 205: ...citance Vin 0 ÎÎÎÎ ÎÎÎÎ Cin ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 ÎÎÎ ÎÎÎ 7 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ pF ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Quiescent Current Per Package ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IDD ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 25 0 5 1 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 0005 0 0010 0 0015 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 25 0 5 1 0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ...

Page 206: ...ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 80 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 250 100 80 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns Data labeled Typ is not to be used for design purposes but is intended as an...

Page 207: ... DRAIN CURRENT mAdc 14 7 VGS Vout IOH All unused inputs connected to ground All unused inputs connected to ground 14 7 Vout IOL VGS V out OUTPUT VOLTAGE Vdc VDD 0 0 VDD VT VT VH Vin INPUT VOLTAGE Vdc Figure 5 Typical Transfer Characteristics VGS 5 0 Vdc c b a c b c b a a 15 Vdc 10 Vdc a TA 55 C b TA 25 C b TA 125 C a b c a b c a b c 5 0 Vdc a TA 55 C b TA 25 C c TA 125 C PIN ASSIGNMENT 11 12 13 14...

Page 208: ...tput Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values...

Page 210: ...ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 290 145 100 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 580 290 200 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Enable to Output tPHZ tPZL 0 90 ns pF CL 95 ns tPHZ tPZL 0 36 ns PF CL 57 ns tPHZ tPZL 0 26 ns pF CL 42 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPHZ tPZL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 75 55 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 280 1...

Page 211: ...E 6 REGISTER STAGE 7 REGISTER STAGE 8 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 3 STATE BUFFER 2 3 STATE BUFFER 3 3 STATE BUFFER 4 3 STATE BUFFER 5 3 STATE BUFFER 6 3 STATE BUFFER 7 3 STATE BUFFER 8 CLOCK CLOCK STROBE STROBE CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK STROBE STROBE CLOCK STROBE 3 1 Input Protection Diodes DYNAMIC TIMING DIAGRAM 3 15 CLOCK 2 DATA IN 1 STROBE OUTPUT ENABLE N Q...

Page 212: ... Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C MC14099B MC14599B 13 14 15 16 9 10 11 1...

Page 213: ...ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ...

Page 214: ...ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 80 65 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 160 130 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Address to Data ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 90 75 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 180 150 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ...

Page 215: ...d Latch Unaddressed Latches 0 0 Data Qn 0 1 Data Reset 1 0 Qn Qn 1 1 Reset Reset Qn is previous state of latch Reset to zero state SWITCHING WAVEFORMS DATA OR WRITE DISABLE OUTPUT Q RESET OUTPUT Q VDD VSS VDD VSS tPHL 50 tTLH tTHL 90 50 10 50 tPLH tPHL ADDRESS WRITE DISABLE DATA VDD VSS VDD VSS VDD VSS 50 50 50 tsu tw L trem tsu th tw H CAUTION To avoid unintentional data changes in the latches Wr...

Page 216: ... 13 Q2 12 Q1 11 Q0 MC14599B FUNCTION DIAGRAM TRUTH TABLE Chip Enable Write Read Write Disable Reset Addressed Latch Other Latches Data Pin 0 X X 0 Z 1 1 0 0 Data Input 1 1 1 0 Z 1 0 X 0 Qn X X X 1 0 0 Z 0 X Don t care No change in state of latch Z High impedance Qn State of addressed latch CAUTION To avoid unintentional data changes in the latches Write Disable must be active high during transitio...

Page 217: ... WRITE DISABLE DATA A2 A1 A0 CE RESET Q7 Q0 tPHL tTLH tPHL 50 90 10 90 10 tTHL tPLH tPLH tw H 50 50 50 50 10 10 90 20 ns 20 ns tsu tw L trem th tsu A2 A1 A0 DATA CE W R VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS 50 tPLH tPHL tPLH tPHL 50 1 NOTE 1 Invalid Data Output 2 Reset in LOW State ...

Page 218: ...Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those valu...

Page 219: ...ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Output Drive Current VOH 2 5 Vdc Source VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ...

Page 220: ... 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 80 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 250 100 80 ÎÎÎ ÎÎÎ ÎÎÎ ns Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Switching Ti...

Page 221: ... C R 1 f t1 t2 t1 RCln VT VT t2 RCln VDD VT VDD VT 1 f RClnƪǒVDD VT VDD VT ǓǒVT VT Ǔƫ t1 t2 tPHL tPLH Figure 6 Integrator R A Vin Vout C VSS VT VDD Vin VSS VT VDD A VSS VT VDD Vout Useful in discriminating against short pulse durations Figure 7 Differentiator Figure 8 Positive Edge Time Delay Circuit C R EDGE EDGE VDD Vin EDGE EDGE tw tw RC ln VDD VT Useful as an edge detector circuit C C C R R R ...

Page 223: ...c VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ...

Page 224: ...ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Times Data to Clock ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 320 130 90 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 160 65 45 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Load to Clock ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 600...

Page 225: ...Î ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width High ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 250 100 70 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125 50 35 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Rise and Fall Time ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr tf ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 15 5 0 4 0 ÎÎÎ ÎÎÎ ÎÎÎ ...

Page 226: ...s all four of the flip flop outputs low after the next clock pulse regardless of the levels of the enable inputs This synchronous clear allows the count length to be modi fied easily decoding the maximum count desired can be ac complished with one external NAND gate The gate output is connected to the clear input to synchronously clear the counter to 0000 LLLL The carry look ahead circuitry provid...

Page 227: ...MOTOROLA CMOS LOGIC DATA 6 189 MC14160B MC14161B MC14162B MC14163B MC14160B MC14162B LOGIC DIAGRAM Clear is synchronous for MC14162B ...

Page 228: ...GIC DATA MC14160B MC14161B MC14162B MC14163B 6 190 MC14160B MC14162B TIMING DIAGRAM Sequence illustrated in waveforms 1 Clear outputs to zero 2 Preset to BCD seven 3 Count to eight nine zero one two and three 4 Inhibit ...

Page 229: ...MOTOROLA CMOS LOGIC DATA 6 191 MC14160B MC14161B MC14162B MC14163B MC14161B MC14163B LOGIC DIAGRAM Clear is synchronous for MC14163B ...

Page 230: ...A MC14160B MC14161B MC14162B MC14163B 6 192 MC14161B MC14163B TIMING DIAGRAM Sequence illustrated in waveforms 1 Clear outputs to zero 2 Preset to binary twelve 3 Count to thirteen fourteen fifteen zero one and two 4 Inhibit ...

Page 231: ...n ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device ...

Page 232: ...urrent VOH 2 5 Vdc Source VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 ...

Page 233: ...h ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 150 90 70 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 75 45 35 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Reset Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 80 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 50 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ...

Page 234: ...MOTOROLA CMOS LOGIC DATA MC14174B 6 196 FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM ...

Page 235: ... or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which d...

Page 236: ...OH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 64 1 6 4 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 4 0 51 1 3 3 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 2 0 88 2 25 8 8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1 7 0 36 0 9 2 4 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ...

Page 237: ...ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 250 100 75 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 110 45 35 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Reset Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 80 60 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 100 40 30 ÎÎÎÎ ÎÎÎÎ ...

Page 238: ...MOTOROLA CMOS LOGIC DATA MC14175B 6 200 FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM ...

Page 241: ...ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 280 110 85 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 55 40 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Reset Pulse Width ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tWH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 180 70 50 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 90 35 26 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency Shift Right or Left Mode ÎÎÎÎ ÎÎÎÎ...

Page 242: ...5 6 11 2 7 9 10 1 NOTE Interchange DSR with DSL and S0 with S1 for testing shift left 20 ns 20 ns 90 50 10 DPn DSR DSL CLOCK Qn RESET th tsu tsu th 50 90 50 10 tTLH tTHL tPLH tPHL tWH cl 1 fcl tPHL trem tWL 50 VDD VSS VDD VSS VOH VOL VDD VSS Parallel Load Serial Load Figure 2 Dynamic Power Dissipation Test Circuit and Waveforms PULSE GENERATOR CL CL CL CL 3 4 5 6 11 2 7 9 10 1 VDD 16 DP0 DP1 DP2 D...

Page 245: ...ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn On Delay Time Inhibit to Output ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPHL ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 300 225 110 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 550 425 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn Off Delay Time Inhibit to Output ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ...

Page 246: ... 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A 50 50 50 tPLH tPHL MINIMUM COINCIDENCE 500 ns VDD 4 75 Vdc 100 2 1 INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A 50 50 100 2 1 tPLH tPHL MINIMUM COINCIDENCE 500 ns VDD 4 75 Vdc INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A tPLH tPHL tPLH tPHL 100 2 1 50 50 INPUT DISABLE STROBE 2 STRO...

Page 247: ...HRONOUS COUNTER ENABLE C1 C2 DIVIDE BY 100 SYNCHRONOUS COUNTER ENABLE C1 C2 V DD V SS V DD V SS V DD V SS V DD V SS 14 OUTPUT A 13 OUTPUT B 12 OUTPUT C 11 OUTPUT D S R Q S R Q S R Q S R Q C1 C2 SCHMITT CLOCK CONDITIONING CIRCUIT 15 OUTPUT INHIBIT SET A 3 SET B 4 SET C 5 SET D 6 OUTPUT SET 2 STROBE 2 9 STROBE 1 7 INPUT DISABLE 10 CLOCK 1 LOGIC DIAGRAM ...

Page 248: ...ll Inputs Six Debouncers Per Package Internal Pullups on All Data Inputs Can Be Used as a Digital Integrator System Synchronizer or Delay Line Internal Oscillator R C or External Clock Source TTL Compatible Data Inputs Outputs Single Line Input Debounces Both Make and Break Contacts Does Not Require Form C Single Pole Double Throw Input Signal Cascadable for Longer Time Delays Schmitt Trigger on C...

Page 251: ...s from the beginning of the clean input signal After some time period of N clock periods the contact is opened and at N 1 a low is loaded into the first bit Just after N 1 when the input bounces low all bits are set to a high At N 2 nothing happens because the input and output are low and all bits of the shift register are high At time N 3 and thereafter the input signal is a high clean signal At ...

Page 252: ...in pullup resistors the inputs cannot be driven with a single standard CMOS gate when VDD is be low 5 V At this voltage the input should be driven with paral leled standard gates or by the MC14049 or MC14050 buffers The clock input circuit pin 7 has Schmitt trigger shaping such that proper clocking will occur even with very slow clock edges eliminating any need for clock preshaping In addi tion ot...

Page 253: ...s earlier Figure 7 Latched Output Circuit IN OUT OSCout MC14011B OSCin MC14490 CLOCK LATCH 1 UNLATCH 0 MULTIPLE TIMING SIGNALS As shown in Figure 8 the Bounce Eliminator circuits can be connected in series In this configuration each output is delayed by four clock periods relative to its respective input This configuration may be used to generate multiple timing signals such as a delay line for pr...

Page 254: ...s protection circuitry to guard against damage due to high static voltages or electric fields However precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit For proper operation Vin and Vout should be constrained to the range VSS Vin or Vout VDD Unused inputs must always be tied to an appropriate logic voltage level e g eith...

Page 255: ...at VDD 5 V On Chip Clock Oscillator Executes One Instruction per Clock Cycle 3 to 18 V Operation Low Quiescent Current Characteristic of CMOS Devices Capable of Driving One Low Power Schottky Load or Two Low Power TTL Loads over Full Temperature Range BLOCK DIAGRAM DATA X1 X2 I0 I1 I2 I3 RST 3 14 13 7 6 5 4 1 INST REG OSC D C IEN LU D C RESULT REG RR MUX D C 16 2 8 WRITE VDD VSS 15 12 11 10 9 RR J...

Page 257: ...ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ X1 to Flag F Flag O RTN JMP ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 200 100 85 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 400 200 170 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ X1 to Write ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 225 125 100 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 450 250 200 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ...

Page 259: ...ctions SKZ JMP RTN Instructions RR IEN OEN remain unaffected X1 RST IEN REGISTER OEN REGISTER RR 4 BIT INSTRUCTION FLAG 0 FLAG F tW R tPHL RESET TO XI tPHL RESET TO RR NOP0 NOPF NOPO tPLH DATA TO FLAG tPHL X1 4 BIT INSTRUCTION RST RR JMP FLAG RTN FLAG SKP F F INTERNAL Instructions Ignored tW cl SKZ JMP RTN JMP tPHL RESET TO JUMP ...

Page 260: ...OR ORC XNOR IEN ÉÉÉÉÉÉ ÉÉÉÉÉÉ 1 X1 4 BIT INSTRUCTION DATA RR OEN REGISTER INTERNAL WRITE STO STOC STO STOC NOP OEN STO STOC tPLH tPHL X1 TO DATA tPHL tPLH VALID WHEN RST L NOTE 1 Valid output data X1 4 BIT INSTRUCTION DATA RR IEN REGISTER INTERNAL LD etc tsu D tsu I NOP IEN LD etc th I th D tPLH tPHL X1 TO RR VALID WHEN RST L ...

Page 262: ... 0 24 0 62 1 84 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOH 2 5 Vdc NOR VOH 4 6 Vdc VOH 9 5 Vdc Inverter VOH 13 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 6 0 72 1 8 5 4 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 0 0 6 1 5 4 5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 1 1 08 2 7 10 5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 1 0 42 1 05 3 15 ÎÎÎ ÎÎÎ ÎÎÎ Î...

Page 263: ...ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 60 40 30 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 120 80 60 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time NAND tPLH tPHL 1 7 ns pF CL 45 ns tPLH tPHL 0 66 ns pF CL 37 ns tPLH tPHL 0 5 ns pF CL 25 ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tPLH tPHL ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 50 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 130 7...

Page 264: ... Figure 2 Input NAND Gate Switching Time Test Circuit and Waveforms PULSE GENERATOR VDD 16 INPUT A 8 VSS CL OUTPUT B 20 ns 20 ns VDD VSS 90 50 10 50 90 10 OUTPUT B INPUT A tPHL tPLH VOH VOL tTHL tTLH 90 50 10 90 50 10 Figure 3 NOR Gate and NOR Inverter Switching Time Test Circuit and Waveforms PULSE GENERATOR CL 20 ns VDD 90 OUTPUT B tTHL INPUT A OUTPUT C CL INPUT A OUTPUT B OUTPUT C VSS VOH VOL V...

Page 266: ...ÎÎÎÎÎ VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOL ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 10 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 3 5 7 8 29 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2 8 6 3 24 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 6 6 17 66 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 0 4 4 16 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mAdc ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Input Current ÎÎÎÎ ÎÎÎÎ Iin ÎÎÎ ÎÎÎ 15 ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 1 ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 00001ÎÎÎ ÎÎÎ...

Page 267: ...H ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 295 130 95 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 590 260 190 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 3 State Propagation Delay Output 1 to High Impedance ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPHZ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 65 30 25 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 130 60 50 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ...

Page 268: ... Open tPLZ Closed Open Open Closed tPZL Closed Open Open Closed tPZH Open Closed Closed Open DISABLE INHIBIT D1 D2 D3 D4 D5 D6 Q1 Q2 Q3 Q4 Q5 Q6 CL 16 VDD 8 VSS PULSE GENERATOR 20 ns 20 ns VDD VSS VOH VOL 90 10 50 50 90 10 tPLH tPHL tTHL tTLH OUTPUT TESTS 1 AND 2 For all tTLH tTHL tPHL and tPLH measurements Vin may be applied to any other Dn input or to inhibit 16 VDD PULSE GENERATOR VDD CL 1 k S1...

Page 269: ... ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW...

Page 271: ...Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Turn On Delay Time all Outputs tPHL 0 3 ns pF CL 60 ns tPHL 0 15 ns pF CL 27 ns tPHL 0 1 ns pF CL 20 ns ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tPHL ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 5 0 10 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 75 35 25 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 150 70 50 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 3 State Propagation Delay Time Output 1 to High Impedance Î...

Page 272: ... 10 OUTPUT INPUT tPLH tPHL 90 50 10 Figure 2 3 State AC Test Circuit and Waveforms tPLZ tPHZ tPZH tPZL PULSE GENERATOR DISABLE INPUT 16 VSS 1 k OUTPUT 20 ns 20 ns VDD 50 90 VDD 1 k 8 INPUT tPHZ tPZH CIRCUIT PULSE GENERATOR DISABLE INPUT tPLZ tPZL CIRCUIT OUTPUT VSS 8 16 INPUT CL CL VDD VSS VOH VOL VOL 0 05 V VOH 0 15 V 10 90 10 90 10 tPLZ tPHZ tPZH tPZL OUTPUT FOR tPZH tPZL CIRCUIT OUTPUT FOR tPHZ...

Page 273: ...ds or One Low Power Schottky TTL Load Over the Rated Temperature Range LOGIC DIAGRAM INPUT VDD OUTPUT LEVEL SHIFTER MODE VCC TTL CMOS MODE SELECT Mode Select Input Logic Levels Output Logic Levels 1 VCC TTL CMOS 0 VSS CMOS CMOS 1 6 of package shown MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14504B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION TA 55 to 125 C for all packages P SUFFIX PLASTIC CASE 648...

Page 274: ...ÎÎÎ ÎÎÎ ÎÎÎ 0 8 0 8 1 5 1 5 3 0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0 8 0 8 1 4 1 5 2 9 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vdc ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input Voltage 1 Level VOH 9 0 Vdc TTL CMOS VOH 13 5 Vdc TTL CMOS VOH 9 0 Vdc CMOS CMOS VOH 13 5 Vdc CMOS CMOS VOH 13 5 Vdc CMOS CMOS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIH ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 5 0 5 0 5 0 5 0 10 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 10 ...

Page 276: ...ad Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C LOGIC DIAGRAM AA 1 BA 2 CA 3 DA 4 EA 5 INH 6 DIS 14 EB 13 DB 12 CB 11 BB 10 AB 9 3 STATE OUTPUT DISABLE 15 ZA 7 ZB VDD PIN 16 VSS PIN 8 Z AB CD E I MOTOROLA...

Page 277: ...4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 1 0 2 0 4 0 0 002 0 004 0 006 1 0 2 0 4 0 30 60 120 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50...

Page 278: ...ns tPLH 5 0 10 15 220 100 65 500 225 160 ns tPHL 1 7 ns pF CL 145 ns tPHL 0 66 ns pF CL 62 ns tPHL 0 5 ns pF CL 35 ns tPHL 5 0 10 15 230 95 60 400 175 150 ns 3 State Propagation Delay Time 1 to High Impedance tPHZ 5 0 10 15 60 45 35 150 110 90 ns 0 to High Impedance tPLZ 5 0 10 15 90 55 40 225 140 100 ns High Impedance to 1 tPZH 5 0 10 15 110 50 40 300 125 100 ns High Impedance to 0 tPZL 5 0 10 15...

Page 279: ... INH AA BA CA DA EA AB BB CB DB EB DIS VDD 16 VOL IOL EXTERNAL POWER SUPPLY ZA ZB INH AA BA CA DA EA AB BB CB DB EB DIS VSS 8 Figure 4 3 State Leakage Current Test Circuit Figure 5 Typical Power Dissipation Test Circuit VDD VDD ITL 16 VSS 8 ZA ZB INH AA BA CA DA EA AB BB CB DB EB DIS PULSE GENERATOR 50 DUTY CYCLE 0 01 µF CERAMIC VDD 16 ZA ZB INH AA BA CA DA EA AB BB CB DB EB DIS VSS 8 CL CL IDD 50...

Page 280: ...DD 16 ZA ZB INH AA BA CA DA EA AB BB CB DB EB DIS VSS 8 PULSE GENERATOR B A CL 1 k A B S2 20 ns 20 ns DISABLE INPUT 90 50 10 tPLZ tPZL VOH VOL 10 tPZH tPHZ 90 10 90 OUTPUT 2 5 V VDD 5 V 10 V AND 15 V 2 V VDD 5 V 6 V VDD 10 V 10 V VDD 15 V S1 To test other side of circuit connect to this output and change switch S1 to other expand input E SWITCH POSITIONS TEST S1 S2 tPLZ A A tPHZ B B tPZL A A tPZH ...

Page 281: ...or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic...

Page 282: ...001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 46 µA kHz f IDD IT 2 91 µA kHz f IDD IT 4 37 µA kHz f IDD µAdc Three State Leakage Current ITL 15 0 1 0 0001 0 1 3 0 µAdc Dat...

Page 283: ... 30 25 20 15 0 0 ns Strobe Pulse Width tWH S 5 0 10 15 140 70 40 70 35 20 ns Setup Time Data to Strobe tsu 5 0 10 15 50 20 10 25 10 5 0 ns Hold Time Strobe to Data th 5 0 10 15 50 35 35 20 10 10 ns 3 State Propagation Delay Time Output 1 to High Impedance tPHZ 5 0 10 15 55 35 30 170 100 70 ns Output 0 to High Impedance tPLZ 5 0 10 15 75 40 35 170 100 70 High Impedance to 1 Level tPZH 5 0 10 15 80 ...

Page 284: ...e AC Test Circuit and Waveforms Test ST1 ST2 ST3 ST4 tPHZ Open Close Close Open tPLZ Close Open Open Close tPZL Close Open Open Close tPZH Open Close Close Open PULSE GENERATOR VDD ST3 ST4 VDD VDD ST1 ST2 CL 1 0 k 1 0 k VSS MR ST DISABLE D0 D1 D2 D3 Q0 Q1 Q2 Q3 20 ns 20 ns VDD VSS VOH VOL tPZH tPZL tPLZ tPHZ DISABLE Q3 OUTPUT 50 90 10 90 10 90 10 2 V VDD 5 V 6 V VDD 10 V 10 V VDD 15 V 2 5 V VDD 5 ...

Page 285: ...ITL and the load current IL required to drive the bus line in cluding fanout to other device inputs and can be calculated by the following ITL N 1 IOD IL N must be calculated for both high and low logic states of the bus line SELECTED AS DRIVING DEVICE 1 2 MC14508B DISABLED 1 2 MC14508B DISABLED 1 2 MC14508B IOD IOD ITL ITL ITL ITL IL IL BUS LINES TYPICAL 3 STATE APPLICATIONS EXAMPLE 1 EXAMPLE 2 D...

Page 286: ...IMUM RATINGS Voltages Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond whi...

Page 287: ...6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiesc...

Page 288: ...630 260 200 ns Preset or Reset to Carry Out tPLH tPHL 1 7 ns pF CL 465 ns tPLH tPHL 0 66 ns pF CL 192 ns tPLH tPHL 0 5 ns pF CL 125 ns tPLH tPHL 5 0 10 15 550 225 150 1100 450 300 ns Reset Pulse Width tw H 5 0 10 15 360 210 160 180 105 80 ns Clock Pulse Width tw H 5 0 10 15 350 170 140 200 100 75 ns Clock Pulse Frequency fcl 5 0 10 15 3 0 6 0 8 0 1 5 3 0 4 0 MHz Preset or Reset Removal Time The Pr...

Page 289: ...CK P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT CL CL CL CL CL 20 ns 20 ns VDD VSS 90 50 10 CLOCK VARIABLE WIDTH PROGRAMMABLE PULSE GENERATOR VDD CL CL CL CL CL VSS PE CARRY IN R UP DOWN CLOCK P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT tsu trem 50 50 VDD VSS VDD VSS VDD VSS VOH VOL VSS VDD 1 fcl tw H tw H tTLH tPLH tPHL tPLH tTHL 90 10 CARRY OUT ONLY tw H trem 20 ns 90 10 CARRY IN OR UP DOWN CLOCK PRESET ENABLE Q1 OR...

Page 290: ...ABLE CLOCK CARRY OUT CARRY IN UP DOWN P1 4 Q1 6 P2 12 Q2 11 P3 13 Q3 14 P4 3 Q4 2 P P P P PE D C PE D C PE D C PE D C Q Q Q Q Q Q Q Q STATE DIAGRAM FOR UP COUNTING STATE DIAGRAM FOR DOWN COUNTING 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 ...

Page 291: ...tate This pin is active high and will inhibit the clock when high Up Down Pin 10 Controls the direction of count high for up count low for down count SUPPLY PINS VSS Negative Supply Voltage Pin 8 This pin is usually connected to ground VDD Positive Supply Voltage Pin 16 This pin is con nected to a positive supply voltage ranging from 3 0 Vdc to 18 0 Vdc Figure 3 Presettable Cascaded 8 Bit Up Down ...

Page 292: ...P DOWN CARRY IN MSD PE P8 P7 P6 P5 P4 P3 P2 P1 CARRY OUT MSD Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 CARRY OUT LSD RESET COUNT MSD COUNT LSD 6 6 6 7 7 7 7 7 7 7 6 6 6 6 9 9 9 9 9 0 0 0 0 0 0 0 0 7 8 9 0 1 2 3 2 1 0 9 8 7 6 6 6 7 8 9 0 1 2 1 0 0 1 0 PRESET ENABLE DOWN COUNT UP COUNT DOWN COUNT UP COUNT UP COUNT RESET PRESET ENABLE ...

Page 293: ... a 10011001 to the preset inputs P0 to P7 For this divide operation both counters should be configured in the count down mode The divide ratio of zero is an undefined state and should be avoided Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PE Cin CLOCK U D P1 P2 P3 Cout L S D MC14510B P1 P2 P3 P4 P5 P6 P7 THUMBWHEEL SWITCHES OPEN FOR 0 RESISTORS 10 kΩ CLOCK fin VDD RESET OPEN COUNT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 M S D MC1451...

Page 294: ...ltage VDD 0 5 to 18 V Input Voltage All Inputs Vin 0 5 to VDD 0 5 V DC Current Drain per Input Pin I 10 mA Operating Temperature Range TA 55 to 125 _C Power Dissipation per Package PD 500 mW Storage Temperature Range Tstg 65 to 150 _C Maximum Output Drive Current Source per Output IOHmax 25 mA Maximum Continuous Output Power Source per Output POHmax 50 mW POHmax IOH VDD VOH Maximum Ratings are tho...

Page 295: ...25 mA 10 9 1 9 0 8 6 9 1 9 0 8 6 9 58 9 26 9 17 9 04 8 90 8 70 9 1 8 6 8 2 Vdc IOH 0 mA IOH 5 0 mA IOH 10 mA IOH 15 mA IOH 20 mA IOH 25 mA 15 14 1 14 13 6 14 1 14 13 6 14 59 14 27 14 18 14 07 13 95 13 70 14 1 13 6 13 2 Vdc Output Drive Current VOL 0 4 V Sink VOL 0 5 V VOL 1 5 V IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Inp...

Page 296: ... tPHL 5 0 10 15 485 200 160 970 400 320 Lamp Test Propagation Delay Time tPLH 0 45 ns pF CL 290 5 ns tPLH 0 25 ns pF CL 112 5 ns tPLH 0 20 ns pF CL 80 ns tPLH 5 0 10 15 313 125 90 625 250 180 ns tPHL 1 3 ns pF CL 248 ns tPHL 0 45 ns pF CL 102 5 ns tPHL 0 35 ns pF CL 72 5 ns tPHL 5 0 10 15 313 125 90 625 250 180 Setup Time tsu 5 0 10 15 100 40 30 ns Hold Time th 5 0 10 15 60 40 30 ns Latch Enable P...

Page 297: ... ns VDD VSS VOH VOL 90 50 10 50 A B AND C ANY OUTPUT 50 DUTY CYCLE 1 2f Figure 2 Dynamic Signal Waveforms 20 ns 20 ns VDD 90 INPUT C a Inputs D and LE low and Inputs A B BI and LT high VSS VOH VOL 50 10 OUTPUT g tPLH tPHL 90 10 50 tTLH tTHL b Input D low Inputs A B BI and LT high 20 ns 10 90 50 VDD VSS VDD VSS VOH VOL th tsu 50 INPUT C OUTPUT g LE c Data DCBA strobed into latches 20 ns 20 ns VDD V...

Page 298: ...UID CRYSTAL LCD READOUT VDD VDD VSS VDD VSS FILAMENT SUPPLY DIRECT LOW BRIGHTNESS VSS OR APPROPRIATE VOLTAGE BELOW VSS CAUTION Maximum working voltage 18 0 V VDD APPROPRIATE VOLTAGE VSS VSS VDD EXCITATION SQUARE WAVE VSS TO VDD 1 4 OF MC14070B A filament pre warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament Direct dc drive of L...

Page 299: ...MOTOROLA CMOS LOGIC DATA 6 261 MC14511B LOGIC DIAGRAM LE 5 D 6 C 2 B 1 A 7 VDD PIN 16 VSS PIN 8 BI 4 LT 3 14 g 15 f 9 e 10 d 11 c 12 b 13 a ...

Page 300: ...re 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C TRUTH TABLE C B A Inhibit Disable Z 0 0 0 0 0 X0 0 0 1 0 0 X1 0 1 0 0 0 X2 0 1 1 0 0 X3 1 0 0 0 0 X4 1 0 1 0 0 X5 1 1 0 0 0 X6 1 1 1 0 0 X7 X X X 1 0 0 X X X X 1 High I...

Page 301: ... IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supp...

Page 302: ...tPHZ tPLZ tPZH tPZL 5 0 10 15 60 35 30 150 100 75 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Power Dissipation Test Circuit and Waveform VDD ID CL Z DISABLE INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 VSS PULSE GENERATOR 50 Vin 50 DUTY CYCLE Para...

Page 303: ...X2 X1 X0 B C A 15 10 14 DISABLE INHIBIT VDD Z VSS 1 1 IN OUT IN 2 OUT 2 TRANSMISSION GATE SELECTED DEVICE MC14512B MC14512B MC14512B IOD ITL ITL IL LOAD DATA BUS 3 STATE MODE OF OPERATION Output terminals of several MC14512B 8 Bit Data Selec tors can be connected to a single date bus as shown One MC14512B is selected by the 3 state control and the re maining devices are disabled into a high impeda...

Page 304: ...l Value Unit DC Supply Voltage VDD 0 5 to 18 V Input Voltage All Inputs Vin 0 5 to VDD 0 5 V DC Current Drain per Input Pin I 10 mA Operating Temperature Range TA 55 to 125 C Power Dissipation per Package PD 500 mW Storage Temperature Range Tstg 65 to 150 _C Maximum Continuous Output Drive Current Source per Output IOHmax 25 mA Maximum Continuous Output Power Source per Output POHmax 50 mW POHmax ...

Page 305: ...7 0 11 Vdc Output Drive Voltage Segments IOH 0 mA Source IOH 5 0 mA IOH 10 mA IOH 15 mA IOH 20 mA IOH 25 mA VOH 5 0 4 1 3 9 3 4 4 1 3 9 3 4 4 57 4 24 4 12 3 94 3 70 3 54 4 1 3 5 3 0 Vdc IOH 0 mA IOH 5 0 mA IOH 10 mA IOH 15 mA IOH 20 mA IOH 25 mA 10 9 1 9 0 8 6 9 1 9 0 8 6 9 58 9 26 9 17 9 04 8 90 8 75 9 1 8 6 8 2 Vdc IOH 0 mA IOH 5 0 mA IOH 10 mA IOH 15 mA IOH 20 mA IOH 25 mA 15 14 1 14 13 6 14 1 ...

Page 306: ...Per Package Vin 0 or VDD Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 9 µA kHz f IDD IT 3 8 µA kHz f IDD IT 5 7 µA kHz f IDD µAdc Noise immunity specified for worst case input combination Noise Margin for both 1 and 0 level 1 0 Vdc min VDD 5 0 Vd...

Page 307: ...H 0 20 ns pF CL 165 ns tPLH 5 0 10 15 640 250 175 1280 500 350 ns tPHL 1 3 ns pF CL 655 ns tPHL 0 60 ns pF CL 260 ns tPHL 0 35 ns pF CL 182 5 ns tPHL 5 0 10 15 720 290 200 1440 580 400 ns Propagation Delay Time RBI and BI Inputs tPLH 1 05 ns pF CL 547 5 ns tPLH 0 45 ns pF CL 177 5 ns tPLH 0 30 ns pF CL 135 ns tPLH 5 0 10 15 600 200 150 750 300 220 ns tPHL 0 85 ns pF CL 442 5 ns tPHL 0 45 ns pF CL ...

Page 308: ...BI and LT high c Setup and Hold Times Input RBI and D low Inputs A B BI and LT high d Pulse Width Data DCBA strobed into latches 20 ns tPLH tTLH INPUT C OUTPUT g 20 ns VDD VSS VOH VOL tTHL tPHL 90 50 10 20 ns INPUT C tPLH OUTPUT RBO tTLH 20 ns VDD VSS VOH VOL 90 50 10 tPHL tTHL 50 90 10 20 ns LE INPUT C OUTPUT g 50 10 90 50 VDD VSS VDD VSS VOH VOL 20 ns VDD VSS 20 ns 90 50 10 LE tWL LE th tsu ...

Page 309: ...ED VSS 1 7 V VDD COMMON ANODE LED 1 7 V VSS VDD VDD VSS VDD DIRECT LOW BRIGHTNESS FILAMENT SUPPLY VSS VSS OR APPROPRIATE VOLTAGE BELOW VSS VDD VSS APPROPRIATE VOLTAGE VDD VSS EXCITATION SQUARE WAVE VSS TO VDD 1 4 OF MC14070B A filament pre warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament Direct dc drive of LC s not recommended...

Page 310: ...PPLICATIONS FOR RIPPLE BLANKING LEADING EDGE ZERO SUPPRESSION CONNECT TO VDD 1 DISPLAYS RBI RBO a g MC14513B INPUT CODE 0 0 0 0 0 D C B A 1 1 0 0 0 RBI RBI RBI RBI RBI D C B A D C B A D C B A D C B A D C B A MC14513B MC14513B MC14513B MC14513B MC14513B 0 0 0 0 0 0 1 0 1 5 0 0 0 0 0 0 0 0 1 1 0 0 1 1 3 a g a g a g a g a g 0 RBO RBO RBO RBO RBO ...

Page 311: ... ZERO SUPPRESSION DISPLAYS RBI a g MC14513B 0 1 0 1 5 D C B A 0 0 0 1 1 RBO D C B A D C B A D C B A D C B A D C B A MC14513B MC14513B MC14513B MC14513B MC14513B 0 0 0 0 0 0 0 0 1 1 0 0 1 1 3 0 0 0 0 0 0 0 0 0 0 a g a g a g a g a g RBI RBI RBI RBI RBI RBO RBO RBO RBO RBO 0 CONNECT TO VDD 1 INPUT CODE ...

Page 312: ...tput Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Pa...

Page 313: ...mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching ITL 5 0 10 15 IT 1 35 µA kHz f IDD IT 2 70 µA kHz f IDD IT 4 05 µA kHz f IDD µAdc Data labelled Typ is not to...

Page 314: ... CL 315 ns tPLH tPHL 0 66 ns pF CL 117 ns tPLH tPHL 0 5 ns pF CL 75 ns tPLH tPHL 5 0 10 15 400 150 100 800 300 200 ns Setup Time Data to Strobe tsu 5 0 10 15 250 100 75 125 50 38 ns Hold Time Strobe to Data th 5 0 10 15 20 0 10 100 40 30 ns Strobe Pulse Width tWH 5 0 10 15 350 100 75 175 50 38 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be use...

Page 315: ... D2 D3 D4 INHIBIT Figure 3 Switching Time Test Circuit and Waveforms PROGRAMMABLE PULSE GENERATOR VDD STROBE INHIBIT D1 D2 D3 D4 CL VDD VSS VDD VSS S0 S1 S15 VSS CL CL INPUT OUTPUT tTLH tTLH tTHL tTHL tPHL tPLH 20 ns OUTPUT S0 OUTPUT S1 OUTPUT S15 90 50 10 90 50 10 S5 S7 D2 D1 ST S3 S4 S6 S10 D3 D4 INH VDD S15 S14 S9 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 S13 S12 S8 S11 S0 ...

Page 316: ... STROBE 1 INHIBIT 23 Q Q R S Q Q R S Q Q R S Q Q R S A B C D IN MC14515B ONLY A B C D 11 S0 9 S1 10 S2 8 S3 7 S4 6 S5 5 S6 4 S7 18 S8 17 S9 20 S10 19 S11 14 S12 13 S13 16 S14 15 S15 A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D ...

Page 317: ...y of the input registers the most significant bit MSB from each register could be se lected for transfer to the data bus Therefore all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers Information from the 3 state bus is redistributed by the MC14514B four bit latch decoder ...

Page 318: ...eter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derati...

Page 319: ...6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiesc...

Page 320: ...60 200 ns Preset or Reset to Carry Out tPLH tPHL 1 7 ns pF CL 465 ns tPLH tPHL 0 66 ns pF CL 192 ns tPLH tPHL 0 5 ns pF CL 125 ns tPLH tPHL 5 0 10 15 550 225 150 1100 450 300 ns Reset Pulse Width tw 5 0 10 15 380 200 160 190 100 80 ns Clock Pulse Width tWH 5 0 10 15 350 170 140 200 100 75 ns Clock Pulse Frequency fcl 5 0 10 15 3 0 6 0 8 0 1 5 3 0 4 0 MHz Preset or Reset Removal Time The Preset or ...

Page 321: ... pF Q0 Q1 Q2 Q3 CARRY OUT PE CARRY IN R UP DOWN CLOCK P0 P1 P2 P3 CL LOGIC DIAGRAM PE C T Q Q P PE C T Q Q P PE C T Q Q P PE C T Q Q P Q2 14 P2 13 Q1 11 P3 3 Q3 2 P0 4 Q0 6 P1 12 CARRY OUT CLOCK PRESET ENABLE RESET CARRY IN UP DOWN 9 1 15 7 5 10 TOGGLE FLIP FLOP PE C T Q Q P PARALLEL IN FLIP FLOP FUNCTIONAL TRUTH TABLE Preset Enable Clock T Qn 1 1 X X Parallel In 0 0 Qn 0 1 Qn 0 X Qn X Don t Care ...

Page 322: ...this input OUTPUTS Q0 Q1 Q2 Q3 Binary outputs Pins 6 11 14 2 Binary data is present on these outputs with Q0 correspond ing to the least significant bit Carry Out Pin 7 Used when cascading stages Carry Out is usually connected to Carry In of the next stage This synchronous output is active low and may also be used to indicate terminal count CONTROLS PE Preset Enable Pin 1 Asynchronously loads data...

Page 323: ...ut goes low for one complete clock cycle thus allowing the next counter to decrement increment one count See Timing Diagram The L S D now counts through another cycle 15 clock pulses and the above cycle is repeated L S D MC14516B Cout Q0 Q1 Q2 Q3 P0 P1 P2 P3 PE R U D CLOCK Cin M S D MC14516B Cout Q0 Q1 Q2 Q3 P0 P1 P2 P3 PE R U D CLOCK Cin Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TERMINAL COUNT INDICATOR P0 P1 P2 P...

Page 324: ...P DOWN COUNTER CLOCK UP DOWN CARRY IN MSD PE P7 P6 P5 P4 P3 P2 P1 P0 CARRY OUT MSD Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CARRY OUT LSD RESET COUNT PRESET ENABLE UP COUNT DOWN COUNT UP COUNT DOWN COUNT PRESET ENABLE RESET 13 14 15 16 17 18 18 17 16 15 14 13 19 251 252 253 254 255 0 1 2 2 1 3 0 1 2 UP COUNT ...

Page 325: ...g a 1111 1111 to the preset inputs P0 to P7 For this divide operation both counters should be configured in the count down mode The divide ratio of zero is an undefined state and should be avoided BUFFER fout M S D MC14516B L S D MC14516B THUMBWHEEL SWITCHES OPEN FOR 0 VDD VDD Cout VDD OPEN COUNT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 P0 P1 P2 P3 P0 P1 P2 P3 PE R U D CLOCK Cin Cout Q0 Q1 Q2 Q3 P0 P1 ...

Page 327: ...0001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 4 2 µA kHz f IDD IT 8 8 µA kHz f IDD IT 13 7 µA kHz f IDD µAdc Three State Leakage Current ITL 15 0 1 0 0001 0 1 3 0 µAdc Data...

Page 328: ...Note Data to Clock Setup Time tsu 5 0 10 15 0 10 15 40 15 0 ns Data to Clock Hold Time th 5 0 10 15 150 75 35 75 25 10 ns Write Enable to Clock Setup Time tsu 5 0 10 15 400 200 110 170 65 50 ns Write Enable to Clock Release Time trel 5 0 10 15 380 180 100 160 55 40 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is ...

Page 329: ...16 17 18 19 33 90 10 tsu 16 BIT OUTPUT 1 15 17 BIT INPUT 32 BIT OUTPUT 6 10 33 BIT INPUT 48 BIT OUTPUT 2 14 49 BIT INPUT 64 BIT OUTPUT 5 11 th1 th1 th1 th1 tWH tWL tTHL tTHL tTHL tTHL VOL VOL VOL VOH VOH VOH 50 90 10 20 ns trel tPHL tPHL tPHL tPHL tPLH 90 10 tTLH tTLH tTLH tTLH th0 th0 th0 th0 tsu0 tsu0 tsu0 50 20 ns 20 ns 20 ns VDD VDD VDD tsu0 tsu1 tsu1 tsu1 tsu1 DATA IN 7 9 WRITE 3 13 CLOCK 4 1...

Page 330: ...DD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and ...

Page 331: ... 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plu...

Page 332: ...s pF CL 117 ns tPHL 0 66 ns pF CL 95 ns tPHL 5 0 10 15 330 130 90 650 230 170 ns Clock Pulse Width tw H tw L 5 0 10 15 200 100 70 100 50 35 ns Clock Pulse Frequency fcl 5 0 10 15 2 5 6 0 8 0 1 5 3 0 4 0 MHz Clock or Enable Rise and Fall Time tTHL tTLH 5 0 10 15 15 5 4 µs Enable Pulse Width tWH E 5 0 10 15 440 200 140 220 100 70 ns Reset Pulse Width tWH R 5 0 10 15 280 120 90 125 55 40 ns Reset Rem...

Page 333: ...CL CL VDD VSS Q3 Q2 Q1 Q0 C E R 20 ns Q tr tf VDD VSS 20 ns CLOCK INPUT 90 50 10 tWL tWH 90 50 10 tPLH tPHL Figure 3 Timing Diagram 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4 3 0 9 8 7 6 5 4 3 2 1 CLOCK ENABLE RESET Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 MC14518B MC14520B ...

Page 334: ...ade Counter MC14518B Logic Diagram 1 2 of Device Shown D C R Q Q D C R Q Q D C R Q Q D C R Q Q Q0 Q1 Q2 Q3 RESET ENABLE CLOCK Figure 5 Binary Counter MC14520B Logic Diagram 1 2 of Device Shown D C R Q Q D C R Q Q D C R Q Q D C R Q Q Q0 Q1 Q2 Q3 RESET ENABLE CLOCK ...

Page 335: ...tection on All Inputs Supply Voltage Range 3 0 Vdc to 18 Vdc Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range Plug in Replacement for CD4019 in Most Applications LOGIC DIAGRAM CONTROL INPUTS DATA INPUTS A B X0 Y0 X1 Y1 X2 Y2 X3 Y3 9 14 6 7 4 5 2 3 15 1 10 Z0 11 Z1 12 Z2 13 Z3 VDD PIN 16 VSS PIN 8 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC...

Page 336: ...1 5 Vdc VIL 5 0 10 15 1 5 3 0 4 0 2 25 4 50 6 75 1 5 3 0 4 0 1 5 3 0 4 0 Vdc 1 Level VO 0 5 or 4 5 Vdc VO 1 0 or 9 0 Vdc VO 1 5 or 13 5 Vdc VIH 5 0 10 15 3 5 7 0 11 3 5 7 0 11 2 75 5 50 8 25 3 5 7 0 11 Vdc Output Drive Current VOH 2 5 Vdc Source VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 ...

Page 337: ...HL 5 0 10 15 250 115 90 500 225 165 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Dynamic Power Dissipation Test Circuit and Waveform VDD Z0 Z1 Z2 Z3 A B X0 Y0 X1 Y1 X2 Y2 X3 Y3 CL CL CL CL VDD VSS ISS Vin 500 µF PULSE GENERATOR 20 ns 20 ns VD...

Page 338: ...l ones 1 0 0 X0 X1 X2 X3 Control A 1 0 1 X0 X1 X2 X3 Control A and Invert 0 1 0 Y0 Y1 Y2 Y3 Control B 0 1 1 Y0 Y1 Y2 Y3 Control B and Invert 1 1 0 X0 ĥY0 X1 ĥY1 X2 ĥY2 X3 ĥY3 Exclusive NOR 1 1 1 X0 ęY0 X1 ęY1 X2 ęY2 X3 ęY3 Exclusive OR This device contains protection circuitry to guard against damage due to high static voltages or electric fields However precautions must be taken to avoid applicat...

Page 339: ...age ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to 18 0 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin Vout ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage DC or Transient ÎÎÎÎÎÎ ÎÎÎÎÎÎ 0 5 to VDD 0 5 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Iin IoutÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Input or Output Current DC or Transient per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ 10 ÎÎÎ ÎÎÎ mA ÎÎÎÎ ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation per Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ 500 ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎ...

Page 340: ...0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 42 µ...

Page 341: ... 1 7 12 4 5 3 5 Propagation Delay Time Reset to Qn tPHL 1 7 ns pF CL 1215 ns tPHL 0 66 ns pF CL 467 ns tPHL 0 5 ns pF CL 350 ns tPHL 5 0 10 15 1300 500 375 2600 1000 750 ns Clock Pulse Width tWH cl 5 0 10 15 385 150 120 140 55 40 ns Clock Pulse Frequency fcl 5 0 10 15 3 5 9 0 12 2 0 5 0 6 5 MHz Clock Rise and Fall Time tTLH tTHL 5 0 10 15 15 5 0 4 0 µs Reset Pulse Width tWH R 5 0 10 15 1400 600 45...

Page 342: ...ty Frequency Change as a Function of VDD TA 25_C VDD Change from 5 0 V to 10 V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature VDD 10 V TA Change from 55_C to 25_C MC14521 only Complete Oscillator TA Change from 25_C to 125_C MC14521 only Complete Oscillator 6 0 2 0 4 0 100 2 0 160 2 0 2 0 2 0 120 2 0 560 ppm ppm ppm ppm ppm ppm Complete oscillator includes crystal capac...

Page 343: ...ÎÎÎÎÎÎÎ FUNCTIONAL TEST SEQUENCE Inputs Outputs Comments Reset In 2 Out 2 VSS VDD Q18 thru Q24 Counter is in three 8 stage sections in parallel mode Counter is reset In 2 and 1 0 0 VDD Gnd 0 Counter is reset In 2 and Out 2 are connected together A test function see Figure 8 has been included for the reduction of test time required to 0 1 1 First 0 to 1 transition on In 2 Out 2 node included for th...

Page 344: ...ATA MC14521B 6 306 LOGIC DIAGRAM VDD 5 RESET 2 9 IN 1 6 IN 2 7 OUT 1 3 VSS 4 OUT 2 STAGES 3 THRU 7 STAGES 11 THRU 15 1 2 8 9 10 16 17 18 19 20 21 22 23 24 10 Q18 11 Q19 12 Q20 13 Q21 14 Q22 15 Q23 1 Q24 VDD PIN 16 VSS PIN 8 ...

Page 345: ... 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C FUNCTION TABLE Inputs Output Clock Reset Inhibit Preset Enable Cascade Feedback 0 Resulting Function X H X L L L Asynchronous reset X X H H X X...

Page 346: ...4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 1...

Page 347: ... 7 5 0 10 15 260 120 100 520 240 200 ns Propagation Delay Time Reset to Q tPHL Figure 8 5 0 10 15 250 110 80 500 220 160 ns Propagation Delay Time Preset Enable to 0 tPHL tPLH Figures 4 9 5 0 10 15 220 100 80 440 200 160 ns Clock or Inhibit Pulse Width tw Figures 5 6 5 0 10 15 250 100 80 125 50 40 ns Clock Pulse Frequency with PE low fmax Figures 4 5 6 5 0 10 15 2 0 5 0 6 6 1 5 3 0 4 0 MHz Clock o...

Page 348: ...0 VSS VDD VGS VOH IOH EXTERNAL POWER SUPPLY CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 0 VSS VDD VGS VOL IOL EXTERNAL POWER SUPPLY Figure 3 Power Dissipation Figure 4 Test Circuit CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 0 VSS VDD CL CL CL CL CL PULSE GENERATOR 20 ns 20 ns CLOCK 90 10 50 VARIABLE WIDTH 50 DUTY CYCLE VSS VDD DEVICE UNDER TEST TEST POINT Q or 0 CL Includes all probe ...

Page 349: ... tr tf tf tr tr tf VDD CLOCK ANY P ANY Q ANY Q CLOCK RESET tPLH tPHL tPLH tPHL tPHL tPLH PRESET ENABLE PRESET ENABLE ANY P GND tw tw tw tw ANY Q OR 0 ANY Q OR 0 tTLH tTHL 1 fmax 1 fmax 90 50 10 90 50 10 90 50 10 90 50 10 90 50 10 50 0 50 90 50 10 tTLH tTHL INHIBIT tPLH tPHL tPHL 50 50 50 tsu th 50 50 VALID Figure 7 Figure 8 Figure 9 Figure 10 trem ...

Page 350: ...nter reaches terminal count Q0 Q1 Q2 Q3 low if Cascade Feedback is high and Preset Enable is low When presetting the counter to a value other than all zeroes the 0 output is valid after the rising edge of Preset Enable when Cascade Feedback is high See the Function Table Cascade Feedback Pin 13 If the Cascade Feedback input is high a high level is generated at the 0 output when the count is all ze...

Page 351: ...ET 13 3 4 6 10 P0 Q0 P1 Q1 P2 Q2 P3 Q3 5 7 11 9 14 15 2 1 D C T R Q PEQ D C T R Q PEQ D C T R Q PEQ D C T R PE Q VSS 12 0 MC14526B LOGIC DIAGRAM Binary Down Counter CF PE INHIBIT CLOCK RESET 13 3 4 6 10 P0 Q0 P1 Q1 P2 Q2 P3 Q3 5 7 11 9 14 15 2 1 12 0 D C T R Q PEQ D C T R Q PEQ D C T R Q PEQ D C T R PE Q VDD VDD ...

Page 352: ...crementing is inhibited Cascaded Presettable Divide By N Figure 12 shows a three stage cascade application Taking Reset high loads N Only the first stage s Reset pin least sig nificant counter must be taken high to cause the preset for all stages but all pins could be tied together as shown When the first stage s Reset pin goes high the 0 output is latched in a high state Reset must be released wh...

Page 353: ...ÎÎÎ ÎÎÎ mW ÎÎÎÎ ÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C...

Page 354: ...itance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 85 µA kHz f IDD IT 1 75 µA kHz f IDD IT 2 60 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes but is intended as an indication o...

Page 355: ...CL 315 ns tPLH tPHL 0 66 ns pF CL 122 ns tPLH tPHL 0 5 ns pF CL 85 ns tPLH tPHL 5 0 10 15 400 155 110 800 310 220 ns Set or Clear to Out tPHL 1 7 ns pF CL 295 ns tPHL 0 66 ns pF CL 132 ns tPHL 0 5 ns pF CL 85 ns tPHL 5 0 10 15 380 165 110 760 330 220 ns Cascade to Out tPHL 1 7 ns pF CL 40 ns tPHL 0 66 ns pF CL 32 ns tPHL 0 5 ns pF CL 20 ns tPLH 5 0 10 15 125 65 45 250 130 90 ns Strobe to Out tPHL ...

Page 356: ...PUT PIN 6 PRESET NO OF 1 PRESET NO OF 2 PRESET NO OF 3 PRESET NO OF 4 PRESET NO OF 5 PRESET NO OF 6 PRESET NO OF 7 PRESET NO OF 8 PRESET NO OF 9 20 ns 20 ns tTLH tTHL CLOCK SET 90 10 50 50 50 50 90 10 tTLH tTHL SET OUT ENABLE IN trem tsu tWH tPHL tPHL tPLH 1 fcl VDD VSS MULTIPLIER PRESET NO S CLEAR CASC Ein CLOCK ST A B C D Eout OUT OUT 9 PULSE GENERATOR PROGRAMMABLE PULSE GENERATOR VDD VSS CL CL ...

Page 357: ...LE WIDTH 90 50 10 PULSE GENERATOR VDD ID VDD VSS CL CL CL CL 500 pF 0 01 µF CERAMIC CASC Ein CLOCK ST A B C D Eout OUT OUT 9 S CLEAR LOGIC DIAGRAM T C R Q Q T C R Q Q T C R Q Q T C R Q S S a b c d D C B A 3 2 15 14 ENABLE IN 11 9 CLOCK CLEAR 13 SET TO NINE 4 R1 R4 R2 R3 6 OUT 5 OUT 1 9 7 ENABLE OUT 10 12 STROBE CASCADE VDD PIN 16 VSS PIN 8 ...

Page 358: ... CASC Ein CLOCK ST A B C D Eout OUT 9 CLEAR S CLOCK 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 1 1 1 0 0 0 0 0 OUT DRM One of four output pulses contributed by DRM to outputfor every 100 clock pulses in for preset No of 94 NOTE More than two MC14527Bs may be cascaded using this configuration MOST SIGNIFICANT DIGIT LEAST SIGNIFICANT DIGIT 2 2 2 1 ...

Page 360: ...Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current at an external load Capacitance CL and at external timing capacitance CX use the formula IT IT CL CX CL 0 36CX VDDf 2x10 8 RXCX VDD 2 2f x 10 3 where IT in µA per circuit CL and CX in pF RX in megohms VDD in V...

Page 361: ...te VDD level tW 15 5 0 5 0 10 15 550 350 300 ns Output Pulse Width Q or Q For CX 0 01 µF use formula tW 0 2 RX CX Ln VDD VSS tW 10 000 10 5 0 10 15 15 10 15 30 50 55 45 90 95 µs Pulse Width Match between Circuits in the same package t1 t2 10 000 10 5 0 10 15 6 0 8 0 8 0 25 35 35 Reset Propagation Delay Reset to Q or Q tPLH tPHL 15 5 0 5 0 10 15 325 90 60 600 225 170 ns 1000 10 5 0 10 15 1000 300 2...

Page 362: ...V Vin 90 10 0 1 mF CERAMIC RX CX RX CX A B RESET A B RESET Q Q Q Q ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ INPUT CONNECTIONS Characteristics Reset A B tPLH tPHL tTLH tTHL tW VDD PG1 VDD tPLH tPHL tTLH tTHL tW VDD VSS PG2 tPLH R tPHL R tW PG3 PG1 PG2 Figure 4 AC Test Circuit PULSE GENERATOR PULSE GENERATOR PULSE GENERATOR VDD RX CX RX CX VSS A B RESET A B RESET Q Q Q Q CL CL CL CL PG1 PG2 PG3 CX 15 pF CL 15 ...

Page 363: ... tTLH tTHL 90 10 tTLH tTHL tTHL tTLH 50 90 10 50 50 tWL tPLH 50 50 50 90 10 A B Q Q RESET tWH tTLH tTHL tPHL tPHL tPHL tWL tPHL tW Figure 6 Pulse Width versus CX 100 000 10 000 1000 100 10 CX EXTERNAL CAPACITANCE pF PULSE WIDTH s t W m 1000 100 10 1 0 0 1 VDD 15 V 10 V 5 0 V 15 V 10 V 5 0 V 15 V 10 V 5 0 V RX 5 0 kW 15 V 10 V 5 0 V RX 100 kW RX 10 kW ...

Page 364: ...Cx VDD Q Q RESET FALLING EDGE TRIGGER RISING EDGE TRIGGER VDD Rx Cx VDD Q Q RESET A B A B VDD VDD Rx Cx VDD Q Q RESET FALLING EDGE TRIGGER RISING EDGE TRIGGER VDD Rx Cx VDD Q Q RESET A B A B Figure 9 Use of a Diode to Limit Power Down Current Surge Figure 10 Connection of Unused Sections VDD VDD VDD DX Rx Cx VDD Q Q RESET RESET VDD VDD NC NC NC A B 1 15 2 14 Q Q ...

Page 365: ...ÎÎ Storage Temperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C TRUTH TABLE X Don t Care STX STY B A ...

Page 366: ...ance Cin 5 0 7 5 pF SWITCHES IN OUT AND COMMONS OUT IN W Z Voltages Referenced to VEE Recommended Peak to Peak Voltage Into or Out of the Switch VI O Channel On or Off 0 VDD 0 VDD 0 VDD Vp p Recommended Static or Dynamic Voltage Across the Switch Figure 5 Vswitch Channel On 0 600 0 600 0 300 mV Output Offset Voltage VOO Vin 0 V No Load 10 µV ON Resistance Ron 10 15 Vswitch v500 mV Vin VIL or VIH C...

Page 367: ...2 15 nV cycle Sine Wave Distortion Vin 1 77 Vdc RMS Centered 0 0 Vdc RL 10 kΩ f 1 0 kHz 5 0 5 0 0 36 Off Channel Leakage Current Vin 5 0 Vdc Vout 5 0 Vdc Vin 5 0 Vdc Vout 5 0 Vdc Vin 7 5 Vdc Vout 7 5 Vdc Vin 7 5 Vdc Vout 7 5 Vdc Ioff 5 0 5 0 7 5 7 5 5 0 5 0 7 5 7 5 0 001 0 001 0 0015 0 0015 125 125 250 250 nA Insertion Loss Vin 1 77 Vdc RMS centered 0 0 Vdc f 1 0 MHz Iloss 20 Log10 Vout Vin RL 1 0...

Page 368: ...V VDD Vin VSS 0 0 V VSS OUT VN 1 k VDD VSS IS Z W STX STY A B X3 Y3 Figure 3 Quiescent Power Dissipation Test Circuit Figure 4 RON Characteristics Test Circuit PULSE GENERATOR VDD OUT 10 k VSS Vin ID VDD fc A0 A1 PD VDD x ID VDD OUT VSS Vin RL STX STY VDD TYPICAL RON versus INPUT VOLTAGE Figure 5 Figure 6 Vin INPUT VOLTAGE Vdc Vin INPUT VOLTAGE Vdc 10 5 0 5 10 0 5 10 15 20 25 VDD 15 V VSS 0 V VDD ...

Page 369: ... 90 10 50 VX 90 Vin Vx Vin Vx tPHZ tPZH STX STY STX STY Figure 9 Crosstalk Test Circuit Figure 10 Frequency Response Test Circuit A OR B CONTROL LOGIC 10 k 50 pF OUT Vin 1 k RL VDD OUT X Y INPUT VSS VDD VSS VFeedthrough RL X Y INPUT 2 5 Vdc 2 5 Vdc 0 0 Vdc Vin Figure 11 Noise Voltage Test Circuit Figure 12 Typical Noise Characteristics QUAN TECH MODEL 2283 OR EQUIV VDD VSS OUT IN 35 30 25 20 15 10...

Page 370: ...8 7 6 Y2 Y1 Y0 STY VDD Z W Y3 X2 X1 X0 STX VSS B A X3 10 k 100 k 1 0 M 10 M 100 M 2 0 0 2 0 4 0 6 0 8 0 10 12 fin INPUT FREQUENCY Hz TYPICAL INSERTION LOSS dB RL 1 MW AND 100 kW 1 0 kW 10 kW 3 0 dB RL 1 0 MW 3 0 dB RL 10 kW 3 0 dB RL 1 0 kW LOGIC DIAGRAM VDD PIN 16 VSS PIN 8 11 12 5 4 3 2 13 14 10 W 9 Z Y3 Y2 Y1 Y0 X3 X2 X1 X0 15 1 6 7 STY STX A B ...

Page 371: ...mperature ÎÎÎÎÎÎ ÎÎÎÎÎÎ 65 to 150 ÎÎÎ ÎÎÎ _C ÎÎÎÎ ÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature 8 Second Soldering ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 ÎÎÎ ÎÎÎ _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C LOGIC TABLE INPUTS A B C D E W Z For all combinati...

Page 372: ... 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 0 25 0 5 1 0 0 0005 0 0010 0 0015 0 25 0 5 1 0 7 5 15 30 µAdc Total Supply Current Dynami...

Page 373: ...L 5 0 10 15 430 195 120 1200 540 410 ns A B C D E Pulse Generator W VDD tPLH 1 7 ns pF CL 170 ns tPLH 0 66 ns pF CL 87 ns tPLH 0 5 ns pF CL 60 ns tPLH 5 0 10 15 255 120 86 640 300 210 ns tPHL 1 7 ns pF CL 195 ns tPHL 0 66 ns pF CL 92 ns tPHL 0 5 ns pF CL 75 ns tPHL 5 0 10 15 280 125 100 750 330 250 ns A B C D E Gnd W Pulse Generator tPHL tPLH 1 7 ns pF CL 145 ns tPHL tPLH 0 66 ns pF CL 72 ns tPHL ...

Page 374: ...ay of the gate and the feedback element tx y z Qn 1 0 0 0 0 0 0 1 Qn 0 1 0 Qn 0 1 1 Qn 1 0 0 Qn 1 0 1 Qn 1 1 0 Qn 1 1 1 1 The flip flop changes state only when all 1 s or all 0 s are entered This configuration may be extended by cascading M5 gates to cover n inputs where all inputs must be 1 s or 0 s before the output will change As an example this configura tion is useful for controlling an n sta...

Page 375: ...ge labeled M5 is a single majority logic gate using five inputs A thru E and one output Z A W 0 B C D E M5 Z A W 1 B C D E M5 Z A W 0 B C M3 Z 1 0 A W 1 B C M3 Z 1 0 A W 1 B C OR3 Z 1 1 A W 0 B C NOR3 Z 1 1 A W 1 B C AND3 Z 0 0 A W 0 B C NAND3 Z 0 0 5 INPUT MAJORITY GATES 3 INPUT MAJORITY GATES 3 INPUT OR GATE 3 INPUT AND GATE 3 INPUT NAND GATE 3 INPUT NOR GATE A B C D E M5 A B C D E M5 A B C D E ...

Page 377: ... Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 25 µA kHz f IDD IT 0 50 µA kHz f IDD IT 0 75 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes but is intended as an indica...

Page 378: ...H tPHL 0 5 ns pF CL 95 ns Odd Even to Q tPLH tPHL 1 7 ns pF CL 165 ns tPLH tPHL 0 66 ns pF CL 67 ns tPLH tPHL 0 5 ns pF CL 45 ns tPLH tPHL 5 0 10 15 5 0 10 15 440 175 120 250 100 70 1320 525 360 750 300 210 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance...

Page 379: ...y occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C TRUTH TABLE Input Output Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout 0 X X X X X X X X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X X X X X 1 1 1 1 0 1 0 1 X X X X X X 1 1 1 0 0 1 0 0 1 X X X X X 1 1 0 1 0 1 0 0 0 1 X X X X 1 1 0 0 0 1 0 0 0 0 1 X X X 1 0 1 1 0 ...

Page 380: ...Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20...

Page 381: ...0 200 ns Propagation Delay Time Dn to Qn tPLH tPHL 1 7 ns pF CL 265 ns tPLH tPHL 0 66 ns pF CL 137 ns tPLH tPHL 0 5 ns pF CL 85 ns tPLH tPHL 5 0 10 15 300 170 110 600 340 220 ns Propagation Delay Time Dn to GS tPLH tPHL 1 7 ns pF CL 195 ns tPLH tPHL 0 66 ns pF CL 107 ns tPLH tPHL 0 5 ns pF CL 75 ns tPLH tPHL 5 0 10 15 280 140 100 560 280 200 ns The formulas given are for the typical characteristic...

Page 382: ... VSS CL CL CL CL CL NOTE Input rise and fall times are 20 ns 50 50 50 50 50 50 50 50 90 50 10 90 50 10 90 50 10 90 50 10 tPHL tPHL tPHL tPHL tPHL tTHL tTHL tTHL tTHL tPLH tPLH tPLH tPLH tPLH tPLH tPLH tTLH tTLH tTLH tTLH tTLH tPHL tPLH tTHL 90 50 10 tPLH tPHL tPHL tPHL D0 D1 D2 D3 D4 D5 D6 D7 Ein Eout GS Q0 Q1 Q2 10 11 12 13 1 2 3 4 5 15 14 9 7 6 PIN NO 50 ...

Page 383: ...sitive Logic LOGIC EQUATIONS Eout Ein D0 D1 D2 D3 D4 D5 D6 D7 10 11 12 13 1 2 3 4 5 D0 D1 D2 D3 D4 D5 D6 D7 Ein 9 7 6 14 15 Q0 Q1 Q2 GS Eout Q0 Ein D1 D2 D4 D6 D3 D4 D6 D5 D6 D7 Q1 Ein D2 D4 D5 D3 D4 D5 D6 D7 Q2 Ein D4 D5 D6 D7 GS Ein D0 D1 D2 D3 D4 05 D6 D7 ...

Page 384: ...switching frequencies RC should be about 1 0 ms if R 33 k ohms C 0 03 µF The analog 3 0 dB bandwidth would then be dc to 1 0 kHz ANALOG TO DIGITAL CONVERSION An analog signal is applied to the analog input of the MC1710 A digital eight bit word known to represent a digi tized level less than the analog input is applied to the MC14512 as in the D to A conversion The word is increm ented at rates su...

Page 385: ...Clock Conditioning Circuits for Slow Transition Inputs Counter Sequences on Positive Transition of Clock A Supply Voltage Range 3 0 Vdc to 18 Vdc Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range BLOCK DIAGRAM PULSE ERROR DETECTOR PULSE SHAPER TEST CONTROL OUTPUT CONTROL MUX MUX MUX MUX MUX UNITS CARRY CONTROL TENS HUNDREDS THOUSANDS TEN...

Page 386: ...0 2 0 3 0 Vdc 1 Level VO 0 5 or 4 5 Vdc VO 1 0 or 9 0 Vdc VO 1 5 or 13 5 Vdc VIH 5 0 10 15 4 0 8 0 12 4 0 8 0 12 3 5 7 0 11 4 0 8 0 12 Vdc Output Drive Current VOH 2 5 Vdc Source VOH 4 6 Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8...

Page 387: ...Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 5 µA kHz f IDD Scan Oscillator IT 1 0 µA kHz f IDD Frequency 1 0 kHz IT 1 5 µA kHz f IDD µAdc Three State Leakage Current ITL 15 0 1 0 0001 0 1 3 0 µAdc Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance The formulas given are for the typical character...

Page 388: ...tPHL 1 8 ns pF CL 1 8 µs tPLH tPHL 0 8 ns pF CL 0 6 µs tPLH tPHL 0 6 ns pF CL 0 5 µs tPLH tPHL 5 0 10 15 1 8 0 6 0 5 3 6 1 2 0 9 µs Scanner Clock to Digit Select tPHL tPLH 1 8 ns pF CL 1 5 µs tPHL tPLH 0 8 ns pF CL 0 5 µs tPHL tPLH 0 6 ns pF CL 0 4 µs tPLH tPLH 5 0 10 15 1 5 0 5 0 4 3 0 1 0 0 75 µs Propagation Delay Time 3 State Control to Q tPHZ 5 0 10 15 75 45 40 150 90 80 ns tPZH 5 0 10 15 120 ...

Page 389: ...DS Q3 CARRY OUT MASTER RESET MODE CONTROL TRUTH TABLE Mode A Mode B First Stage Output Carry to Second Stage Application 0 0 Normal Count and Display At 9 to 0 transition of first stage 5 digit Counter 0 1 Inhibited Input Clock Test Mode Clock directly into stages 1 2 and 4 1 1 Inhibited At 4 to 5 transition of first stage 4 digit counter with 10 and roundoff at front end 1 0 Counts 3 4 5 6 7 5 Co...

Page 390: ... result in Error Out to go to a 1 If error detection is not needed tie Clock B high or low and leave Pins 1 and 22 unconnected CLOCK A CLOCK B RESET ERROR OUT GOOD PULSE ERROR 1 ERROR 2 ERROR 3 ERROR 4 GOOD PULSE CLOCK SKEW RANGE NOTES 1 The skew is the time difference between the low to high transition of CA to the high to low transition of CB or vice versa Capacitors C1 C22 tied from pins 1 and ...

Page 391: ... 2 Forcing a BCD Stage to the Q Outputs When the Q outputs of a given stage are required this configuration will lock up the selected stage within four clock cycles The select line feedback may be hardwired or switched CLOCK BCD FOR SELECTED STAGE Q0 CLOCK A Q1 Q2 Q3 SC DS5 DS4 DS3 DS2 DS1 MC14534B MODE B CLOCK A Eout MR Cext DS2 DS1 MODE A Q0 3 ST BCD Cext CLOCK B VDD 3 ST DIG DS4 Q3 5 4 3 2 1 10...

Page 392: ...TL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C T...

Page 393: ...5 0 5 1 5 1 7 0 36 0 9 3 5 0 7 0 14 0 35 1 1 mAdc VOH 2 5 Vdc Source VOH 4 6 Vdc Pin 13 VOH 9 5 Vdc VOH 13 5 Vdc 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Q...

Page 394: ...66 ns pF CL 567 ns tPHL 0 5 ns pF CL 425 ns tPHL 5 0 10 15 1500 600 450 3000 1200 900 ns Clock Pulse Width tWH 5 0 10 15 600 200 170 300 100 85 ns Clock Pulse Frequency 50 Duty Cycle fcl 5 0 10 15 1 2 3 0 5 0 0 4 1 5 2 0 MHz Clock Rise and Fall Time tTLH tTHL 5 0 10 15 No Limit Reset Pulse Width tWH 5 0 10 15 1000 400 300 500 200 150 ns The formulas given are for the typical characteristics only a...

Page 395: ...hen Clock Inhibit is brought low no oscillator start up time is required When Clock Inhibit is low the counter will start counting on the occurrence of the first negative edge of the clocking source at IN1 OSC INHIBIT Pin 14 A high level on this pin stops the RC oscillator which allows for very low power standby op eration May also be used in conjunction with an external clock with essentially the...

Page 396: ... Input Stage Selected 8 Bypass D C B A Stage Selected for Decode Out 1 0 0 0 0 1 1 0 0 0 1 2 1 0 0 1 0 3 1 0 0 1 1 4 1 0 1 0 0 5 1 0 1 0 1 6 1 0 1 1 0 7 1 0 1 1 1 8 1 1 0 0 0 9 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16 FUNCTION TABLE In1 Set Reset Clock Inh OSC Inh Out 1 Out 2 Decode Out 0 0 0 0 No Change 0 0 0 0 Advance to next state X 1 0 0 0 0 1 ...

Page 397: ...C DIAGRAM STAGES 18 THRU 23 24 17 STAGES 10 THRU 15 16 T 9 STAGES 2 THRU 7 8 T 1 6 2 RESET 8 BYPASS 14 OSC INHIBIT 3 IN 1 4 OUT 1 OUT 2 5 SET 1 7 CLOCK INHIBIT R En C S Q A 9 B 10 C 11 D 12 DECODER DECODER OUT 13 15 MONO IN V DD PIN 16 V SS PIN 8 ...

Page 398: ...pical CX versus Pulse Width VDD 5 0 V Figure 4 Typical CX versus Pulse Width VDD 10 V 100 0 1 1 0 10 1000 100 10 1 0 CX EXTERNAL CAPACITANCE pF PULSE WIDTH t W µs RX 100 kΩ 50 kΩ 10 kΩ 5 kΩ TA 25 C VDD 5 V FORMULA FOR CALCULATING tW IN MICROSECONDS IS AS FOLLOWS tW 0 00247 RX CX 0 85 WHERE R IS IN kΩ CX IN pF 1000 100 10 1 0 CX EXTERNAL CAPACITANCE pF 100 0 1 1 0 10 PULSE WIDTH t W µs FORMULA FOR ...

Page 399: ...ons in parallel All flip flops are now at a 1 The count er is now returned to the normal 24 stages in series configu ration One more pulse is entered into In1 which will cause the counter to ripple from an all 1 state to an all 0 state Figure 8 Functional Test Circuit VDD VSS PULSE GENERATOR SET RESET 8 BYPASS IN1 C INH MONO IN OSC INH C B A D OUT 1 OUT 2 DECODE OUT FUNCTIONAL TEST SEQUENCE Inputs...

Page 400: ...on the first negative clock transition The output returns high depending on the 8 Bypass A B C and D inputs and the clock input period A 2n frequency division where n the number of stages selected from the truth table is obtainable at Decode Out A 20 divided output of IN1 can be obtained at OUT1 and OUT2 Figure 9 Time Interval Configuration Using an External Clock Set and Clock Inhibit Functions D...

Page 401: ...negative transition of the clock input causes Decode Out to go high Since the Mono In input is being used the output becomes monostable The pulse width of the output is dependent on the external timing components The second and all subsequent pulses occur at 2n x the clock period intervals where n the number of stages selected from the truth table PULSE GEN CLOCK 8 BYPASS A B C D RESET SET CLOCK I...

Page 402: ... Inh input the oscillator is disabled This puts the device in a low current standby condition The rising edge of the Reset pulse will cause the output to go low This in turn causes Osc Inh to go low However while Reset is high the oscillator is still disabled i e standy condition After Reset goes low the output remains low for 2n 2 of the oscillator s period After the part times out the output aga...

Page 404: ...acitance Pin 2 or 14 Cin 25 pF Input Capacitance Other Inputs Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package Q Low Q High IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Quiescent Current Active State Both Per Package Q High Q Low IDD 5 0 10 15 2 0 2 0 2 0 0 04 0 08 0 13 0 20 0 45 0 70 2 0 2 0 2 0 mAdc Total Supply Current at an external load capacitance CL and at external...

Page 405: ...h A B or Reset tWH tWL 5 0 10 15 170 90 80 85 45 40 ns Retrigger Time trr 5 0 10 15 0 0 0 ns Output Pulse Width Q or Q Refer to Figures 8 and 9 CX 0 002 µF RX 100 kΩ T 5 0 10 15 198 200 202 210 212 214 230 232 234 µs CX 0 1 µF RX 100 kΩ 5 0 10 15 9 3 9 4 9 5 9 86 10 10 14 10 5 10 6 10 7 ms CX 10 µF RX 100 kΩ 5 0 10 15 0 91 0 92 0 93 0 965 0 98 0 99 1 03 1 04 1 06 s Pulse Width Match between circui...

Page 406: ... RX CX VSS CX VSS Vin CX RX A B RESET A B RESET Q Q Q Q VSS CL CL CL CL 20 ns 20 ns VDD 0 V 90 10 Vin ID INPUT CONNECTIONS Characteristics Reset A B tPLH tPHL tTLH tTHL T tWH tWL VDD PG1 VDD tPLH tPHL tTLH tTHL T tWH tWL VDD VSS PG2 tPLH R tPHL R tWH tWL PG3 PG1 PG2 Figure 3 Switching Test Circuit Includes capacitance of probes wiring and fixture parasitic NOTE Switching test waveforms for PG1 PG2...

Page 407: ...DTH RELATIVE FREQUENCY OF OCCURRENCE 2 1 0 1 2 15 14 13 12 11 10 9 8 7 6 5 VDD SUPPLY VOLTAGE VOLTS NORMALIZED PULSE WIDTH CHANGE WITH RESPECT TO VALUE AT V DD 10 V TA 25 C RX 100 kΩ CX 0 1 µF 0 POINT PULSE WIDTH VDD 5 0 V T 9 8 ms VDD 10 V T 10 ms VDD 15 V T 10 2 ms RX 100 kΩ CX 0 1 µF Figure 7 Typical Total Supply Current versus Output Duty Cycle TOTAL SUPPLY CURRENT A µ 1000 100 10 1 0 0 1 0 00...

Page 408: ...acitor CX completely charged to VDD When the trigger input A goes from VSS to VDD while inputs B and Reset are held to VDD a valid trigger is recognized which turns on comparator C1 and N channel transistor N1 At the same time the output latch is set With transistor N1 on the capacitor CX rapidly discharges toward VSS until Vref1 is reached At this point the output of comparator C1 changes state a...

Page 409: ... Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the Reset input the output pulse T can be made significantly shorter than the minimum pulse width specifi cation POWER DOWN CONSIDERATIONS Large capacitance values can cause problems due to the large amount of energy stored When a system containing the MC14538B is powered down the capa...

Page 410: ... 13 Non Retriggerable Monostables Circuitry CX RX VDD Q Q RESET VDD B VDD A B RISING EDGE TRIGGER CX RX VDD Q Q RESET VDD B A VSS FALLING EDGE TRIGGER CX RX VDD Q Q A B RESET VDD CX RX VDD Q Q RESET VDD A B FALLING EDGE TRIGGER RISING EDGE TRIGGER NC NC NC VDD VDD A B Figure 14 Connection of Unused Sections Q Q CD ...

Page 412: ...nput Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 85 µA kHz f IDD IT 1 70 µA kHz f IDD IT 2 60 µA kHz f IDD µAdc Data labelled Typ is not to be use...

Page 413: ...ns pF CL 60 ns tPLH 5 0 10 15 225 110 85 450 220 170 ns tPHL 1 7 ns pF CL 160 ns tPHL 0 66 ns pF CL 82 ns tPHL 0 5 ns pF CL 65 ns tPHL 5 0 10 15 245 115 90 490 230 180 ns Strobe Input to Output tPLH tPHL 1 7 ns pF CL 60 ns tPLH tPHL 0 66 ns pF CL 42 ns tPLH tPHL 0 5 ns pF CL 35 ns tPLH tPHL 5 0 10 15 145 75 60 290 150 120 ns The formulas given are for the typical characteristics only at 25_C Data ...

Page 414: ...VDD VSS A B ST X0 X1 X2 X3 ST Y0 Y1 Y2 Y3 W Z 20 ns 20 ns Vin VDD CL CL 0 01 µF CERAMIC 500 µF VSS 90 50 10 50 DUTY CYCLE ID PIN ASSIGNMENT LOGIC DIAGRAM 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Y2 Y3 A ST VDD W Y0 Y1 X2 X3 B ST VSS Z X0 X1 B A X0 X1 X2 X3 Y0 Y1 Y2 Y3 2 14 6 5 4 3 10 11 12 13 ST 1 Z 7 9 W 15 ST ...

Page 416: ...Cin 5 0 7 5 pF Quiescent Current Pin 5 is High Auto Reset Disabled IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Auto Reset Quiescent Current Pin 5 is low IDDR 10 15 250 500 30 82 250 500 1500 2000 µAdc Supply Current Dynamic plus Quiescent ID 5 0 10 15 ID 0 4 µA kHz f IDD ID 0 8 µA kHz f IDD ID 1 2 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes bu...

Page 417: ... CL 2475 ns tPHL tPLH 5 0 10 15 6 0 3 5 2 5 18 10 7 5 µs Clock Pulse Width tWH cl 5 0 10 15 900 300 225 300 100 85 ns Clock Pulse Frequency 50 Duty Cycle fcl 5 0 10 15 1 5 4 0 6 0 0 75 2 0 3 0 MHz MR Pulse Width tWH R 5 0 10 15 900 300 225 300 100 85 ns Master Reset Removal Time trem 5 0 10 15 420 200 200 210 100 100 ns The formulas given are for the typical characteristics only at 25_C Data label...

Page 418: ...PIN 7 FREQUENCY SELECTION TABLE A B Number of Counter Stages n Count 2n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 TRUTH TABLE State Pin 0 1 Auto Reset 5 Auto Reset Operating Auto Reset Disabled Master Reset 6 Timer Operational Master Reset On Q Q 9 Output Initially Low After Reset Output Initially High After Reset Mode 10 Single Cycle Mode Recycle Mode Figure 3 Oscillator Circuit Using RC Con...

Page 419: ...tes of B However when B is 0 normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator i e effectively outputting 28 The Q Q select output control pin provides for a choice of output level When the counter is in a reset condition and Q Q select pin is set to a 0 the Q output is a 0 corre spondingly when Q Q select pin is set to a 1 the Q output is a 1...

Page 420: ...INGS Voltages referenced to VSS Rating Symbol Value Unit DC Supply Voltage VDD 0 5 to 18 V Input Voltage All Inputs Vin 0 5 to VDD 0 5 V DC Input Current per Pin Iin 10 mA Operating Temperature Range TA 55 to 125 _C Power Dissipation per Package PD 500 mW Storage Temperature Range Tstg 65 to 150 _C Maximum Continuous Output Drive Current Source or Sink per Output IOHmax IOLmax 10 mA Maximum Contin...

Page 421: ...IOH 5 0 5 0 10 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 10 1 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 9 5 Vdc VOL 1 5 Vdc IOL 5 0 10 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 10 1 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Cin 5 0 7 5 pF Quiescent Current Per Package Vin 0 or VDD Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010...

Page 422: ...5 0 10 15 100 50 40 200 100 80 ns Turn Off Delay Time tPLH 1 7 ns pF CL 520 ns tPLH 0 66 ns pF CL 217 ns tPLH 0 5 ns pF CL 160 ns tPLH 5 0 10 15 605 250 185 1210 500 370 ns Turn On Delay Time tPHL 1 7 ns pF CL 420 ns tPHL 0 66 ns pF CL 172 ns tPHL 0 5 ns pF CL 130 ns tPHL 5 0 10 15 505 205 155 1650 660 495 ns Setup Time tsu 5 0 10 15 350 450 500 ns Hold Time th 5 0 10 15 40 30 20 ns Latch Disable ...

Page 423: ...0 Vdc VSS 0 Vdc POLmax 70 mWdc Figure 3 Dynamic Power Dissipation Signal Waveforms Inputs BI and Ph low and Inputs D and LD high f in respect to a system clock Figure 4 Dynamic Signal Waveforms a Inputs D Ph and BI low and Inputs A B and LD high b Inputs D Ph and BI low and Inputs A and B high c Data DCBA strobed into latches 20 ns 20 ns VDD VSS VOH VOL 10 50 90 1 2f 50 DUTY CYCLE A B AND C ANY OU...

Page 424: ...ARGE READOUT PIN ASSIGNMENT CONNECTIONS TO SEGMENTS 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d e g f VDD a b c D B C LD VSS BI PH A SQUARE WAVE VSS TO VDD COMMON BACKPLANE ONE OF SEVEN SEGMENTS MC14543B OUTPUT Ph MC14543B OUTPUT Ph VSS APPROPRIATE VOLTAGE MC14543B OUTPUT Ph VSS COMMON CATHODE LED COMMON ANODE LED VDD MC14543B OUTPUT Ph VDD MC14543B OUTPUT Ph APPROPRIATE VOLTAGE VSS VDD PIN 16 VSS PI...

Page 425: ...sion of Non significant zero Capable of Driving Two Low power TTL Loads One Low power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages referenced to VSS Rating Symbol Value Unit DC Supply Voltage VDD 0 5 to 18 V Input Voltage All Inputs Vin 0 5 to VDD 0 5 V DC Input Current per Pin Iin 10 mAdc Operating Tempera...

Page 426: ...IOH 5 0 5 0 10 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 10 1 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 9 5 Vdc VOL 1 5 Vdc IOL 5 0 10 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 10 1 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Cin 5 0 7 5 pF Quiescent Current Per Package Vin 0 or VDD Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010...

Page 427: ... 50 40 200 100 80 ns Turn Off Delay Time tPLH 1 7 ns pF CL 520 ns tPLH 0 66 ns pF CL 217 ns tPLH 0 5 ns pF CL 160 ns tPLH 5 0 10 15 605 250 185 1210 500 370 ns Turn On Delay Time tPHL 1 7 ns pF CL 420 ns tPHL 0 66 ns pF CL 172 ns tPHL 0 5 ns pF CL 130 ns tPHL 5 0 10 15 505 205 155 1650 660 495 ns Setup Time tsu 5 0 10 15 0 0 0 40 15 10 ns Hold Time th 5 0 10 15 80 30 20 40 15 10 ns Latch Disable P...

Page 428: ... 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 3 4 X X 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 1 4 5 X 1 0 0 0 1 0 1 0 1 0 1 1 0 1 1 5 X 1 0 0 0 1 1 0 0 1 0 1 1 1 1 1 6 X 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 7 X X 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 8 9 X X 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 9 Blank X 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 Blank X...

Page 429: ...0 Vdc VSS 0 Vdc POLmax 70 mWdc Figure 3 Dynamic Power Dissipation Signal Waveforms Inputs BI and Ph low and Inputs D and LD high f in respect to a system clock Figure 4 Dynamic Signal Waveforms a Inputs D Ph and BI low and Inputs A B and LD high b Inputs D Ph and BI low and Inputs A and B high c Data DCBA strobed into latches 20 ns 20 ns VDD VSS VOH VOL 10 50 90 1 2f 50 DUTY CYCLE A B AND C ANY OU...

Page 430: ... 1 3 INPUT CODE D C B A D C B A D C B A D C B A D C B A D C B A a g a g a g a g a g a g RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO TRAILING EDGE ZERO SUPPRESSION DISPLAYS CONNECT TO VDD 1 0 0 0 1 1 0 MC14544B MC14544B MC14544B MC14544B MC14544B MC14544B 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 5 0 1 3 0 0 INPUT CODE D C B A D C B A D C B A D C B A D C B A D C B A a g a g a g a g a g a ...

Page 431: ...tput IOHmax 65 mA Maximum Continuous Power Dissipation PD 1200 mW Maximum Ratings are those values beyond which damage to the device may occur See Power Derating Curve Figure 1 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields however it is advised that normal precautions be taken to avoid application of any voltage higher than maxim...

Page 432: ...10 9 1 8 8 8 4 9 2 9 1 9 0 8 9 8 5 9 3 9 3 9 2 9 0 8 8 9 3 9 2 8 1 Vdc IOH 5 0 mA IOH 10 mA IOH 20 mA IOH 40 mA IOH 65 mA 15 14 13 8 13 5 14 2 14 1 14 0 13 8 13 5 14 3 14 3 14 2 14 0 13 7 14 4 14 2 13 3 Vdc Output Drive Current VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 32 0 80 2 10 0 26 0 65 1 7 0 44 1 13 4 4 0 18 0 45 1 2 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Cap...

Page 433: ...ic Symbol VDD Vdc Min Typ Max Unit Output Rise Time tTLH 5 0 10 15 40 40 40 80 80 80 ns Output Fall Time tTHL 5 0 10 15 125 75 70 250 150 140 ns Data Propagation Delay Time tPLH 5 0 10 15 750 300 200 1500 600 400 ns tPHL 5 0 10 15 750 300 200 1500 600 400 Blank Propagation Delay Time tPLH 5 0 10 15 750 300 200 1500 600 400 ns tPHL 5 0 10 15 500 250 170 1000 500 340 ...

Page 434: ... 2 D 6 14 g 15 f 9 e 10 d 11 c 12 b 13 a 4 BI 1200 1000 800 600 400 200 0 175 150 125 100 75 50 25 TA AMBIENT TEMPERATURE 0 C Figure 1 Ambient Temperature Power Derating P D MAXIMUM POWER DISSIPATION mW PER PACKAGE L CERAMIC P PDIP D SOIC 410 mW L 230 mW P 150 mW D ...

Page 435: ...number of segments and worst case conditions A filament pre warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament GAS DISCHARGE READOUT FLUORESCENT READOUT Caution Absolute maximum working voltage 18 0 V VDD VSS COMMON CATHODE LED 1 7 V VDD VSS COMMON ANODE LED 1 7 V VDD VSS VDD VSS COMMON CATHODE LED VDD VSS VZD VDD VSS APPROPRIAT...

Page 436: ...ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages referenced to VSS Rating Symbol Value Unit DC Supply Voltage VDD 0 5 to 18 Vdc Input Voltage All Inputs Vin 0 5 to VDD 0 5 Vdc DC Input Current per Pin Iin 10 mAdc Power Dissipation per Package PD 500 mW Operating Temperature Range TA 55 to 125 _C Storage Temperature Range Tstg 65 to 150 _C Maximum Ratings are those values beyond which damage to the device...

Page 437: ... 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Cin 5 0 7 5 pF Quiescent Current Per Package Clock 0 V Other Inputs VDD or 0 V Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 8 µA kHz f IDD IT 1 6...

Page 438: ...6 ns pF CL 177 ns tPLH tPHL 0 5 ns pF CL 130 ns Clock to Sout tPLH tPHL 1 7 ns pF CL 665 ns tPLH tPHL 0 66 ns pF CL 277 ns tPLH tPHL 0 5 ns pF CL 195 ns Clock to EOC tPLH tPHL 1 7 ns pF CL 215 ns tPLH tPHL 0 66 ns pF CL 97 ns tPLH tPHL 0 5 ns pF CL 75 ns tPLH tPHL 5 0 10 15 5 0 10 15 5 0 10 15 500 210 155 750 310 220 300 130 100 1000 420 310 1500 620 440 600 260 200 ns SC D FF or MR Setup Time tsu...

Page 439: ...L CL CL CL CL VDD VSS Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout C SC FF MR D PROGRAMMABLE PULSE GENERATOR TIMING DIAGRAM Q8 is ninth bit of serial information available from 8 bit register NOTE Pin 10 VSS INH Indicates Serial Out is inhibited low Don t care condition ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ CLOCK SC D Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout INH INH Q7 Q6 Q7 ...

Page 440: ...te and must be disregarded For 8 bit operation FF is tied to VSS For applications with more than 8 but less than 16 bits use the basic connections shown in Figure 1 The FF input of the MC14559B is used to shorten the setup Tying FF directly to the least significant bit used in the MC14559B allows EOC to provide the cascading signal and results in smooth transition of serial information from the MC...

Page 441: ...e 4 Because each successive approximation register SAR has a capability of handling only an eight bit word two must be cascaded to make an ADC with more than eight bits When it is necessary to cascade two SAR s the second SAR must have a stable resettable state to remain in while awaiting a subsequent start signal However the first stage must not have a stable resettable state while recycling be c...

Page 442: ...ata is started with every external control pulse Additional Motorola Parts for Successive Approximation ADC Monolithic digital to analog converters The MC1408 1508 converter has eight bit resolution and is avail able with 6 7 and 8 bit accuracy The amplifier compara tor block The MC1407 1507 contains a high speed operational amplifier and a high speed comparator with ad justable window With these ...

Page 443: ...for Control Input VEE for Switch I O 0 5 to VDD 0 5 V Iin Input Current DC or Transient per Control Pin 10 mA Isw Switch Through Current 25 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW ...

Page 444: ...N OUT AND COMMONS OUT IN W X Y Z Voltages Referenced to VEE Recommended Peak to Peak Voltage Into or Out of the Switch VI O Channel On or Off 0 VDD 0 VDD 0 VDD Vp p Recommended Static or Dynamic Voltage Across the Switch Figure 3 Vswitch Channel On 0 600 0 600 0 300 mV Output Offset Voltage VOO Vin 0 V No Load 10 µV ON Resistance Ron 5 0 10 15 Vswitch v500 mV Vin VIL or VIH Control and Vin 0 to VD...

Page 445: ...dthrough Attenuation Figure 5 RL 1 kΩ Vin 1 2 VDD VEE p p fin 55 MHz 10 50 dB Channel Separation Figure 6 RL 1 kΩ Vin 1 2 VDD VEE p p fin 3 MHz 10 50 dB Crosstalk Control Input to Common O I Figure 7 R1 1 kΩ RL 10 kΩ Control tr tf 20 ns 10 75 mV Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance This device contains protection...

Page 446: ...h Circuit Schematic IN OUT OUT IN VDD VDD VDD VEE VDD VEE LEVEL CONVERTED CONTROL IN OUT OUT IN CONTROL CONTROL 9 W0 15 W1 1 X0 2 X1 3 Y0 6 Y1 10 Z0 11 Z1 12 8 7 16 VDD VEE 14 W 4 X 5 Y 13 Z CONTROL LEVEL CONVERTER Figure 2 MC14551B Functional Diagram VSS ...

Page 447: ...width and Off Channel Feedthrough Attenuation Figure 6 Channel Separation Adjacent Channels Used for Setup CONTROL Vout CL 50 pF RL Vin CONTROL CL 50 pF RL Vout RL OFF ON Vin VDD VEE 2 Figure 7 Crosstalk Control Input to Common O I Figure 8 Off Channel Leakage CONTROL Vout CL 50 pF RL R1 CONTROL SECTION OF IC OFF CHANNEL UNDER TEST OTHER CHANNEL S VDD VEE VEE VDD VEE VDD Control input used to turn...

Page 448: ...TAGE VOLTS R ON ON RESISTANCE OHMS TA 125 C 55 C 350 300 250 200 150 100 50 0 8 0 10 6 0 4 0 2 0 0 2 0 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS R ON ON RESISTANCE OHMS TA 125 C 25 C 25 C 55 C 700 600 500 400 300 200 100 0 8 0 10 6 0 4 0 2 0 0 2 0 4 0 6 0 8 0 10 Vin INPUT VOLTAGE VOLTS R ON ON RESISTANCE OHMS TA 125 C 55 C 25 C 350 300 250 200 150 100 50 0 8 0 10 6 0 4 0 2 0 0 2 0 4 0 6 0 8 0 10 Vin ...

Page 449: ...o 15 volts which is the recommended maximum difference be tween VDD and VEE Balanced supplies are not required However VSS must be greater than or equal to VEE For example VDD 10 volts VSS 5 volts and VEE 3 volts is acceptable See the table below Figure A Application Example EXTERNAL CMOS DIGITAL CIRCUITRY 9 Vp p ANALOG SIGNAL 0 TO 5 V DIGITAL CONTROL SIGNAL VDD VSS VEE SWITCH I O COMMON O I CONTR...

Page 450: ...issipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C TRUTH TABLE Inputs Master Reset Clock Disable LE Outputs 0 0 0 No Change 0 0 0 Adva...

Page 451: ...VOH 9 5 Vdc Other VOH 13 5 Vdc Outputs 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc Pin 3 VOL 1 5 Vdc IOL 5 0 10 15 0 5 1 1 1 8 0 4 0 9 1 5 0 88 2 25 8 8 0 28 0 65 1 20 mAdc VOL 0 4 Vdc Sink Other VOL 0 5 Vdc Outputs VOL 1 5 Vdc 5 0 10 15 3 0 6 0 18 2 5 5 0 15 4 0 8 0 20 1 6 3 5 10 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacita...

Page 452: ...Reset to Latch Enable Setup Time 2b tsu 5 0 10 15 600 400 200 300 200 100 ns Removal Time Latch Enable to Clock 2b trem 5 0 10 15 80 10 0 200 70 50 ns Clock Pulse Width 2a tWH cl 5 0 10 15 550 200 150 275 100 75 ns Reset Pulse Width 2b tWH R 5 0 10 15 1200 600 450 600 300 225 ns Reset Removal Time trem 5 0 10 15 80 0 20 180 50 30 ns Input Clock Frequency 2a fcl 5 0 10 15 1 5 5 0 7 0 0 9 2 5 3 5 MH...

Page 453: ...TER RESET SCAN OSCILLATOR DIGIT SELECT 1 DIGIT SELECT 2 DIGIT SELECT 3 UP AT 80 UP AT 980 UP AT 800 DISABLES CLOCK WHEN HIGH UNITS TENS HUNDREDS PULSE GENERATOR a 16 VDD Q3 Q2 Q1 Q0 O F DS1 DS2 DS3 8 VSS C LE DIS MR CL CL CL CL CL GENERATOR 1 b VDD Q3 Q2 Q1 Q0 O F DS1 DS2 DS3 VSS C LE MR DIS CL CL CL CL CL GENERATOR 2 GENERATOR 3 20 ns 20 ns 90 10 tPLH tPHL 50 50 tTHL tTLH 10 90 50 1 fcl tWL cl 99...

Page 454: ...e three BCD counters and the multiplexer scanning circuit While Master Reset is high the digit scanner is set to digit one but all three digit select outputs are disabled to prolong display life and the scan oscillator is inhibited The Disable input when high prevents the input clock from reaching the counters while still retaining the last count A pulse shaping circuit at the clock input permits ...

Page 455: ...DS2 DS1 C1A C1B O F µ 0 001 F 5 3 2 4 6 1 7 A B C D Ph LD BI a b c d e f g 9 10 11 12 13 15 14 MC14543B LSD VDD DISPLAYS ARE LOW CURRENT LEDs I peak 10 mA PER SEGMENT MSD VDD 5 3 2 4 6 1 7 A B C D Ph LD BI a b c d e f g 9 10 11 12 13 15 14 MC14543B 10 13 5 6 7 9 15 1 2 14 3 4 12 11 CLK DIS Q3 Q2 Q1 Q0 DS3 DS2 DS1 C1A C1B O F MC14553B MC14553B LE MR LE MR ...

Page 456: ...Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages...

Page 457: ... Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 2...

Page 458: ...for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Dynamic Power Dissipation Waveforms Figure 2 Dynamic Signal Waveforms All outputs connected to respective CL loads f system clock frequency LOGIC DIAGRAM MULTIPLIER CELL Inputs X0 X1 Y0 Y1 K1 and M2 low and inputs M0 and M1...

Page 459: ...K1 K0 and M M n 1 M n 2 M2 M1 M0 Binary Numbers Number of output binary digits m n Number of packages mxn 4 For m or n of both odd select next highest even number Y n 1 M n 2 M n 1 Y n 2 X0 X1 Y3 M2 M3 Y2 X0 X1 Y1 M0 M1 Y0 X0 X1 K0 K1 Y n 1 Y n 2 X2 X3 Y n 2 X m 2 X m 1 Y n 1 S m n 1 S m n 2 S m n 3 S m 2 S m 1 S m Y3 Y2 X2 X3 Y3 Y2 X m 2 X m 1 Y1 Y0 X2 X3 K2 K3 Y1 Y0 X m 2 X m 1 K m 2 K m 1 S m 1...

Page 460: ...nt per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating P and D DW Packages 7 0 mW C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C BLOCK DIAGRAM 2 4 MC14555B MC14556B 3 1 14 13 15 5 6 7 12 11 10 9...

Page 461: ...9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers ...

Page 462: ...PHL 0 66 ns pF CL 52 ns tPLH tPHL 0 5 ns pF CL 40 ns tPLH tPHL 5 0 10 15 200 85 65 400 170 130 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Dynamic Power Dissipation Signal Waveforms Figure 2 Dynamic Signal Waveforms All 8 outputs connect to ...

Page 463: ...ut Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C LENGTH SELECT TR...

Page 464: ...put Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 010 0 020 0 030 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 75 µA kHz f IDD IT 3 50 µA kHz f IDD IT 5 25 µA kHz f IDD µAdc Data labelled Typ is not to be used...

Page 465: ... 5 13 0 1 7 5 0 6 7 MHz Setup Time A or B to Clock or CE Worst case condition L1 L2 L4 L8 L16 L32 VSS Register Length 1 tsu 5 10 15 700 290 145 350 130 85 ns Best case condition L32 VDD L1 through L16 Don t Care Any register length from 33 to 64 5 10 15 400 165 60 45 5 0 Hold Time Clock or CE to A or B Best case condition L1 L2 L4 L8 L16 L32 VSS Register Length 1 th 5 10 15 200 100 10 150 60 50 ns...

Page 466: ... 15 16 9 10 11 12 5 4 3 2 1 8 7 6 L32 L16 L8 L4 V DD A B SEL Q Q CLOCK RESET L1 L2 V SS A B CE A B SELECT B A RESET CLOCK CE 9 6 7 3 4 5 C R 32 BIT 12 L32 C R 2 BIT 1 L2 2 L1 C R 1 BIT C R 16 BIT 13 L16 14 L8 C R 1 BIT C R 8 BIT 10 11 Q Q 15 L4 C R 4 BIT VDD PIN 16 VSS PIN 8 ...

Page 467: ...es referenced to VSS Rating Symbol Value Unit DC Supply Voltage VDD 0 5 to 18 V Input Voltage All Inputs Vin 0 5 to VDD 0 5 V DC Input Voltage per Pin Iin 10 mAdc Operating Temperature Range TA 55 to 125 _C Power Dissipation per Package PD 500 mW Storage Temperature Range Tstg 65 to 150 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P a...

Page 468: ...0 1 0 00001 0 1 1 0 µAdc Input Capacitance Cin 5 0 7 5 pF Quiescent Current Per Package Vin 0 or VDD Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 2 µA kHz f IDD IT 2 4 µA kHz f IDD IT 3 6 µA kHz f IDD µAdc Noise immunity specified for worst case ...

Page 469: ...ns tPHL 0 66 ns pF CL 242 ns tPHL 0 5 ns pF CL 160 ns tPHL 5 0 10 15 780 275 185 1560 550 370 ns The formulae given are for the typical characteristics only TRUTH TABLE Inputs Outputs Enable Pin 3 RBI Pin 5 D Pin 6 C Pin 2 B Pin 1 A Pin 7 a Pin 13 b Pin 12 c Pin 11 d Pin 10 e Pin 9 f Pin 15 g Pin 14 RBO Pin 4 Display 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 X 0 0 0 1 0 0 0 0 1 1 0 1 1 X 0 0 1 0 1 1 0 1 1 0 1...

Page 470: ...MOTOROLA CMOS LOGIC DATA MC14558B 6 432 LOGIC DIAGRAM 13 12 11 10 9 15 14 4 a b c d e f g RBO 6 2 1 7 5 3 ENABLE RBI A B C D ...

Page 471: ...BO RBI RBO RBI RBO RBI RBO N4 N3 N2 N1 N 1 N 2 N 3 En En En En En En En RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO Figure 3 Leading and Trailing Zero Suppression with PWM Intensity Blanking and No Lamp Test BLANKING VDD N4 N3 N2 N1 N 1 N 2 N 3 En En En En En En En RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO Figure 4 Zero Suppression with Lamp Test and Intensity Blanking LA...

Page 472: ...nd D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C TRUTH TABLE Input Output A4 A3 A2 A1 B4 B3 B2 B1 Cin Cout S4 S3 S2 S1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 ...

Page 473: ...4 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Qu...

Page 474: ...s pF CL 465 ns tPLH tPHL 0 66 ns pF CL 187 ns tPLH tPHL 0 5 ns pF CL 135 ns 5 0 10 15 550 220 160 1500 600 450 ns Turn Off Delay Time Cin to S tPLH 1 7 ns pF CL 715 ns tPLH 0 66 ns pF CL 197 ns tPLH 0 5 ns pF CL 215 ns tPLH 5 0 10 15 800 350 240 2250 975 750 ns Turn On Delay Time Cin to S tPHL 1 7 ns pF CL 565 ns tPHL 0 66 ns pF CL 197 ns tPHL 0 5 ns pF CL 145 ns tPHL 5 0 10 15 650 230 170 1800 60...

Page 475: ...d digit such as in this typical config uration A second MC14561B permits either digit to be added to or subtracted from the other or either word to appear unmodified at the output X Don t Care Zero Add Subtract Result 0 0 B plus A 0 1 B minus A 1 X B TRUTH TABLE ADD SUBTRACT ZERO B10 A10 B1 A1 MC14561B MC14561B MC14560B MC14560B F1 F2 F3 F4 A1 A3 A1 A4 COMP COMP Z F1 F2 F3 F4 A2 A3 A4 COMP COMP Z ...

Page 476: ...generates the correct BCD code and carry An NBCD adder block which performs the above function is available in a single CMOS package MC14560 Figure 2 b shows n decades cascaded for addition of n digit unsigned NBCD numbers Add time is typically 0 1 0 2n µs for n decades When the carry out of the most significant de cade is a logical 1 an overflow is indicated COMPLEMENT ARITHMETIC Complement arith...

Page 477: ...ive OR of Add Sub line and BS produces B which controls the B complementers If BS the sign of B is a logical 1 B is negative and the Add Sub line is a 0 add B to A then the output of the exclusive OR BS is a logical 1 and B is complemented If BS 1 and Add Sub 1 B is not complemented since subtracting a negative number is the same as adding a positive number When Add Sub is a 1 and BS 0 BS is a 1 a...

Page 478: ... truth table reveal that Overflow can be generated by the exclusive OR function of End Around Carry and Carry Out This analysis results in a minimum device count consisting of one exclusive OR package and one dual Majority Logic package to implement BS EAC Sign and Overflow The logic connections of these devices are shown in Figure 5 The output sign RS complements the result of the add subtract op...

Page 479: ...raw Hill 1962 2 McMOS Handbook Motorola Inc 1st Edition 3 Beuscher H Electronic Switching Theory and Circuits New York Van Nostrand Reinhold 1971 4 Garrett L CMOS May Help Majority Logic Win De signer s Vote Electronics July 19 1973 5 Richards R Digital Design New York Wiley Interscience 1971 Figure 7 Adder Subtracter for Unsigned NBCD Numbers A1 B1 A2 B2 An Bn Cin C Cout Cin C Cout Cin C Cout R1 ...

Page 480: ...Cout Cout OVERFLOW SIGN OF RS 1 4 MC14070 SIGN Z Z W W VDD EAC B1 A1 MC14561 MC14561 M5 M5 MC14561 MC14560 Cout MC14530 A B C D E A B C D E C C Z R1 A1 A2 A3 A4 F1 F2 F3 F4 A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 S3 S4 A1 A2 A3 A4 F1 F2 F3 F4 A1 A2 A3 A4 F1 F2 F3 F4 C C Z Cin 1 4 MC14070 1 4 MC14070 BS VDD A S BS ADD SUB Typical Add Subtract Time 0 6 0 4n s where n Number of Decades µ C C Z ...

Page 481: ...out 0 thus sign of R must be negative 1 0 1 1 EAC 1 because expression for R is in error by 1 A B when Cout 1 thus sign of R must be positive 0 There is never an overflow when 1 0 0 R B A B 10N 1 A B A 10N 1 No EAC 0 because 9 s complement expression for R is correct result B vA when Cout 0 thus sign of R must be negative 1 numbers of opposite sign are added 1 0 1 EAC 1 because expression for R is...

Page 482: ...f A 1 Negative BS Sign of B 1 Negative Cout Adder Carry Out Figure 10 Mapping of EAC Sign and Overflow Logic 0 1 1 1 0 1 0 0 End Around Carry AS Cout BS 1 1 0 1 0 0 0 1 Sign SGN AS Cout BS 0 1 0 0 1 0 0 0 Overflow OVF AS Cout BS Center of Symmetry EAC S2 ASBS Cout S3 ASBS Cout M3 ASBS Cout SGN S2 ASBS Cout S3 ASBS Cout M3 ASBS Cout 0 1 1 1 0 1 0 0 EAC 0 0 1 1 1 1 0 0 Cout 0 1 0 0 1 0 0 0 OVF ę ę K...

Page 483: ... VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C...

Page 484: ... Vdc VOH 9 5 Vdc VOH 13 5 Vdc IOH 5 0 5 0 10 15 3 0 0 64 1 6 4 2 2 4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 2...

Page 485: ...tTLH tTHL 5 0 10 15 100 50 40 200 100 80 ns Propagation Delay Time tPLH tPHL 1 7 ns pF CL 315 ns tPLH tPHL 0 66 ns pF CL 127 ns tPLH tPHL 0 5 ns pF CL 95 ns tPLH tPHL 5 0 10 15 400 160 120 1000 400 300 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figu...

Page 486: ...valent Outputs Equivalent Input A4 A3 A2 A1 Equivalent Output F4 F3 F2 F1 0 0 0 0 0 9 1 0 0 1 1 0 0 0 1 8 1 0 0 0 2 0 0 1 0 7 0 1 1 1 3 0 0 1 1 6 0 1 1 0 4 0 1 0 0 5 0 1 0 1 5 0 1 0 1 4 0 1 0 0 6 0 1 1 0 3 0 0 1 1 7 0 1 1 1 2 0 0 1 0 8 1 0 0 0 1 0 0 0 1 9 1 0 0 1 0 0 0 0 0 10 1 0 1 0 7 0 1 1 1 11 1 0 1 1 6 0 1 1 0 12 1 1 0 0 5 0 1 0 1 13 1 1 0 1 4 0 1 0 0 14 1 1 1 0 3 0 0 1 1 15 1 1 1 1 2 0 0 1 0 ...

Page 487: ...added to or subtracted from the other or either word to appear unmodified at the output ADD SUBTRACT ZERO MC14561B MC14560B MC14561B MC14560B UNITS TENS B10 A10 B1 A1 A1 A2 A3 A4 COMP COMP Z F1 F2 F3 F4 A1 A2 A3 A4 B1 B2 B3 Cin S1 S2 S3 S4 Cout A1 A2 A3 A4 COMP COMP Z F1 F2 F3 F4 A1 A2 A3 A4 B1 B2 B3 Cin S1 S2 S3 S4 Cout B4 TRUTH TABLE Zero Add Subtract Result 0 0 B plus A 0 1 B minus A 1 X B X Do...

Page 488: ...50 Figure 3 Serial Add Subtract Circuit ADD SUBTRACT CLOCK A REGISTER 100 s 10 s 1 s 100 s 10 s 1 s B REGISTER MC14561B MC14560B A1 A2 A3 A4 COMP COMP Z F1 F2 F3 F4 D C Q A1 Cin A2 A3 A4 B1 B2 B3 B4 S1 S2 S3 S4 Cout TYPE D FLIP FLOP RESULT ...

Page 489: ...y Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packag...

Page 490: ...e Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 010 0 020 0 030 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 94 µA kHz f IDD IT 3 81 µA kHz f IDD IT 5 52 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes but is intended as an indication of the...

Page 491: ...0 Duty Cycle tWH 5 0 10 15 600 220 150 300 110 75 ns Clock Pulse Frequency fcl 5 0 10 15 1 9 5 6 8 0 1 1 3 0 4 0 MHz Data to Clock Setup Time tsu 1 5 0 10 15 20 10 0 170 64 60 ns tsu 0 5 0 10 15 20 10 0 91 58 48 ns Data to Clock Hold Time th 1 5 0 10 15 350 165 155 263 109 100 ns th 0 5 0 10 15 350 200 140 267 140 93 ns Clock Input Rise and Fall Times tr tf 5 0 10 15 15 5 4 µs The formulas given a...

Page 492: ...s Q32 Q48 Q64 Q80 Q96 Q112 and Q128 will occur at Clock Pulse 32 48 64 80 96 112 128 in the same relationship as Q16 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS CLOCK DATA IN Q16 CLOCK DATA IN Q16 PULSE 1 PULSE 2 PULSE 16 PULSE 17 50 50 50 90 10 50 tWH tWL tr tf 50 50 tsu 0 th 0 50 90 10 tPHL tTHL PULSE 1 PULSE 2 PULSE 16 PULSE 17 50 50 50 tWH tWL 50 50 50 tsu 1 th 1 50 90 10 tTHL tPLH ...

Page 493: ...8 Vdc Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per ...

Page 494: ...c Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 0 µA kHz f IDD IT 2 0 µA kHz f IDD IT 3 0 µA kHz f IDD µAdc Data labelled Typ is not to be use...

Page 495: ...282 ns tPHL 0 5 ns pF CL 185 ns tPHL 5 0 10 15 930 315 210 3000 1000 750 ns Clock Pulse Width tWH cl 5 0 10 15 1200 400 270 400 125 90 ns Reset Pulse Width tWH R 5 0 10 15 1200 400 270 400 125 90 ns Clock Pulse Frequency fcl 5 0 10 15 1 0 2 5 4 2 0 3 1 0 1 5 MHz Clock Pulse Rise and Fall Time tTLH tTHL 5 0 10 15 No Limit Monostable Multivibrator Pulse Width tWH Qm 5 0 10 15 1200 400 300 2800 900 6...

Page 496: ... PROGRAMMABLE PULSE GENERATOR VDD CA CB RESET 5 6 B A CONTROL Q0A Q1A Q2A Q3A Q0B Q1B Q2B Qm VSS CL CL CL CL CL CL CL CL 20 ns tWH cl 50 10 10 OR 5 6 CLOCK AND B RESET Q3A OR Q2B Qm tWH Qm WHQm t 50 50 tPLH tTHL tTLH 10 90 50 tPHL tPLH tWH R 50 10 90 20 ns fcl Figure 2 Switching Time Test Circuit and Waveforms 90 ...

Page 497: ...A 6 459 MC14566B TIMING DIAGRAM Monostable Multivibrator Divide By 10 Counter Divide By 5 Divide By 6 CLOCK RESET Q0 Q1 Q2 Q3 CLOCK RESET CONTROL 5 6 Q0 Q1 Q2 0 1 2 3 4 5 6 7 8 9 0 1 0 1 2 3 4 5 0 1 2 3 4 0 A B Qm DON T CARE ...

Page 498: ...e taken in the indicated circuit to filter line transients which may cause false counting TENTH SECONDS HOURS 1 0 M 60 Hz 1500 pF VDD VDD 5 6 10 5 6 10 5 6 10 5 6 10 C C C C C C C C Q0 Q1 Q2 Q0 Q1 Q2 Q0 Q1 Q2 Q0 Q1 Q2 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 R R A B C A B A B A B A B Qm Qm Qm Qm D MINUTES SECONDS MC14011B ...

Page 499: ...es ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages referenced to VSS Rating Symbol Value Unit DC Supply Voltage VDD 0 5 to 18 Vdc Input Voltage All Inputs Vin 0 5 to VDD 0 5 Vdc DC Input Current per Pin Iin 10 mAdc Power Dissipation per Package PD 500 mW Operating Temperature Range TA 55 to 125 _C Storage Temperature Range Tstg 65 to 150 _C Maximum Ratings are those values beyond which damage to th...

Page 500: ...dc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Cin 5 0 7 5 pF Quiescent Current Per Package Vin 0 or VDD Iout 0 µA IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers swi...

Page 501: ...ts tPHL 5 0 10 15 550 195 120 1100 390 240 ns Turn On Delay Time PCout and LD Outputs tPLH 5 0 10 15 675 300 190 1350 600 380 ns DIVIDE BY 4 16 64 OR 100 COUNTER D1 Maximum Clock Pulse Frequency Division Ratio 4 64 or 100 fcl 5 0 10 15 3 0 8 0 10 6 0 16 22 MHz Division Ratio 16 5 0 10 15 1 0 3 0 5 0 2 5 6 3 9 7 Propagation Delay Time Q1 C2 Output Division Ratio 4 64 or 100 tPLH tPHL 5 0 10 15 450 ...

Page 502: ...GH 50 20 ns 20 ns tW PCin 90 50 10 tPLH tPLH tTHL 90 10 tPHL tPHL tTLH THREE STATE THREE STATE 75 tPLH tPHL 25 VOH VOL PCin PG1 LD PCout B A VDD VSS CL DP0 CTL DP1 DP2 DP3 PCin F G C1 PE PCout LD Q1 C2 0 20 ns 20 ns tW C1 tPHL 10 50 90 tTLH tTHL fin fmax 90 50 10 C1 Q1 C2 DP0 DP1 DP2 DP3 PCin F G C1 PE CTL Q1 C2 PCout LD 0 VSS VDD a b CL DP0 DP1 DP2 DP3 PCin F G C1 PE CTL Q1 C2 PCout LD 0 CL VSS V...

Page 503: ...OLA CMOS LOGIC DATA 6 465 MC14568B LOGIC DIAGRAM PCin B REF C1 F G 0 COUNTER D2 D Q C C D Q C Q PE Q C D PCout LD COUNTER D1 Q1 C2 CTL PE 14 9 10 11 3 13 1 15 2 VDD PIN 16 VSS PIN 8 4 5 6 7 DP3 DP2 DP1 DP0 A ...

Page 504: ... Typical Maximum Frequency Divider D2 Division ratio 2 CL 50 pF 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 100 80 60 40 20 0 20 40 T TEMPERATURE C f FREQUENCY MHz VDD 15 V VDD 10 V VDD 5 V 12 10 8 6 4 2 0 100 80 60 40 20 0 20 40 T TEMPERATURE C f FREQUENCY MHz VDD 15 V VDD 10 V VDD 5 V 6 5 4 3 2 1 0 100 80 60 40 20 0 20 40 T TEMPERATURE C f FREQUENCY MHz VDD 15 V VDD 10 V VDD 5 V ...

Page 505: ...ome intermedi ate value until the frequencies of both signals are equal and their phase difference equal to zero i e until locked condition is obtained Capture and lock range will be determined by the VCO fre quency range The comparator is provided with a lock indi cator output which will stay at logic 1 in locked conditions The state diagram Figure 5 depicts the internal state transitions It assu...

Page 506: ...when cascaded must be used as the most significant digit Because of this it can be cascaded with binary counters as well as with BCD counters MC14569B MC14522B MC14526B TYPICAL APPLICATIONS Figure 6 Cascading MC14568B and MC14522B or MC14526B with MC14569B fin CF C MC14569B ZERO DETECT CF C MC14522B OR MC14526B Q4 PE 0 CF C MC14522B OR MC14526B Q4 PE 0 Q1 C2 PE 0 MC14568B LSD MSD fout DP0 DP3 DP0 ...

Page 507: ...e 5 MHz Channel spacing 25 kHz Reference frequency 6 25 kHz Figures shown in parenthesis refer to example Recommended reading 1 AN535 Phase Lock Techniques 2 AR254 Phase Locked Loop Design Articles 5 MHz VDD VDD VDD PCin C1 CTL 0 MC14568B PCout G F PE VSS VDD DP0 DP3 VCO fout DP0 DP3 C PE MC14522B 0 Q ZERO DETECT BCD BINARY CF C N1 0 5 625 kHz STEPS N2 0 9 62 5 kHz STEPS N3 0 4 8 12 6 25 kHz STEPS...

Page 508: ... 10 695 MHz RECEIVER FIRST MIXER RECEIVER SECOND MIXER MC14568B 91 1 20 2 55 MHz N 91 120 255 MHz DOWN MIXER N MC14526B MIXER OSCILLATOR TRASMIT ONLY TO TRANSMITTER 26 965 27 255 28 605 MHz 10 695 MHz RCV TRX VDD NOTE 1 10 kHz Channel Spacing 2 Expandable to 165 Channels Expanded frequency range shown in parenthesis Figure 9 Typical 23 Channel CB Frequency Synthesizer for Double Conversion Transce...

Page 509: ... Voltages Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to...

Page 510: ... Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 0 58 µA kHz f IDD IT 1 20 µA kHz f IDD IT 1 95 µA kHz f IDD µAdc Data labelled Typ is not to be u...

Page 511: ... 200 1200 500 400 ns Turn Off Delay Time Zero Detect Output tPHL 5 0 10 15 380 150 100 600 300 200 ns Q Output 5 0 10 15 530 225 155 1000 400 300 ns Clock Pulse Width tWH 5 0 10 15 300 150 115 100 45 30 ns Clock Pulse Frequency fcl 5 0 10 15 3 5 9 5 13 0 2 1 5 1 7 8 MHz Clock Pulse Rise and Fall Time tTLH tTHL 5 0 10 15 NO LIMIT µs Data labelled Typ is not to be used for design purposes but is int...

Page 512: ...ply Voltage This pin is usual ly connected to ground VDD Pin 16 Positive Supply Voltage This pin is con nected to a positive supply voltage ranging from 3 0 volts to 18 0 volts OPERATING CHARACTERISTICS The MC14569B is a programmable divide by N dual 4 bit down counter This counter may be programmed i e pre set in BCD or binary code through inputs P0 to P7 For each counter the counting sequence ma...

Page 513: ...et Inputs Divide Ratio P7 P6 P5 P4 P3 P2 P1 P0 Zero Detect Q Comments 0 0 0 0 0 0 0 0 256 256 Max Count 0 0 0 0 0 0 0 1 X X Illegal State 0 0 0 0 0 0 1 0 2 X Min Count 0 0 0 0 0 0 1 1 3 X X X X 0 0 0 0 1 1 1 1 15 X 0 0 0 1 0 0 0 0 16 X X X X 0 0 1 0 0 0 0 0 32 X X X X 0 1 0 0 0 0 0 0 64 X X X X 0 1 1 1 1 1 1 1 127 X 1 0 0 0 0 0 0 0 128 128 Q Output Active 1 0 0 0 1 0 0 0 136 136 1 1 1 1 1 1 1 1 25...

Page 514: ...Count 0 0 0 0 0 0 1 1 3 X X X X 0 0 0 0 1 0 0 1 9 X 0 0 0 1 0 0 0 0 10 X X X X 0 0 0 1 1 0 0 1 19 X 0 0 1 0 0 0 0 0 20 X X X X 0 0 1 1 0 0 0 0 30 X X X X 0 1 0 0 0 0 0 0 40 X X X X 0 1 0 1 0 0 0 0 50 X X X X 0 1 1 0 0 0 0 0 60 X X X X 0 1 1 1 0 0 0 0 70 X X X X 1 0 0 0 0 0 0 0 80 80 Q Output Active 1 0 0 1 0 0 0 0 90 90 1 1 1 1 0 0 0 0 150 150 1 1 1 1 1 0 0 1 159 159 80 40 20 10 8 4 2 1 Bit Value ...

Page 515: ...0 0 0 0 0 1 0 2 X Min Count 0 0 0 0 0 0 1 1 3 X X X X 0 0 0 0 1 1 1 1 15 X 0 0 0 1 0 0 0 0 16 X X X X 0 0 0 1 1 1 1 1 31 X 0 0 1 0 0 0 0 0 32 X X X X 0 0 1 1 0 0 0 0 48 X 0 1 0 0 0 0 0 0 64 X 0 1 0 1 0 0 0 0 80 X 0 1 1 1 0 0 0 0 112 X 1 0 0 0 0 0 0 0 128 128 Q Output Active 1 0 0 1 0 0 0 0 144 144 1 0 0 1 1 1 1 1 159 159 27 26 25 24 23 22 21 20 128 64 32 16 8 4 2 1 Bit Value Counter 2 BCD Counter ...

Page 516: ...0 1 1 3 X X X X 0 0 0 0 1 0 0 1 9 X 0 0 0 1 0 0 0 0 10 X X X X 0 0 1 1 0 0 0 0 30 X X X X 0 1 0 0 0 0 0 0 40 X X X X 0 1 0 1 0 0 0 0 50 X X X X 0 1 1 1 0 0 0 0 70 X X X X 1 0 0 0 0 0 0 0 80 80 Q Output Active 1 0 0 1 0 0 0 0 90 90 1 0 0 1 1 0 0 1 99 99 80 40 20 10 8 4 2 1 Bit Value Counter 2 BCD Counter 1 BCD Counting Sequence X No Output Always Low TIMING DIAGRAM MC14569B CLOCK 16 15 14 13 12 11 ...

Page 517: ... D PE C DP Q D PE C DP Q D PE C DP Q D PE C DP Q D PE C DP Q D PE C DP Q D PE C DP Q D PE C DP VDD 1 15 ZERO DETECT VDD D Q PE DP C D Q PE DP C D Q PE DP C D Q PE DP C IU 2 CASCADE FEEDBACK 7 3 4 5 6 9 11 14 10 12 13 CTL2 CTL1 P0 P1 P2 P3 CLOCK P4 P5 P6 P7 ...

Page 518: ...14522B OR MC14526B Q4 PE 0 Q1 C2 PE 0 MC14568B LSD MSD fout DP0 DP3 DP0 DP3 DP0 DP3 Q Figure 4 Frequency Synthesizer with MC14568B and MC14569B Using a Mixer Channel Spacing 10 kHz Frequencies shown in parenthesis are given as an example 40 kHz VSS PE DP0 DP3 PCin C1 CT1 0 PCout G F Q1 C2 VSS VSS VCO fout 144 146 MHz VDD MC14011 CF Q ZERO DETECT C CRYSTAL OSCILLATOR 2 k 2 M MIXER MC14569B 143 5 MH...

Page 519: ...oad over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Voltages Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Le...

Page 520: ... 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 0 25 0 5 1 0 0 0005 0 0010 0 0015 0 25 0 5 1 0 7 5 15 30 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 89 µA kHz f IDD IT 3 80 µA kHz f IDD IT 5 68 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes but is intended as an indication of t...

Page 521: ...00 80 ns Propagation Delay Time tPLH tPHL 1 7 ns pF CL 5 ns tPLH tPHL 0 66 ns pF CL 17 ns tPLH tPHL 0 5 ns pF CL 15 ns tPLH tPHL 5 0 10 15 90 50 40 180 100 80 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Switching Time Test Circuits and Wavef...

Page 522: ...ut Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_...

Page 523: ...001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 010 0 020 0 030 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 18 µA kHz f IDD IT 1 91 µA kHz f IDD IT 2 67 µA kHz f IDD µAdc Three State Leakage Current ITL 15 0 1 0 0001 0 1 3 0 µAdc Dat...

Page 524: ...0 10 15 0 0 0 100 50 35 ns Setup Time Address Data to Clock tsu Figure 3 5 0 10 15 50 30 25 20 0 0 ns Hold Time Clock to Address Data th Figure 3 5 0 10 15 480 195 150 160 65 50 ns 3 State Enable Disable Delay Time tPHZ tPLZ tPZH tPZL Figures 4 and 7 5 0 10 15 130 60 45 260 120 90 ns Clock Pulse Width tw Figure 3 5 0 10 15 820 330 220 410 165 110 ns When loading repetitive highs the output may gli...

Page 525: ...PETITIVE WAVEFORMS P G 1 P G 2 P G 3 OUTPUT Qn A B Figure 3 Figure 4 CLOCK ADDRESS DATA Q tw H tw L VDD VSS VDD VSS VOH VOL 50 tsu th 50 tPLH tPHL tTLH tTHL 50 90 10 3 STATE A OR B VDD VSS VOH VOL VOH VOL QA QB tPHZ 90 50 50 10 90 10 tPZL tPZH tPZL CLOCK WE tsu trem 50 50 50 50 VDD VSS VDD VSS DEVICE UNDER TEST Q CL DEVICE UNDER TEST Q CL 1 kΩ CONNECT TO VCC WHEN TESTING tPLZ AND tPZL CONNECT TO G...

Page 526: ...2 23 22 Q3A Q2A Q1A Q0A Q3B Q2B Q1B Q0B TRUTH TABLE Clock WE Write 1 Write 0 Read 1A Read 0A Read 1B Read 0B 3 State A 3 State B Dn QnA QnB 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 0 0 X X X X X X X 1 1 X No Change No Change X X X X X X X X 0 0 X Z Z 0 X X X X X X X 1 1 X No Change No Change 1 X X X X X X X 1 1 X No Change No Change 1 0 0 0 1 1 0 1 1 Dn to word 0 Contents of word 1 displayed Co...

Page 527: ... indicating equality Also when the ALU is in the subtract mode the Cn 4 output can be used to indicate relative magnitude as shown in this table Data Level Cn Cn 4 Magnitude Active High H L H L H H L L A vB A B A B A wB Active Low L H L H L L H H A vB A B A B A wB Functional and Pinout Equivalent to 74181 Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range 3 0 Vdc to 18 Vdc Ca...

Page 528: ... 8 8 0 36 0 9 2 4 mAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 8 µA kHz f IDD IT 3 7 µA kHz f IDD IT 5 5 µA kHz f IDD µAdc Data labelled Typ is not to be used for design purposes but...

Page 529: ...tPLH tPHL 1 7 ns pF CL 530 ns tPLH tPHL 0 66 ns pF CL 187 ns tPLH tPHL 0 5 ns pF CL 135 ns tPLH 5 0 10 15 615 220 160 1230 440 360 ns Carry in to Sum Out tPLH tPHL 1 7 ns pF CL 295 ns tPLH tPHL 0 66 ns pF CL 112 ns tPLH tPHL 0 5 ns pF CL 80 ns tPLH tPHL 5 0 10 15 380 145 105 760 290 210 ns Carry in to Cn 4 tPLH tPHL 1 7 ns pF CL 220 ns tPLH tPHL 0 66 ns pF CL 87 ns tPLH tPHL 0 5 ns pF CL 60 ns tPL...

Page 530: ... A B G P VDD Vout VOH IOH EXTERNAL POWER SUPPLY VSS HIGH FOR ALL OUTPUTS EXCEPT Cn 4 VDD S0 S1 S2 S3 A0 A1 A2 A3 B0 B1 B2 B3 Cn MC Cn 4 F0 F1 F2 F3 A B G P SEE AC TEST SETUP REFERENCE TABLE FOR CONNECTIONS VDD TPin PULSE GENERATOR LOAD A TPout 50 pF LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A 20 ns 20 ns VDD 0 V VOH VOL VOH VOL TPin 1 TPout 2 TPout 90 10 10 90 10 tTLH tPHL tPLH tTHL tT...

Page 531: ...S1 S0 Logic Function MC H Arithmetic Function MC L Cn L Logic Function MC H Arithmetic Function MC L Cn H L L L L A A minus 1 A A L L L H AB AB minus 1 A B A B L L H L A B AB minus 1 AB A B L L H H Logic 1 minus 1 Logic 0 minus 1 L H L L A B A plus A B AB A plus AB L H L H B AB plus A B B A B plus AB L H H L A ęB A minus B minus 1 A ęB A minus B minus 1 L H H H A B A B AB AB minus 1 H L L L AB A p...

Page 532: ... PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C LOGIC EQUATIONS Cn x G0 P0 Cn Cn y G1 P1 G0 P1 P0 Cn Cn z G2 P2 G1 P2 P1...

Page 533: ...Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 4 µA kHz f IDD IT 2 8 µA kHz f IDD IT 4 3 µA kHz f IDD µAdc Data labelled Typ is not to be used ...

Page 534: ... 0 10 15 345 140 110 690 280 220 ns The formulas given are for the typical characteristics only at 25_C Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance Figure 1 Dynamic Power Dissipation Test Circuit and Waveform 20 ns Vin VDD VSS 10 90 50 20 ns VARIABLE WIDTH Vin Cin CL VDD G0 G1 G2 G3 P0 P1 P2 P3 CL CL CL CL Cn x Cn y Cn ...

Page 535: ...Y Cn Cn Cn Cn Cn 4 G P G P G P G P G0 P0 Cn x G1 P1 Cn y G2 P2 Cn z G3 P3 G P Cn MC14582B Cn Cn Cn Cn Cn 4 G P G P G P G P G0 P0 Cn x G1 P1 Cn y G2 P2 Cn z G3 P3 G P Cn MC14582B 32 BIT ALU TWO LEVEL LOOK AHEAD OVER 16 BIT GROUPS MC14581B Cn Cn Cn Cn Cn 4 G P G P G P G P G0 P0 Cn x G1 P1 Cn y G2 P2 Cn z G3 P3 G P Cn MC14582B Cn Cn Cn G P G P G0 P0 Cn x G1 P1 Cn y Cn MC14582B COMBINED TWO LEVEL LOOK...

Page 536: ...ut Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Pack...

Page 537: ... Current Per Package IDD 5 0 10 15 0 25 0 5 1 0 0 0005 0 0010 0 0015 0 25 0 5 1 0 7 5 15 30 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 33 µA kHz f IDD IT 2 65 µA kHz f IDD IT 3 98 µA kHz f IDD µAdc Three State Leakage Current ITL 15 0 1 0 0001 0 1 3 0 µAdc Data labelled Typ is not to be used for design purposes but i...

Page 538: ...tPLH tPHL 0 5 ns pF CL 235 ns tPLH tPHL 5 0 10 15 1100 380 260 2200 760 520 ns Ain Bin to Exclusive OR tPLH tPHL 1 7 ns pF CL 665 ns tPLH tPHL 0 66 ns pF CL 257 ns tPLH tPHL 0 5 ns pF CL 145 ns tPLH tPHL 5 0 10 15 750 280 170 1500 560 340 ns 3 State Enable Disable Delay Time see figure 5 ton toff 1 7 ns pF CL 140 ns ton toff 0 66 ns pF CL 57 ns ton toff 0 5 ns pF CL 30 ns ton toff 5 0 10 15 225 90...

Page 539: ...t Bout 1 2 2 2 Aout Bout 2 1 1 1 Exclusive OR 2 1 1 1 2 2 1 Figure 2 Power Dissipation Test Circuit and Waveforms PULSE GENERATOR 1 Ain Aout PULSE GENERATOR 2 DIS Bin Aout Bout Bout VDD VSS 0 01 µF CERAMIC 500 µF CL CL CL CL CL fout Ain fout Bin ID Figure 3 Typical Threshold Points POSITIVE COMMON NEGATIVE R1 R2 POSITIVE COMMON NEGATIVE R1 A Feedback scheme for independent threshold adjustment B F...

Page 540: ...t Bout VDD CL VSS CL CL CL CL 50 tPLH 50 50 50 90 10 90 10 50 90 10 50 50 90 10 tf tr tPHL tPHL tPLH tPHL tPLH tf toff ton tPLH tPHL tr ton toff tf tr tPHL tPLH tPHL tPLH tf tr Ain Bin 3 STATE DISABLE Aout Bout Aout Bout EXCLUSIVE OR VDD VSS VDD VSS VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL NOTE Dashed lines indicate high output resistance INPUT tr tf 20 ns tr tf ...

Page 541: ...includes test circuit capacitance Test Switch Position ton HL 1 ton LH 2 toff HL 2 toff LH 1 PULSE GENERATOR 1 PULSE GENERATOR 2 VDD VDD VSS Ain DIS Bin Aout Aout Bout Bout CL 1 k 1 k 1 2 SW Ain Bin 3 STATE DISABLE Aout Bout VDD VSS VDD VSS VDD VSS VOH VOL VOH VOL 50 ton LH toff LH toff LH 10 toff HL VOL ton LH 10 90 VOH VOH 90 VOH toff LH VOL 10 VOH VOL VOL 10 VOH VOL 90 90 VOH ton HL VOH SWITCH ...

Page 542: ...Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the device may occur Temperature Derating Plastic P and D DW Packages 7 0 mW _C From 65_C To 125_C Ceramic L Packages 12 mW _C From 100_C To 125_C EQIVALENT CIRCUIT SCHEMATIC ...

Page 543: ...0 0 0005 0 0010 0 0015 0 25 0 5 1 0 7 5 15 30 µAdc Total Supply Current Dynamic plus Quiescent Per Package CL 50 pF on all outputs all buffers switching IT 5 0 10 15 IT 1 8 µA kHz f IDD IT 3 6 µA kHz f IDD IT 5 4 µA kHz f IDD µAdc Hysteresis Voltage VH 5 0 10 15 0 27 0 36 0 77 1 0 1 3 1 7 0 25 0 3 0 6 0 6 0 7 1 1 1 0 1 2 1 5 0 21 0 25 0 50 1 0 1 2 1 4 Vdc Threshold Voltage Positive Going VT 5 0 10...

Page 544: ...ntial performance Figure 1 Switching Time Test Circuit and Waveforms PULSE GENERATOR VDD INPUT CL VSS 7 OUTPUT 20 ns 20 ns VDD VSS VOH VOL 90 50 10 90 50 10 tPLH tPHL OUTPUT INPUT tf tr VDD VT VT VSS VDD VSS Vout Vin VH VH VDD VT VT VSS VDD VSS Vout Vin VDD 0 VDD VT VT 0 VH Vin INPUT VOLTAGE Vdc V out OUTPUT VOLTAGE Vdc Figure 2 Typical Schmitt Trigger Applications b A Schmitt trigger offers maxim...

Page 545: ...ges Referenced to VSS Symbol Parameter Value Unit VDD DC Supply Voltage 0 5 to 18 0 V Vin Vout Input or Output Voltage DC or Transient 0 5 to VDD 0 5 V Iin Iout Input or Output Current DC or Transient per Pin 10 mA PD Power Dissipation per Package 500 mW Tstg Storage Temperature 65 to 150 _C TL Lead Temperature 8 Second Soldering 260 _C Maximum Ratings are those values beyond which damage to the d...

Page 546: ...4 0 51 1 3 3 4 4 2 0 88 2 25 8 8 1 7 0 36 0 9 2 4 mAdc VOL 0 4 Vdc Sink VOL 0 5 Vdc VOL 1 5 Vdc IOL 5 0 10 15 0 64 1 6 4 2 0 51 1 3 3 4 0 88 2 25 8 8 0 36 0 9 2 4 mAdc Input Current Iin 15 0 1 0 00001 0 1 1 0 µAdc Input Capacitance Vin 0 Cin 5 0 7 5 pF Quiescent Current Per Package IDD 5 0 10 15 5 0 10 20 0 005 0 010 0 015 5 0 10 20 150 300 600 µAdc Total Supply Current Dynamic plus Quiescent Per ...

Page 547: ...al performance Figure 1 Dynamic Power Dissipation Signal Waveforms Figure 2 Dynamic Signal Waveforms 20 ns 20 ns 2f 1 VDD VSS VDD VSS VOH VOL VOH VOL VOH VOL A B out A B out A B out B3 A3 20 ns 20 ns VDD VSS VOH VOL 90 50 10 tPLH tPHL tTLH tTHL 90 50 10 B0 A B out A B out Inputs A B and A B high and inputs B3 A3 B2 A2 B1 A1 A0 and A B low Inputs A B and A B high and inputs B2 A2 B1 A1 B0 A0 and A ...

Page 548: ... A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS VDD VSS WORD B A WORD MC14585B MC14585B MC14585B B3 A3 B2 A2 B1 A1 B0 A0 A B A B A B INPUTS A B A B A B OUTPUT A B A B A B OUTPUTS WORD B B11 B10 B0 WORD A A11 A10 A0 15 14 2 1 7 9 10 11 5 6 4 A B in A B in A B in B0 A0 B1 A1 B2 A2 B3 A3 12 3 13 A B out A B out A B out LOGIC DIAGRAM ...

Page 549: ...Enable Diode Protection All Inputs Supply Voltage Range 3 0 Vdc to 18 Vdc Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows 1 TTL Load 4 LSTTL Loads BLOCK DIAGRAMS MC14598B MC14597B Enable Outputs 1 High Impedance 0 Dn Dn State of nth latch OUTPUT TRUTH TABLE 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 D4 D3 D2 D1 VDD D7 D6 D5 ENABLE DATA RESET D0 VSS INCREMENT STROBE FULL NC D...

Page 550: ...10 15 2 0 6 0 10 2 0 6 0 10 1 9 3 1 4 3 2 0 6 0 10 Vdc Input Voltage 0 Level Other Inputs VO 4 5 or 0 5 Vdc VO 9 0 or 1 0 Vdc VO 13 5 or 1 5 Vdc VIL 5 0 10 15 1 5 3 0 4 0 2 25 4 50 6 75 1 5 3 0 4 0 1 5 3 0 4 0 Vdc VO 0 5 or 4 5 Vdc 1 Level VO 1 0 or 9 0 Vdc VO 1 5 or 13 5 Vdc VIH 5 0 10 15 3 5 7 0 11 3 5 7 0 11 2 75 5 50 8 25 3 5 7 0 11 Vdc Output Drive Current Source Full Sink Only VOH 4 6 Vdc VO...

Page 551: ...00 100 80 400 200 160 Reset to Output 5 0 10 15 175 90 70 350 180 140 Pulse Width Enable tWH tWL 5 0 10 15 320 240 160 160 120 80 ns Strobe 5 0 10 15 200 100 80 100 50 40 Increment MC14597B only 5 0 10 15 200 100 80 100 50 40 Reset 5 0 10 15 300 160 100 150 80 50 Setup Time Data tsu 5 0 10 15 100 50 35 50 25 20 ns Address MC14598B only 5 0 10 15 200 100 70 100 50 35 Increment MC14597B only 5 0 10 ...

Page 552: ...12 D4 11 D5 10 D6 9 D7 INCREMENT 7 R CLK 3 STAGE COUNTER AND DECODER ADDITIONAL 7 LATCHES R D Q CLK MC14597B TIMING DIAGRAMS NOTES 1 High impedance output state another device controls bus 2 Reset in High state 1 4 V with VDD 5 0 V D6 INTERNAL D7 INTERNAL INCREMENT DATA STROBE FULL RESET tWL tWH 20 ns 90 10 tsu th tW 10 90 20 ns tPHL trem 50 tW Dn FULL ENABLE tTLH tTHL 90 90 10 10 tPHL tWL 1 NOTE ...

Page 553: ... D4 13 D5 12 D6 11 D7 ADDRESS DECODER ADDITIONAL 7 LATCHES A0 7 A1 8 A2 10 TO OTHER LATCHES M S B MC14598B TIMING DIAGRAM 1 4 V with VDD 5 0 V NOTES 1 High impedance output state another device controls bus 2 Output Load as for MC14597B D7 RESET A0 A1 A2 DATA STROBE ENABLE 90 10 50 50 tPHL tPLH 1 tTHL tPLH 90 10 tTLH tW 50 20 ns 90 10 tsu th th tsu 90 10 50 90 10 20 ns tW 20 ns tW ...

Page 554: ...g Motorola prod ucts are included as a means of illustration only Complete information sufficient for construction purposes may not be fully illustrated Although the information herein has been carefully checked and is believed to be reliable Motorola assumes no responsibility for inaccuracies Information here in does not convey to the purchaser any license under the patent rights of Motorola or o...

Page 555: ...CMOS Reliability 7 ...

Page 556: ...ul until the random period where λ is relatively constant In this equation λ is failures per unit of time It is usually expressed in percent failures per thousand hours Other forms include FIT Failures in Time 103 hrs x 10 4 10 9 failures per hour and MTTF Mean Time To Failure or MTBF Mean Time Between Failures both being equal to 1 λ and having units of hours Since reliability evaluations usually...

Page 557: ...2 formula to determine the failure rate at the temperature of interest Assuming T1 of 125_C at t1 of 10 000 hours a t2 of 7 8 million hours results at a T2 of 50_C If one reject results in the 10 000 device hours of testing at 125_C the failure rate at that temperature will be 0 1 1 000 hours using a 60 confidence level One reject at the equivalent 7 8 million device hours at 50_C will result in a...

Page 560: ...e IC SOIC package versus ambient temperature TA The dotted line indicates maximum allowable power dissipation derated over the ambient temperature range 25_C to 125_C Figure 9 Junction Temperature for Typical CMOS Logic Device 150 C 125 C 100 C 75 C 50 C 125 C 65 C 25 C TA AMBIENT TEMPERATURE T J JUNCTION TEMPERATURE C 500 400 300 200 100 P MAXIMUM POWER DISSIPATION PER PACKAGE mW TJ SOIC 135 C 13...

Page 561: ...Equivalent Gate Count 8 ...

Page 562: ...54 MC14015B 53 MC14512B 17 25 MC14016B 8 MC14514B 59 MC14017B 62 5 MC14515B 67 MC14018B 38 25 MC14516B 61 MC14020B 84 MC14517B 119 MC14021B 74 MC14518B 43 5 MC14023B 9 MC14519B 11 5 MC14023UB 4 5 MC14520B 43 5 MC14024B 59 MC14522B 86 MC14025B 9 MC14526B 86 MC14025UB 4 5 MC14527B 46 MC14028B 26 MC14528B 24 MC14029B 65 5 MC14530B 22 MC14034B 145 MC14531B 44 MC14035B 38 5 MC14532B 38 5 MC14040B 73 MC...

Page 563: ...Packaging Information Including Surface Mounts 9 ...

Page 564: ... DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSION F MAY NARROW TO 0 76 0 030 WHERE THE LEAD ENTERS THE CERAMIC BODY A B C 14 PL D G F N K 14 PL J M L S B M 0 25 0 010 T S A M 0 25 0 010 T T SEATING PLANE 1 7 14 9 CASE 646 06 ISSUE M 1 7 14 8 B A DIM MIN MAX MIN MAX MILLIMETERS INCHES A 0 715 0 770 18 16 ...

Page 565: ... 75 0 054 0 068 D 0 35 0 49 0 014 0 019 F 0 40 1 25 0 016 0 049 G 1 27 BSC 0 050 BSC J 0 19 0 25 0 008 0 009 K 0 10 0 25 0 004 0 009 M 0 7 0 7 P 5 80 6 20 0 228 0 244 R 0 25 0 50 0 010 0 019 _ _ _ _ CASE 620A 01 ISSUE O NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSION F MAY NARROW TO 0 76 0 030 W...

Page 566: ...95 0 305 7 50 7 74 M 0 10 0 10 S 0 020 0 040 0 51 1 01 _ _ _ _ CASE 751B 05 ISSUE J NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION 4 MAXIMUM MOLD PROTRUSION 0 15 0 006 PER SIDE 5 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 127 0 005 TOTAL IN EXCESS OF THE D DI...

Page 567: ...TERS A 2 35 2 65 A1 0 10 0 25 B 0 35 0 49 C 0 23 0 32 D 10 15 10 45 E 7 40 7 60 e 1 27 BSC H 10 05 10 55 h 0 25 0 75 L 0 50 0 90 q 0 7_ _ CASE 7O7 02 ISSUE C NOTES 1 POSITIONAL TOLERANCE OF LEADS D SHALL BE WITHIN 0 25 0 010 AT MAXIMUM MATERIAL CONDITION IN RELATION TO SEATING PLANE AND EACH OTHER 2 DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL 3 DIMENSION B DOES NOT INCLUDE MOLD FLASH 1 SEA...

Page 568: ... 08 0 200 D 0 38 0 53 0 015 0 021 G 2 54 BSC 0 100 BSC J 0 20 0 30 0 008 0 012 K 3 18 4 32 0 125 0 170 L 7 62 BSC 0 300 BSC M 0 15 0 15 N 0 51 1 02 0 020 0 040 _ _ _ _ F 1 40 1 78 0 055 0 070 REPLACES 726 04 CASE 623 05 ISSUE M NOTES 1 DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL 2 LEADS WITHIN 0 13 0 005 RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION WHEN FORMED PAR...

Page 569: ...20 0 040 _ _ _ _ 1 12 13 24 B H A F D G K SEATING PLANE N C M J L CASE 751E 04 ISSUE E NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETER 3 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION 4 MAXIMUM MOLD PROTRUSION 0 15 0 006 PER SIDE 5 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 13 0 005 TOTAL IN EXCESS OF D DIME...

Page 570: ...7 Packaging Information Including Surface Mounts 9 Equivalent Gate Count 8 Data Sheets 6 CMOS Handling and Design Guidelines 5 B and UB Series Family Data 4 The Better Program 3 Product Selection Guide 2 Master Index 1 ...

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Summary of Contents for CMOS Logic

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Motorola CMOS Logic, Manual, Page: 95 / 571

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Summary of Contents for CMOS Logic

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