Motorola CMOS Logic, Manual, Page: 459 / 571

MOTOROLA CMOS LOGIC DATA
6–421
MC14554B
EXPANSION DIAGRAM
m–Bit by n–Bit Parallel Binary Multiplier (Top View)
S = (X x Y) + K + M Where: x means Arithmetic Times.
S = (X x Y) + K + M Where: + means Arithmetic Plus.
S = S(m + n–1) S(m + n–2)
…
S2 S1 S0
X = X(m–1) X (m–2)
…
X2 X1 X0, Y = Y(n–1) Y(n–2)
…
Y2 Y1 Y0
K = K(m–1) K(m–2)
…
K2 K1 K0 and M = M(n–1) M(n–2)
…
M2 M1 M0
(Binary Numbers).
Number of output binary digits = m + n
Number of packages = mxn/4 (For m or n of both odd select next highest even number.)
Y(n–1)
M(n–2)
M(n–1) Y(n–2)
X0
X1
Y3
M2
M3 Y2
X0
X1
Y1
M0
M1 Y0
X0
X1
K0
K1
Y(n–1)
Y(n–2)
X2
X3
Y(n–2)
X(m–2)
X(m–1)
Y(n–1)
S(m + n–1) S(m + n–2) S(m + n–3) S(m+2) S(m+1) S(m)
Y3
Y2
X2
X3
Y3
Y2
X(m–2)
X(m–1)
Y1
Y0
X2
X3
K2
K3
Y1
Y0
X(m–2)
X(m–1)
K(m–2)
K(m–1)
S(m–1) S3 S1
S2 S0 S(m–2)
X AND K
Y AND M
Y1
M0
M1
C0
M2
C1
S2
VSS
VDD
Y0
X0
X1
K0
S0
K1
S1