Motorola CMOS Logic, Manual, Page: 501 / 571

MOTOROLA CMOS LOGIC DATA
6–463
MC14568B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(CL = 50 pF, TA = 25
_
C)
Characteristic Symbol
VDD
V
Min Typ Max Unit
Output Rise Time tTLH 5.0
10
15
—
—
— 180
90
65
360
180
130 ns
Output Fall Time tTHL 5.0
10
15
—
—
— 100
50
40
200
100
80
ns
Minimum Pulse Width, C1, Q1/C2, or PCin Input tWH 5.0
10
15
—
—
— 125
60
45
250
120
90
ns
Maximum Clock Rise and Fall Time,
C1, Q1/C2, or PCin Input
tTLH,
tTHL
5.0
10
15
15
15
15 —
—
— —
—
—
µ
s
PHASE COMPARATOR
Input Resistance Rin 5.0 to 15 — 106 — M
Ω
Input Sensitivity, dc Coupled — 5.0 to 15 See Input Voltage
Turn–Off Delay Time,
PCout and LD Outputs
tPHL 5.0
10
15
—
—
— 550
195
120 1100
390
240
ns
Turn–On Delay Time.
PCout and LD Outputs
tPLH 5.0
10
15
—
—
— 675
300
190 1350
600
380
ns
DIVIDE–BY–4, 16, 64 OR 100 COUNTER (D1)
Maximum Clock Pulse Frequency
Division Ratio = 4, 64 or 100
fcl
5.0
10
15
3.0
8.0
10
6.0
16
22
—
—
—
MHz
Division Ratio = 16 5.0
10
15
1.0
3.0
5 0 2.5
6.3
9.7 —
—
—
Propagation Delay Time, Q1/C2 Output
Division Ratio = 4, 64 or 100
tPLH,
tPHL
5.0
10
15
—
—
— 450
190
130 900
380
260
ns
Division Ratio = 16 5.0
10
15
—
—
— 720
300
200 1440
600
400
PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2)
Maximum Clock Pulse Frequency
(Figure 3a)
fcl 5.0
10
15
1.2
3.0
4.0 1.8
8.5
12
—
—
— MHz
Turn–On Delay Time, “0” Output
(Figure 3a)
tPLH 5.0
10
15
—
—
— 450
190
130 900
380
260 ns
Turn–Off Delay Time, “0” Output
(Figure 3a)
tPHL 5.0
10
15
—
—
— 225
85
60
450
170
150 ns
Minimum Preset Enable Pulse Width tWH(PE) 5.0
10
15
—
—
— 75
40
30 250
100
75
ns