Motorola CMOS Logic, Manual, Page: 323 / 571

MOTOROLA CMOS LOGIC DATA
6–285
MC14516B
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
L.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
M.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
TERMINAL COUNT
INDICATOR
P0 P1 P2 P3 P4 P5 P6 P7
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
+VDD +VDD
+VDD
OPEN = COUNT
CLOCK
RESET
RESISTORS = 10 k
W
0 = COUNT
1 = PRESET
1 = UP
0 = DOWN
PRESET
ENABLE