LeCroy DDA 7 Zi series, Operator'S Manual

Page: 339 / 544

Operator's Manual
WP700Zi-OM-E-RevA
338
Figure 5-12. PLL closed-loop transfer function when "PLL BW" is set to 9 kHz.
The bandwidth of any PLL is a trade-off between jitter (phase noise) and desirable properties like a wide locking
range and fast tracking. The "lock range" is the maximum frequency step for which the PLL can acquire lock
without slipping a cycle. If we set up the VCO to start at other than the correct frequency (which corresponds to a
frequency step), the PLL must change frequency to match the data. With PLL BW set to 9 kHz, the lock range is
only about 25 kHz, slightly less than 0.1% of the expected clock frequency. The pull-in range is much broader but
the pull-in time can be quite long. If we start the VCO just 0.4% away from the correct frequency, it would take
hundreds of microseconds for the PLL to lock.
Since the acquired data may be a millisecond or less in duration, extracting the clock depends critically on the
scope’s ability to determine T (1/clock frequency) from the data and on starting the PLL's VCO at that frequency
and at about the right phase. When it can do that, the VCO starts up locked and does not have to settle
noticeably. If it cannot find the frequency, the warning message: "ORDATA VCO start freq is 3.19*LP fc, didn't
find it” will be displayed. As the message says, if the scope cannot find the frequency, it starts the VCO at
3.19024 * LP fc. That ratio is 26.16/8.2 (to six significant digits). That is correct for DVD according to the
specification; however, it may not be within 0.1% for a real drive. Experience shows that drives read a couple of
percent fast.
To make the clock extraction successful, the scope must be successful in finding the starting frequency from the
data. Here are some things you should do to make this successful:
1. Capture as clean a signal as possible. Remember that a passive probe is 10 M resistive only at low
frequencies and, therefore, may significantly load a high-speed signal. A passive probe's response will roll off well
below the scope's DC 50 bandwidth. Consider using a differential probe such as the AP033 or AP034, or an
FET probe such as the AP020. Remember to attach the ground lead.
2. Equalize properly. If the signal you are probing is already equalized but not very clean, you can tell ODATA that
it is RF anyway and set the boost to zero. That way the data will be low-pass filtered, which greatly reduces noise.
If you don't equalize when you need to, or if you apply boost to an already equalized signal, the scope will
probably not be able to determine the starting VCO frequency from the data, you will see the warning described
above, and the extracted clock may not be good.
3. Sample at about 20 times the expected clock frequency. If you sample closer to 10 times the clock or below
that, the extraction algorithm may not be able to correctly separate the peaks in the width distribution to determine
the frequency at which to start the PLL. If you sample much more than 20 times the clock, the widths (in samples)