IXYS zilog Z51F6412, Manual

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Z51F6412
Product Specification
PS030302-0212 P R E L I M I N A R Y 86
11.5.2.5 Register Map
Table 11-10 Register Map
Name Address Dir Default Description
T2CR BA
H
R/W 00
H
Timer 2 Mode Control Register
T2CR1 BB
H
R/W 00
H
Timer 2 Mode Control Register 1
T2L BC
H
R 00
H
Timer 2 Low Register
PWM2LDR BC
H
R/W 00
H
PWM 2 Duty Low Register
CDR2L BC
H
R 00
H
Timer 2 Capture Data Low Register
T2H BD
H
R 00
H
Timer 2 High Register
PWM2HDR BD
H
R/W 00
H
PWM 2 Duty High Register
CDR2H BD
H
R 00
H
Timer 2 Capture Data High Register
T2DRL BE
H
W FF
H
Timer 2 Data Register Low
PWM2LPR BE
H
W FF
H
PWM 2 Period Low Register
T2DRH BF
H
W FF
H
Timer 2 Data Register High
PWM2HPR BF
H
W FF
H
PWM 2 Period High Data Register
T3CR C2
H
R/W 00
H
Timer 3 Mode Control Register
T3CR1 C3
H
R/W 00
H
Timer 3 Mode Control Register 1
T3L C4
H
R 00
H
Timer 3 Low Register
PWM3LDR C4
H
R/W 00
H
PWM 3 Duty Low Register
CDR3L C4
H
R 00
H
Timer 3 Capture Data Low Register
T3H C5
H
R 00
H
Timer 3 High Register
PWM3HDR C5
H
R/W 00
H
PWM 3 Duty High Register
CDR3H C5
H
R 00
H
Timer 3 Capture Data High Register
T3DRL C6
H
W FF
H
Timer 3 Data Register Low
PWM3LPR C6
H
W FF
H
PWM 3 Period Low Register
T3DRH C7
H
W FF
H
Timer 3 Data Register High
Source Clock
(f
SCLK
)
Duty Cycle(1+0080
H
)X500ns = 64.50us
Tx
00 01 02 03 04 7F 80 81 82 3FF 00 01 02
Tx/PWMx
POL0 = 1
Tx/PWMx
POL0 = 0
Period Cycle(1+03FF
H
)X500ns = 512us

1.95kHz
PWMxLPR(8-bit)
PWMxLDR(8-bit)
FF
H
80
H
TxCK[2:0] = 01
H
(f
PCLK
/4)
PWMxHPR = 03
H
PWMxLPR = FF
H
PWMxHDR = 00
H
PWMxLDR = 80
H
PWMxHPR(8-bit)
PWMxHDR(8-bit)
03
H
00
H
Figure 11-20 Example of PWM at 8MHz