Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
73
11.5.1.3 16 Bit Timer/Counter Mode
The timer register is being run with all 16bits. A 16-bit timer/counter register T0, T1 are incremented
from 0003H to FFFFH until it matches T0DR, T1DR and then resets to 0000H. the match output
generates the Timer 0 interrupt ( no timer 1 interrupt). The clock source is selected from T0CK[2:0]
and T1CK[1:0] must set 11b and 16BIT bit must set to ‘1’. The timer 0 is LSB 8-bit, the timer 1 is MSB
8-bit. T0DR must not be 0x00(0x01~0xFF). The 16-bit mode setting is shown as Figure 11-19.
11.5.1.4 8-Bit Capture Mode
The timer 0, 1 capture mode is set by CAP0, CAP1 as ‘1’. The clock source can use the
internal/external clock. Basically, it has the same function of the 8-bit timer/counter mode and the
interrupt occurs at T0, 1 and T0DR, T1DR matching time, respectively. The capture result is loaded
into CDR0, CDR1. The T0, T1 value is automatically cleared by hardware and restarts counter.
This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider
than the maximum period of timer.
As the EIEDGE and EIPOLA register setting, the external interrupt INT0, INT1 function is chosen.
The CDR0, T0 and T0DR are in same address. In the capture mode, reading operation is read the
CDR0, not T0DR because path is opened to the CDR0. The CDR1 has the same function.
÷4096
÷1024
÷256
P
r
e
s
c
a
l
e
r
MUX
÷2
÷4
÷16
÷64
EC0
SCLK
[B5
H
]
T0IF
Timer0
Interrup
t
16-bit Counter
16-bit Data Register
F/F
P52/T0
PIN
T0EN
Clear
[B6
H
]
Comparator
T0ST
T0CK[2:0]
3
T1
(8-bit)
T0
(8-bit)
T1DR
(8-bit)
T0DR
(8-bit)
[B3
H
]
[B3
H
]
POL1
16BIT PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
T0EN
T0PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
T1CR
T0CR
1
X
0
X X X X X
X
1
0
0
1
1
X
X
ADDRESS : B2
H
INITIAL VALUE : 0000_0000
B
ADDRESS : B4
H
INITIAL VALUE : 0000_0000
B
Figure 11-9 16 Bit Timer/Event Counter0, 1 Block Diagram
