Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
63
11.2.4 Bit Interval Timer Register description
The Bit Interval Timer Register consists of BIT Clock control register (BCCR) and Basic Interval
Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine
cycle, BCLR bit is cleared as ‘0’ automatically.
11.2.5 Register description for Bit Interval Timer
BCCR (BIT Clock Control Register) : 8BH
7
6
5
4
3
2
1
0
BITF
-
-
BCLR
BCK2
BCK1
BCK0
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial value : 05H
BITF
When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write
‘0’ to this bit.
0 no
generation
1 generation
BCLR
If BCLK Bit is written to ‘1’, BIT Counter is cleared as ‘0’
0 Free
Running
1 Clear
Counter
BCK[2:0]
Select BIT overflow period (BIT Clock
≒
3.9 KHz)
BCK2 BCK1
BCK0
0
0
0
0.512msec (BIT Clock * 2)
0 0 1
1.024msec
0 1 0
2.048msec
0 1 1
4.096msec
1 0 0
8.192msec
1 0 1
16.384msec
(default)
1 1 0
32.768msec
1 1 1
65.536msec
BITR (Basic Interval Timer Register) : 8CH
7
6
5
4
3
2
1
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R
R
R
R
R
R
R
R
Initial value : 00H
BIT[7:0]
BIT Counter
