Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
116
SPIDRx (SPI Data Register) : D3H, 93H
7
6
5
4
3
2
1
0
SPIDR7
SPIDR6
SPIDR5
SPIDR4
SPIDR3
SPIDR2
SPIDR1
SPIDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
SPIDR [7:0]
SPI data register.
Although you only use reception, user must write any data in here
to start the SPI operation.
SPISRx (SPI Status Register) : D4H, F1H
7
6
5
4
3
2
1
0
TCIR
WCOL
SS_HIGH
-
-
SSENA
TXENA
RXENA
R
R
R/W
-
-
R/W
R/W
R/W
Initial value : 00H
TCIR
When a serial data transmission is complete, the TCIR bit is set. If the
SPI interrupt is enabled, an interrupt is requested. And TCIR bit is
cleared by hardware when executing the corresponding interrupt. If SPI
interrupt is disable, TCIR bit is cleared when user read the status
register SPISR, and then access (read/write) the data register SPIDR.
0 Interrupt
cleared
1
Transmission Complete and Interrupt Requested
WCOL
This bit is set if the data register SPIDR is written during a data transfer.
This bit is cleared when user read the status register SPISR, and then
access (read/write) the data register SPIDR.
0 No
collision
1 Write
Collision
SS_HIGH
When SS pin is configured as input(master or slave), if ‘HIGH’ signal
come into SS pin, this flag bit will be set at the SS rising time. And you
can clear it by writing ‘0’.
You can write only zero.
0 Flag
is
cleared
1 Flag
is
set
SSENA
This bit controls the SS pin operation
0 Disable
1 Enable
TXENA
This bit controls a data transfer operation
0 Disable
1 Enable
RXENA
This bit controls a data reception operation
0 Disable
1 Enable
