Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
83
11.5.2 16-bit
Timer/Event Counter 2, 3, 4, 5
11.5.2.1 Overview
The 16-bit timer x(2~5) consists of Multiplexer, Timer Data Register High/Low, Timer Register
High/Low, Timer Mode Control Register, PWM Duty High/Low, PWM Period High/Low Register It is
able to use internal 16-bit timer/ counter without a port output function.
The 16-bit timer x is able to use the divided clock of the main clock selected from prescaler output.
11.5.2.2 16-Bit Timer/Counter Mode
In the 16-bit Timer/Counter Mode, If the TxH + TxL value and the TxDRH + TxDRL value are
matched, T3/PWM3 port outputs. The output is 50:50 of duty square wave, the frequency is following
)
1
(
Value
Prescaler
2
Frequency
Clock
Timer
TxDR
COMP
f
f
COMP
is timer output frequency and TxDR is the 16 bits value of TxDRH and TxDRL.
To export the compare output as Tx/PWMx, the Tx_PE bit in the TxCR1 register must set to ‘1’.
The 16-bit Timer/Counter Mode is selected by control registers as shown in Figure 11-17
Figure 11-17 Timer4 16-bit Mode Block Diagram
÷1024
÷256
÷64
P
r
e
s
c
a
l
e
r
MUX
÷1
÷4
÷8
÷16
SCLK
TxIF
Timerx
Interrupt
16-bit Timer3 Counter
16-bit Timer3 Data Register
TxEN
Clear
Comparator
TxST
TxCK[2:0]
3
TxH
(8-bit)
TxL
(8-bit)
TxDRH
(8-bit)
TxDRL
(8-bit)
-
-
-
-
-
ECEN
Tx_PE
POL
TxCR1
-
- - - - X X X
ADDRESS : BB
H,
C3
H,
CB
H,
2F39
H
INITIAL VALUE : ----_-000
B
÷2048
TxEN
PWMx
E
CAPx
TxCK2
TxCK1
TxCK0
TxCN
TxST
TxCR
1
- 0 X X X X X
ADDRESS : BA
H,
C2
H,
CA
H,
2F38
H
INITIAL VALUE : 0--0_0000
B
