Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
138
ADCRH (A/D Converter Result High Register) : 9BH
7
6
5
4
3
2
1
0
ADDM11
ADDM10
ADDM9
ADDM8
ADDM7
ADDL11
ADDM6
ADDL10
ADDM5
ADDL9
ADDM4
ADDL8
R
R
R
R
R
R
R
R
Initial value : xxH
ADDM[11:4]
MSB align, A/D Converter High result (8-bit)
ADDL[11:8]
LSB align, A/D Converter High result (4-bit)
ADCRL (A/D Converter Result Low Register) : 9CH
7
6
5
4
3
2
1
0
ADDM3
ADDL7
ADDM2
ADDL6
ADDM1
ADDL5
ADDM0
ADDL4
ADDL3
ADDL2
ADDL1
ADDL0
R
R
R
R
R
R
R
R
Initial value : xxH
ADDM[3:0]
MSB align, A/D Converter Low result (4-bit)
ADDL[7:0]
LSB align, A/D Converter Low result (8-bit)
ADCM2 (A/D Converter Mode Register) : 9BH
7
6
5
4
3
2
1
0
EXTRG
TSEL2
TSEL1
TSEL0
ADCCK2
ALIGN
CKSEL1
CKSEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 01H
EXTRG
A/D external Trigger
0 External
Trigger
disable
1 External
Trigger
enable
TSEL[2:0]
A/D Trigger Source selection
TSEL2 TSEL1 TSEL0 Description
0 0 0 Ext.
Interrupt
0
0 0 1 Ext.
Interrupt
1
0
1
0
Pin Change Interrupt 7
0
1
1
Timer0 interrupt event
1
0
0
Timer1 interrupt event
1
0
1
Timer2 interrupt event
1
1
0
Timer3 interrupt event
1
1
1
Timer4 interrupt event
ADCCK2
A/D Converter Clock selection 2
0
use SCLK(fx) as source of ADC clock selection
1
use (1/2 fx) as source of ADC clock selection with CKSEL
This bit would be needed for higher SCLK frequency than
10MHz
ALIGN
A/D Converter data align selection.
0
MSB align (ADCRH[7:0], ADCRL[7:4])
1 LSB
align
(ADCRH[3:0], ADCRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1 CKSEL0 ADC
Clock
ADC
VDD
0 0 fx/2
Test
Only
