Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
102
When the Receiver is enabled (RXE=1), the clock recovery logic tries to find a high to low transition
on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock
recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed
mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is
considered that a valid start bit is detected and the internally generated clock is synchronized to the
incoming data frame. And the data recovery can begin. The synchronization process is repeated for
each start bit.
As described above, when the Receiver clock is synchronized to the start bit, the data recovery can
begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic
samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. And
uses sample 8, 9, and 10 to decide data value for Normal mode, samples 4, 5, and 6 for Double
Speed mode. If more than 2 samples have low levels, the received bit is considered to a logic 0 and
more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery
process is then repeated until a complete frame is received including the first stop bit. The decided bit
value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit
of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find
start bit.
The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more
samples of 3 center values have high level, correct stop bit is detected, else a Frame Error flag is set.
After deciding first stop bit whether a valid stop bit is received or not, the Receiver goes idle state and
monitors the RXD line to check a valid high to low transition is detected (start bit detection).
RxD
0
0
1
2
3 4
5
6
7
8
9 10 11 12 13 14 15 16
1
2
3
IDLE
BIT0
START
0
1
2
3
4
5
6
7
8
1
2
Sample
(U2X = 0)
Sample
(U2X = 1)
Figure 11-26 Start Bit Sampling
RxD
1
2
3 4
5
6
7
8
9 10 11 12 13 14 15 16
1
BIT n
1
2
3
4
5
6
7
8
1
Sample
(U2X = 0)
Sample
(U2X = 1)
Figure 11-27 Sampling of Data and Parity Bit
