Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
46
10.5 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a
reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So
instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the
PC stack. For the interrupt service routine, the interrupt controller gives the address of LJMP
instruction to CPU. After finishing the current instruction, at the next instruction to go interrupt service
routine needs 5~8 machine cycle and the interrupt service task is terminated upon execution of an
interrupt return instruction [RETI]. After generating interrupt, to go to interrupt service routine, the
following process is progressed
Saves PC value in order to continue
process again after executing ISR
IE.EA Flag
1
IEx.y
1
1
Program Counter low Byte
SP
SP + 1
M(SP)
(PCL)
2
Program Counter high Byte
SP
SP + 1
M(SP)
(PCH)
3
Interrupt Vector Address occurrence
(Interrupt Vector Address)
4
ISR(Interrupt Service Routine) move, execute
5
Return from ISR
RETI
6
Program Counter high Byte recovery
(PCL)
(SP+1)
7
Main Program execution
9
Program Counter low Byte recovery
(PCL)
(SP-1)
8
Figure 10-3 Interrupt Vector Address Table
