IXYS zilog Z51F6412 Manual Download Page 122

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Z51F6412

Product Specification

PS030302-0212

P R E L I M I N A R Y

119

11.9.6 Acknowledge

The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA

line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit

because it’s performing some real time function, the data line must be left HIGH by the slave. And

also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must

release the SDA line (Data Packet). The master can then generate either a STOP condition to abort

the transfer, or a repeated START condition to start a new transfer.

If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by

not generating an acknowledge on the last byte that was clocked out of the slave. The slave

transmitter must release the data line to allow the master to generate a STOP or repeated START

condition.

11.9.7 Synchronization / Arbitration

Clock synchronization is performed using the wired-AND connection of I

C interfaces to the SCL

line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to

start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state

is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL

line if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated

Data Output

By Transmitter

ACK

NACK

Clock pulse for ACK

Data Output

By Receiver

SCL From MASTER

START or Repeated

START Condition

STOP or Repeated

START Condition

MSB

Acknowledgement

Signal form Slave

Acknowledgement

Signal form Slave

Byte Complete,

Interrupt within Device

Clock line held low while

interrupts are served.

ACK

SDA

SCL

Figure 11-37 Data Transfer on the I

C-Bus

Figure 11-38 Acknowledge on the I

C-Bus

Summary of Contents for zilog Z51F6412

Page 2: ...ure to perform can be reason ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Document Disclaimer 2012 Zilog Inc All rights reserved Inf...

Page 3: ...this document s revision history reflects a change from its previous edi tion For more details refer to the corresponding page s or appropriate links furnished in the table below Date Revision Level D...

Page 4: ...cs 24 7 5 Power On Reset Characteristics 25 7 6 Brown Out Detector Characteristics 25 7 7 Internal RC Oscillator Characteristics 25 7 8 Ring Oscillator Characteristics 26 7 9 PLL Characteristics 26 7...

Page 5: ...Peripheral Operation in IDLE STOP Mode 145 12 3 IDLE mode 146 12 4 STOP mode 147 12 5 Release Operation of STOP1 2 Mode 148 13 RESET 150 13 1 Overview 150 13 2 Reset source 150 13 3 Block Diagram 150...

Page 6: ...7 Correspondence between vector Table address and the entry address of ISP 49 Figure 10 8 Saving Restore Process Diagram Sample Source 49 Figure 10 9 Timing chart of Interrupt Acceptance and Interrup...

Page 7: ...re of Two Masters 120 Figure 11 41 Formats and States in the Master Transmitter Mode 123 Figure 11 42 Formats and States in the Master Receiver Mode 125 Figure 11 43 Formats and States in the Slave Tr...

Page 8: ...on 161 Figure 14 6 Acknowledge on the serial bus 161 Figure 14 7 Clock synchronization during wait procedure 162 Figure 14 8 Connection of transmission 162 Figure 15 1 Flash Memory Map 167 Figure 15 2...

Page 9: ...42 Table 10 2 Interrupt Vector Address Table 45 Table 10 3 Register Map 52 Table 11 1 Register Map 59 Table 11 2 VDC current consumption 61 Table 11 3 Register Map 62 Table 11 4 Register Map 64 Table...

Page 10: ...51F6412 Product Specification PS030302 0212 P R E L I M I N A R Y 7 Table 15 3 Operation Mode 173 Table 15 4 The selection of memory type by ADDRH 7 4 174 Table 15 5 Security policy using lock bits 17...

Page 11: ...ircuitry The Z51F6412 MCU also supports power saving modes to reduce power consumption Device Name Flash XRAM SRAM ADC Package Z51F6412ATX 64KB 3KB 256 bytes 15 channel 80 pin LQFP Z51F6412ARX 64 pin...

Page 12: ...tion Execution Time 125ns 16MHz NOP Instruction Power down mode IDLE STOP1 STOP2 mode Sub Active mode System used external 32 768KHz crystal Operating Frequency 1MHz 10MHz crystal oscillator 2 4 8 16M...

Page 13: ...e Flash Memory Size 64 64 KB Flash Flash Memory F General Purpose Flash Device Family Z51 Z8051 8 Bit Core MCU 1 4 Development Tools 1 4 1 Compiler We do not provide the compiler Please contact third...

Page 14: ...e OCD Debugger program works on Microsoft Windows NT 2000 XP Vista 32bit operating system If you want to see more details please refer OCD debugger manual You can download debugger S W and manual from...

Page 15: ...mer OCD emulator It can write code in MCU device too Because of OCD debugging supports ISP In System Programming It does not require additional H W except developer s target system Gang programmer It...

Page 16: ...PWM4 P57 T5 PWM5 SPI0 P37 MISO0 P36 MOSI0 P35 SCK0 P34 SSS0 I2C P07 SDA P06 SCL P07 P00 SUBXIN P04 SUBXOUT P05 XIN P62 XOUT P63 nRESET VDD VSS USART0 P03 RxD0 P02 TxD0 P01 ACK0 P00 USS0 P50 BUZ BUZZER...

Page 17: ...50 55 53 52 51 54 45 49 48 47 46 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 nTEST VDD18 DSCL DSDA LPF VDD P63 XOUT VSS P62 XIN P66 P67 P65 EC5 nRESET P64 EC4 P60 EC2 P61 EC3 P56 T4 PW...

Page 18: ...7 28 29 P31 ACK1 AN9 P30 USS1 AN8 30 31 P33 RxD1 AN11 P32 TxD1 AN10 32 48 47 46 45 44 43 41 42 37 40 39 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nTEST VDD18 DSCL DSDA LPF VDD P63 XOUT VSS nR...

Page 19: ...Z51F6412 Product Specification PS030302 0212 P R E L I M I N A R Y 16 4 Package Diagram Figure 4 1 80 pin LQFP package...

Page 20: ...Z51F6412 Product Specification PS030302 0212 P R E L I M I N A R Y 17 Figure 4 2 64 pin LQFP package...

Page 21: ...e register can be used via software when this port is used as output port Input INT0 P11 INT1 P12 INT2 P13 INT3 P14 INT4 P15 INT5 P16 INT6 P17 INT7 P20 I O Port P2 8 Bit I O Port Can be set in input o...

Page 22: ...er can be used via software when this port is used as output port Input BUZ P51 EC0 P52 T0 P53 T1 PWM1 P54 T2 PWM2 P55 T3 PWM3 P56 T4 PWM4 P57 T5 PWM5 P60 I O Port P6 6 Bit I O Port Can be set in inpu...

Page 23: ...filter for PLL If it doesn t use PLL it doesn t need filter circuit and it connects to GND Analog nRESET I Input XOUT O Main Oscillator output XIN I Main Oscillator input VSS P Ground VDD P Power SUB...

Page 24: ...FUNC ENABLE LevelShift 1 8V to ExtVDD LevelShift ExtVDD to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r...

Page 25: ...D LevelShift ExtVDD to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE...

Page 26: ...cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specificati...

Page 27: ...VSS AVDD VDD V Analog Power Voltage AVDD AVDD VDD V Analog Reference Voltage AVREF 2 7 5 5 V Analog Ground Voltage AVSS VSS V Analog Input Leakage Current AVDD VDD 5 12V 10 uA ADC Operating Current ID...

Page 28: ...stics Table 7 6 Brown Out Detector Characteristics Parameter Symbol Condition MIN TYP MAX Unit Operating Voltage VSS 5 5 V Operating Temperature 40 85 Detection Level 4 2V 4 0 4 4 V 3 6V 3 4 3 8 V 2 5...

Page 29: ...P MAX Unit Operating Voltage 1 8 5 5 V Operating Temperature 40 85 Frequency 1 MHz Stabilization Time mS Operating Current IDD uA SIDD 1 uA 7 9 PLL Characteristics Table 7 9 PLL Characteristics Parame...

Page 30: ...OH1 ALL I O IOH 8 57mA VDD 4 5V 3 5 V Input High Leakage Current IIH ALL PAD 1 uA Input Low Leakage Current IIL ALL PAD 1 uA Pull Up Resister RPU ALL PAD except DSCL DSDA 20 50 k Power Supply Current...

Page 31: ...tCPW XIN 90 ns External Clock Transition Time tRCP tFCP XIN 10 ns Interrupt Input Width tIW INT0 INTx 2 tSYS External Interrupt Transition Time tFI tRI INT0 INTx 1 us nRESET Input Pulse L Width tRST n...

Page 32: ...Output Clock H or L Pulse Width tSCKL tSCKH SCK tSYS 30 ns Output Clock Pulse Transition Time tFSCK tRSCK SCK 30 ns First Output Clock Delays Time tFOD OUTPUT Output Clock Delay Time tDS OUTPUT 100 n...

Page 33: ...ented are outside specified operating range e g outside specified VDD range This is for information only and devices are guaranteed to operate properly only within the specified range The data present...

Page 34: ...4K bytes for one bank of memory space Figure 8 1 shows a map of the lower part of the program memory After reset the CPU begins execution from location 0000H Each interrupt is assigned a fixed locatio...

Page 35: ...owest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Status Word select which register bank is in use This allo...

Page 36: ...4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F R5 R4 R3 R2 R1 R0 R6 R7 2FH Register bank 0...

Page 37: ...PU P3PU P4PU P5PU P6PU P7PU 34 F8H IP1 UCTRL11 UCTRL12 UCTRL13 USTAT1 UBAUD1 UDATA1 F0H B SPISR1 FEARH FEARM FEARL FEDR FECR CAL_CNTR E8H FEMR FESR FETCR CAL_ADDR CAL_DATA E0H ACC UCTRL01 UCTRL02 UCTR...

Page 38: ...nter 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Low Byte 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W Initial value 00H DPL D...

Page 39: ...r Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set cleared by hardware each instruction cycle to indicate an odd e...

Page 40: ...leared by a system reset 9 2 3 Pull up Resistor Selection Register PxPU The on chip pull up resistor can be connected to them in 1 bit units with a pull up resistor selection register PxPU The pull up...

Page 41: ...ter P1DB 2F19H R W 00H P1 Debounce Enable Register P2 90H R W 00H P2 Data Register P2IO 99H R W 00H P2 Direction Register P2PU 2F02H R W 00H P2 Pull up Resistor Selection Register P2OD 2F0EH R W 00H P...

Page 42: ...gister 0 PSR1 2F51H R W 00H Port Selection Register 1 9 3 Px Port 9 3 1 Px Port Description Px ports are 8 bit General purpose I O ports except P8 Px control registers consist of Data register Px dire...

Page 43: ...used PxOD Px Open drain Selection Register 2F0CH 2F14H 7 6 5 4 3 2 1 0 Px7OD Px6OD Px5OD Px4OD Px3OD Px2OD Px1OD Px0OD R W R W R W R W R W R W R W R W Initial value 00H PxOD 7 0 Configure open drain o...

Page 44: ...R W R W R W R W R W R W R W R W Initial value 00H PCI7 7 0 Configure Pin Change Interrupt of P7port 0 Disable 1 Enable PSR0 Port Selection Register 0 92H 7 6 5 4 3 2 1 0 PSR07 PSR06 PSR05 PSR04 PSR03...

Page 45: ...is set to 0 all interrupts are disabled when EA is set to 1 interrupts are individually enabled or disabled through the other bits of the interrupt enable registers The Z51F6412 MCU supports a four le...

Page 46: ...POLA External Interrupt Polarity register as shown in Figure 10 1 Also each external interrupt source has control setting bits The EIFLAG External interrupt flag register register provides the status...

Page 47: ...1 2 3 4 5 6 7 8 9 10 11 30 31 IE1 A9H IE5 ADH IP B8H IP1 F8H EIFLAG 0 A4H Release Stop Sleep FLAG0 FLAG1 FLAG2 FLAG3 INT5 IIF RXC1 TXC1 RXC TXC TCIR EA IE 7 A8H PCI P0 I2C USART1 Rx USART1 Tx INT6 EIF...

Page 48: ...4 11 Maskable 0053H USART1 Tx INT11 IE1 5 12 Maskable 005BH T0 INT12 IE2 0 13 Maskable 0063H T1 INT13 IE2 1 14 Maskable 006BH T2 INT14 IE2 2 15 Maskable 0073H T3 INT15 IE2 3 16 Maskable 007BH T4 INT16...

Page 49: ...at the next instruction to go interrupt service routine needs 5 8 machine cycle and the interrupt service task is terminated upon execution of an interrupt return instruction RETI After generating int...

Page 50: ...g after Controlling Interrupt bit EA INTnE set Next Instruction Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes the pending interrupt active after executing the ne...

Page 51: ...Following example is shown to service INT0 routine during INT1 routine in Figure 10 5 In this example INT0 interrupt priority is higher than INT1 interrupt priority If some interrupt is lower than INT...

Page 52: ...Interrupt Routine Figure 10 6 Interrupt Response Timing Diagram 01H 25H 00B3H 00B4H Basic Interval Timer Vector Table Address 0EH 2EH 0125H 0126H Basic Interval Timer Service Routine Address Figure 10...

Page 53: ...ore makes interrupt acknowledge at first cycle of command executes long call to jump interrupt routine as INT_VEC Note command cycle C P L Last cycle 1 1st cycle or 1st phase 2 2nd cycle or 2nd phase...

Page 54: ...The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a 0 to it 10 12 4 External Interrupt Edge Register EIEDGE The External interrupt edge regist...

Page 55: ...for controlling interrupt functions Also it has External interrupt control registers The interrupt register consists of Interrupt Enable Register IE Interrupt Enable Register 1 IE1 Interrupt Enable R...

Page 56: ...Enable or disable USART1 Rx Interrupt 0 Disable 1 Enable INT9E Enable or disable I2C Interrupt 0 Disable 1 Enable INT8E Enable or disable SPI0 Interrupt 0 Disable 1 Enable INT7E Enable or disable USAR...

Page 57: ...0 Disable 1 Enable INT22E Enable or disable BIT Interrupt 0 Disable 1 Enable INT21E Enable or disable WDT Interrupt 0 Disable 1 Enable INT20E Enable or disable WT Interrupt 0 Disable 1 Enable INT19E E...

Page 58: ...al value 00H INT35E Reserved 0 Disable 1 Enable INT34E Reserved 0 Disable 1 Enable INT33E Reserved 0 Disable 1 Enable INT32E Reserved 0 Disable 1 Enable INT31E Enable or disable External Interrupt 7 0...

Page 59: ...which type of edge or level sensitive interrupt may occ ur 0 Level default 1 Edge EIPOLA External Interrupt Polarity Register A6H 7 6 5 4 3 2 1 0 POLA7 POLA6 POLA5 POLA4 POLA3 POLA2 POLA1 POLA0 R W R...

Page 60: ...r EIEDGE EIPOLA if EIBOTH is enable EIEDGE and EIPOLA r egister value don t matter 0 Disable default 1 Enable EIENAB External Interrupt Enable Register A3H 7 6 5 4 3 2 1 0 ENAB7 ENAB6 ENAB5 ENAB4 ENAB...

Page 61: ...l into the XIN pin and open the XOUT pin The default system clock is INT RC Oscillator and the default division rate is two In order to stabilize system internally use 1MHz RING oscillator for BIT WDT...

Page 62: ...etermine division rate Note when using fINTRC as system clock only division rate come into effect Note To change by software CBYS set to 1 DIV1 DIV0 description 0 0 fINTRC 1 16MHz 0 1 fINTRC 2 8MHz de...

Page 63: ...ase of PLLCKS is 0 32KHz In addition this bit automatically set by interrupt event on sub active or power down 0 PLL output is Fvcoin 32 768KHz bypass default 1 PLL output is Fpll VDConSUB Normal Powe...

Page 64: ...and has only 1mA current capability while main VDC for normal operation is off Second if user wanted to use 32 768KHz on PLL enable CS 1 0 0x2 of SCCR PLLCKS 0 and PLLEN 1 of PLLCR in this case PLL V...

Page 65: ...During Power On BIT gives a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As clock function time interrupt occurrence 11 2 2 Block Diagram 11 2 3 Register...

Page 66: ...0 BITF BCLR BCK2 BCK1 BCK0 R W R R R R W R W R W R W Initial value 05H BITF When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit 0 no generation 1 generation BCLR If BCLK...

Page 67: ...onsists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equal to the 8 bits of WDTR the interrupt request flag is generated This can be used as W...

Page 68: ...rantee proper operation the data should be greater than 01H WDTCR Watch Dog Timer Counter Register Read Case 8EH 7 6 5 4 3 2 1 0 WDTCR7 WDTCR6 WDTCR5 WDTCR4 WDTCR3 WDTCR2 WDTCR1 WDTCR0 R R R R R R R R...

Page 69: ...I M I N A R Y 66 11 3 6 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCR 7 0 WDTR 7 0 WDTIF Interrupt WDTRESETB WDTCL Occur WDTR 0000_0011b Match Detect Counter Clear RESET 0 1 2 3 0 1 2...

Page 70: ...nter circuits may be composed of 21 bit counter which is low 14 bit with binary counter and high 7 bit with auto reload counter in order to raise resolution In WTR it can control WT clear and set Inte...

Page 71: ...er Mode Register 9DH 7 6 5 4 3 2 1 0 WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 R W R W R W R W R W R W Initial value 00H WTEN Control Watch Timer 0 disable 1 enable WTIFR When WT Interrupt occurs this bit be...

Page 72: ...value 7FH WTCL Clear WT Counter 0 Free Run 1 Clear WT Counter auto clear after 1 Cycle WTR 6 0 Set WT period WT Interrupt Interval fwck 2 14 x 7bit WT Value 1 Note To guarantee proper operation it is...

Page 73: ...nternal or external clock source external EC0 The clock source is selected by clock select logic which is controlled by the clock select T0CK 2 0 T1CK 1 0 TIMER0 clock source fX 2 4 16 64 256 1024 409...

Page 74: ...of timer P2 3 occurs The external clock EC0 counts up the timer at the rising edge If EC0 is selected from T0CK 2 0 EC0 port becomes input port The timer 1 can t use the external EC0 clock 4096 1024 2...

Page 75: ...tch with T0DR T1DR Occur Interrupt Occur Interrupt Occur Interrupt Figure 11 7 Timer Event Counter0 1 Example T0DR T1DR Value TIME STOP Timer 0 1 T0IF T1IF Interrupt Occur Interrupt Occur Interrupt Cl...

Page 76: ...atching time respectively The capture result is loaded into CDR0 CDR1 The T0 T1 value is automatically cleared by hardware and restarts counter This timer interrupt in capture mode is very useful when...

Page 77: ...F INT1 Interrupt 8 bit Timer1 Counter T1 8Bit 8 bit Timer1 Data Register T1CN Clear B6H T1ST INT1 EIEDGE 1 POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST T1CR T...

Page 78: ...nterval Period 0 Count Pulse Period PCP Up count CDR0 CDR1 Load Ext INT0 1PIN Figure 11 11 Input Capture Mode Operation of Timer 0 1 T0 T1 Interrupt Request INT0F INT1F XXH Interrupt Interval Period F...

Page 79: ...period of the PWM output is determined by the T1PPR PWM period register T1PWHR 3 2 T1PWHR 1 0 PWM Period T1PWHR 3 2 T1PPR X Source Clock PWM Duty T1PWHR 1 0 T1PDR X Source Clock Note T1PPR must be set...

Page 80: ...determined by the bit POL 1 High 0 Low And if the duty value is set to 00H the PWM output is determined by the bit POL 1 Low 0 High P r e s c a l e r MUX T0 Clock Source fx T1CN T1ST T1CK 1 0 2 1 2 1...

Page 81: ...H fXIN T1PWHR 03H T1PPR FFH T1PDR 80H Figure 11 15 Example of PWM at 4MHz T3 00 01 02 03 04 T1 PWM1 POL 1 T1CR 1 0 10H 2us T1PWHR 00H T1PPR 0EH T1PDR 05H 09 08 07 06 05 0D 0C 0B 0A 02 01 00 0E 06 05 0...

Page 82: ...W FFH Timer 1 PWM Period Register T1 B6 R 00H Timer 1 Register T1PDR B6 R W 00H Timer 1 PWM Duty Register CDR1 B6 R 00H Capture 1 Data Register T1PWHR B7 W 00H Timer 1 PWM High Register 11 5 1 9 Timer...

Page 83: ...096 1 1 1 External Clock EC0 T0CN Control Timer 0 Count pause continue 0 Temporary count stop 1 Continue count T0ST Control Timer 0 start stop 0 Counter stop 1 Clear counter and start T0 Timer 0 Regis...

Page 84: ...ect clock source of Timer 1 Fx is the frequency of main system T1CK1 T1CK0 description 0 0 fx 0 1 fx 2 1 0 fx 16 1 1 Use Timer 0 Clock T1CN Control Timer 1 Count pause continue 0 Temporary count stop...

Page 85: ...y write when PWM3E 1 CDR1 Capture 1 Data Register Read Case B6H 7 6 5 4 3 2 1 0 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10 R R R R R R R R Initial value 00H CDR3 7 0 T1 Capture data T1PWHR Timer...

Page 86: ...tputs The output is 50 50 of duty square wave the frequency is following 1 Value Prescaler 2 Frequency Clock Timer TxDR COMP f fCOMP is timer output frequency and TxDR is the 16 bits value of TxDRH an...

Page 87: ...riting operation The PWMxLDR TxL CDRxL has the same function P R E S C A L E R 1 4 8 16 64 256 1024 2048 MUX TxH 8 bit TxL 8 bit 16 bit Counter TxST TxEN 4 ECTN TxCK 2 0 SCLK INTx EIEDGE 5 2 clear INT...

Page 88: ...he period value the PWM output is determined by the bit POL 1 High 0 Low And if the duty value is set to 00H the PWM output is determined by the bit POL 1 Low 0 High P R E S C A L E R 1 4 8 16 64 256...

Page 89: ...M 2 Period High Data Register T3CR C2H R W 00H Timer 3 Mode Control Register T3CR1 C3H R W 00H Timer 3 Mode Control Register 1 T3L C4H R 00H Timer 3 Low Register PWM3LDR C4H R W 00H PWM 3 Duty Low Reg...

Page 90: ...ture Data Low Register T5H 2F3BH R 00H Timer 5 High Register PWM5HDR 2F3BH R W 00H PWM 5 Duty High Register CDR5H 2F3BH R 00H Timer 5 Capture Data High Register T5DRL 2F3CH W FFH Timer 5 Data Register...

Page 91: ...Timer X Fx is the frequency of main system TxCK2 TxCK1 TxCK0 description 0 0 0 fSCLK 0 0 1 fSCLK 4 0 1 0 fSCLK 8 0 1 1 fSCLK 16 1 0 0 fSCLK 64 1 0 1 fSCLK 256 1 1 0 fSCLK 1024 1 1 1 fSCLK 2048 TxCN C...

Page 92: ...DRxL 7 0 Tx Capture Low data PWM2LDR PWM3LDR PWM4LDR PWM5LDR PWM 2 5 Low Duty Register Write Case BCH C4H CCH 2F3AH 7 6 5 4 3 2 1 0 PWMxLD7 PWMxLD6 PWMxLD5 PWMxLD4 PWMxLD3 PWMxLD2 PWMxLD1 PWMxLD0 W W...

Page 93: ...PWM2LPR PWM3LPR PWM4LPR PWM5LPR PWM 2 5 Low Period Register Write Case BEH C6H CEH 2F3CH 7 6 5 4 3 2 1 0 PWMxLP7 PWMxLP6 PWMxLP5 PWMxLP4 PWMxLP3 PWMxLP2 PWMxLP1 PWMxLP0 W W W W W W W W Initial value...

Page 94: ...ite 1 to clear interrupt flag TMIF3 Timer 3 Interrupt Flag 0 No Timer 3 interrupt 1 Timer 3 interrupt occurred write 1 to clear interrupt flag TMIF2 Timer 2 Interrupt Flag 0 No Timer 2 interrupt 1 Tim...

Page 95: ...equency at 16MHz BUZDR 7 0 Buzzer Frequency kHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 250kHz 125kHz 62 5kHz 31 25kHz 0000_0001 125kHz 62 5kHz 31 25kHz 15 624kHz 1111_1101 984 2...

Page 96: ...r Buzzer Driver BUZDR Buzzer Data Register 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the...

Page 97: ...ta Register Empty and RX Complete Double Speed Asynchronous Communication Mode USART has three main parts of Clock Generator Transmitter and Receiver The Clock Generation logic consists of synchroniza...

Page 98: ...MSEL1 UMSEL0 UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRLx1 ADDRESS E2H FAH 2F28H 2F30H INITIAL VALUE 0000_0000B UDRIE TXCIE RXCIE WAKEIE TXE RXE USARTEN U2X UCTRLx2 ADDRESS E3H FBH 2F29H 2F31H INITIAL...

Page 99: ...U2X bit in the UCTRLx2 register The MASTER bit in UCTRLx2 register controls whether the clock source is internal Master mode output port or external Slave mode input port The XCK pin is only active w...

Page 100: ...and fSCLK is the frequency of main system clock SCLK 11 7 5 Synchronous mode Operation When synchronous or spi mode is used the XCK pin will be used as either clock input slave or clock output master...

Page 101: ...s transmitted it can be directly followed by a new frame or the communication line can be set to an idle state The idle means high state of data pin The next figure shows the possible combinations of...

Page 102: ...e frame at the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode USIZE 2 0 7 the ninth bit must be written to the TX8 bit in UCTRLx3 register...

Page 103: ...t LOW on RXD pin Each bit after start bit is sampled at pre defined baud rate asynchronous or sampling edge of XCK synchronous and shifted into the receive shift register until the first stop bit of a...

Page 104: ...bled UPM 1 0 the PE bit is always read zero Note The error flags related to receive operation are not used when USART is in spi mode 11 7 9 3 Parity Checker If Parity Bit is enabled UPM 1 1 the Parity...

Page 105: ...s 4 5 and 6 for Double Speed mode If more than 2 samples have low levels the received bit is considered to a logic 0 and more than 2 samples have high levels the received bit is considered to a logic...

Page 106: ...mats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers the USART has a clock polarity bit UCPOL and a clock phase control bit UCPHA to select one...

Page 107: ...cond XCK edge the USART shifts the second data bit value out to the MOSI and MISO outputs of the master and slave respectively Unlike the case of UCPHA 1 when UCPHA 0 the slave s SS input must go to i...

Page 108: ...s similar to that of synchronous or asynchronous operation An SPI transfer is initiated by checking for the USART Data Register Empty flag UDRE 1 and then writing a byte of data to the UDATA Register...

Page 109: ...D3 2F34H R W FFH USART Baud Rate Generation Register 3 UDATA3 2F35H R W 00H USART Data Register 3 11 7 12 USART Register description USART module consists of USART Control 1 Register UCTRLx1 USART Con...

Page 110: ...preparing transmit data UCPOL UCPHA Leading Edge Trailing Edge 0 0 Sample Rising Setup Falling 0 1 Setup Rising Sample Falling 1 0 Sample Falling Setup Rising 1 1 Setup Falling Sample Rising UCTRLx2...

Page 111: ...operation 1 Loop Back mode DISXCK In Synchronous mode of operation selects the waveform of XCK output 0 XCK is free running while USART is enabled in synchronous master mode 1 XCK is active while any...

Page 112: ...when in asynchronous mode of operation 0 No WAKE interrupt is generated 1 WAKE interrupt is generated SOFTRST This is an internal reset and only has effect on USART Writing 1 to this bit initializes t...

Page 113: ...The USART Transmit Buffer and Receive Buffer share the same I O address with this DATA register The Transmit Data Buffer is the destination for data written to the UDATA register Reading the UDATA re...

Page 114: ...0 51 0 2 103 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5...

Page 115: ...phase and whether LSB first data transfer or MSB first data transfer 11 8 2 Block Diagram 64 32 P r e s c a l e r MUX 2 4 8 16 fSCLK PxDA x SPICR 2 0 3 MUX Edge Detector SPI Control Circuit WCOL TCIR...

Page 116: ...user want to use only either transmit or receive clear the TXENA or RXENA In this case user can use disabled pin by GPIO freely 11 8 4 SS pin function 1 When the SPI is configured as a Slave the SS pi...

Page 117: ...0 SPICR1 92H R W 0H SPI Control Register 1 SPIDR1 93H R W 0H SPI Data Register 1 SPISR1 F1H 0H SPI Status Register 1 SCKx CPOL 0 SCKx CPOL 1 SSx TCIR MISOx MOSIx Output D0 D1 D2 D3 D4 D5 D6 D7 MOSxI...

Page 118: ...ster or Slave mode 0 Slave mode 1 Master mode CPOL CPHA These two bits control the serial clock SCK mode Clock Polarity CPOL bit determine SCK s value at idle mode Clock Phase CPHA bit determine if da...

Page 119: ...rupt If SPI interrupt is disable TCIR bit is cleared when user read the status register SPISR and then access read write the data register SPIDR 0 Interrupt cleared 1 Transmission Complete and Interru...

Page 120: ...2 Block Diagram 11 9 3 I2 C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock SCL The HIGH or LOW state of the data line can only change when the clock signal on the...

Page 121: ...STOP condition If a repeated START condition Sr is generated instead of STOP condition the bus stays busy So the START and repeated START conditions are functionally identical 11 9 5 Data Transfer Ev...

Page 122: ...edge on the last byte that was clocked out of the slave The slave transmitter must release the data line to allow the master to generate a STOP or repeated START condition 11 9 7 Synchronization Arbit...

Page 123: ...ship of I2 C bus Its first stage is comparison of the address bits 11 9 8 Operation The I2 C is byte oriented and interrupt based Interrupts are issued after all bus events except for a transmission o...

Page 124: ...rship during arbitration process the MLOST bit in I2CSR is set and I2 C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLSOT bit in I2CSR is set the ACKEN b...

Page 125: ...n this case load SLA R W into the I2CDR and set the START bit in I2CMR After doing one of the actions above write arbitrary value to I2CSR to release SCL line In case of 1 move to step 7 In case of 2...

Page 126: ...Register ACK Interrupt SCL line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other master continues Slave Receiver 0x1D or Transmitter 0x1F Master...

Page 127: ...r or a slave receiver go to appropriate section In this stage I 2 C holds the SCL LOW This is because to decide whether I2 C continues serial transfer or stops communication The following steps contin...

Page 128: ...that data transfer between master and slave is over To clear I2CSR write arbitrary value to I2CSR After this I2 C enters idle state The processes described above for master receiver operation of I2C c...

Page 129: ...another START condition Else if the address equals to SLA bits and the ACKEN bit is enabled I2 C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits...

Page 130: ...r Y 0x47 ACK STOP Y N 0x46 P 0x22 IDLE IDLE Y GCALL 0x1F 0x97 0x17 From master to slave Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt SCL line is held l...

Page 131: ...bits and the ACKEN bit is enabled I2 C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN bit is disabled I2 C enters idle state Whe...

Page 132: ...ster I2CDR DFH R W FFH I2 C Data Register I2CSAR D7H R W 00H I 2 C Slave Address Register I2CSAR1 D6H R W 00H I2 C Slave Address Register 1 SLA W ACK DATA LOST S or Sr Y N 0x45 ACK STOP Y N 0x44 P 0x2...

Page 133: ...0 I2 C is inactive 1 I2 C is active RESET Initialize internal registers of I 2 C 0 No operation 1 Initialize I 2 C auto cleared INTEN Enable interrupt generation of I 2 C 0 Disable interrupt operates...

Page 134: ...OP condition is detected Note 1 0 No STOP condition is detected 1 STOP condition is detected SSEL This bit is set when I2 C is addressed by other master Note 1 0 I 2 C is not selected as slave 1 I 2 C...

Page 135: ...operating frequency of I2 C in master mode fI2C is calculated by the following equation fI2C 1 tSCLK 4 SCLL SCLH 4 I2CSDAHR SDA Hold Time Register DEH 7 6 5 4 3 2 1 0 SDAH7 SDAH6 SDAH5 SDAH4 SDAH3 SDA...

Page 136: ...ther I2 C allows general call address or not when I2 C operates in slave mode 0 Ignore general call address 1 Allow general call address I2CSAR1 I2C Slave Address Register 1 D6H 7 6 5 4 3 2 1 0 SLA7 S...

Page 137: ...e register ADCHR and ADCLR contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCHR and ADCLR the A D conversion status bit AFLAG is set to 1 and...

Page 138: ...bit set 0 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRH 7 0 ADCRL 7 4 ADCRL 3 0 b...

Page 139: ...erter Mode Register ADCM A D Converter Result High Register ADCRH A D Converter Result Low Register ADCRL A D Converter Mode 2 Register ADCM2 Note when STBY bit is set to 1 ADCM2 can be read If ADC en...

Page 140: ...sion Start REFSEL A D Converter reference selection 0 Internal Reference VDD 1 External Reference AVREF AN0 disable AFLAG A D Converter operation state 0 During A D Conversion 1 A D Conversion finishe...

Page 141: ...XTRG TSEL2 TSEL1 TSEL0 ADCCK2 ALIGN CKSEL1 CKSEL0 R W R W R W R W R W R W R W R W Initial value 01H EXTRG A D external Trigger 0 External Trigger disable 1 External Trigger enable TSEL 2 0 A D Trigger...

Page 142: ...Z51F6412 Product Specification PS030302 0212 P R E L I M I N A R Y 139 0 1 fx 4 3V 5V 1 0 fx 8 2 7V 3V 1 1 fx 32 2 4V 2 7V Note 1 fx system clock 2 ADC clock have to be used 3MHz under...

Page 143: ...and the remainder is replaced with the dividend value The registers for CALCULATOR_AI can be indirectly accessed via CAL_CNTR CAL_ADDR CAL_DATA to save the SFR area and to increase the code performan...

Page 144: ...Divisor equals 0 0 Divisor is not 0 1 Divisor is 0 EOD End of Division Note Multiplication needs only one clock cycle Note Division needs 32 clock cycles 0 During Calculation 1 Idle or End of Calculat...

Page 145: ...Z51F6412 Product Specification PS030302 0212 P R E L I M I N A R Y 142 CAL_DATA 7 0 Calculator Internal Register Current Value indexed by CAL_ADDR address index value...

Page 146: ...8 a 15 08 ADDR ADDR 1 CAL_DATA a MA 07 00 a 07 00 ADDR ADDR 1 CAL_DATA b 8 MB 15 08 b 15 08 ADDR ADDR 1 CAL_DATA b MB 07 00 b 07 00 ADDR ADDR 1 now ADDR points to MO 31 24 so just read it mul_o unsign...

Page 147: ...0 ADDR ADDR 1 CAL_DATA b 8 DB 15 08 b 15 08 ADDR ADDR 1 CAL_DATA b DB 07 00 b 07 00 ADDR ADDR 1 while CAL_CNTR CAL_DIV_DONE 0 wait until division is done need 32clock cycles now ADDR points to DQ 31 2...

Page 148: ...nly operate in sub clock mode Stop Only operate in sub clock mode Timer Operates Continuously Halted Only when the Event Counter Mode is Enable Timer operates Normally Halted Only when the Event Count...

Page 149: ...be enabled before IDLE mode If using reset because the device becomes initialized state the registers have reset value Ex MOV PCON 0000_0001b setting of IDLE mode set the bit of STOP and IDLE Control...

Page 150: ...ased from STOP mode the Basic interval timer is activated on wake up Therefore before STOP instruction user must be set its relevant prescaler divide ratio to have long enough time more than 20msec th...

Page 151: ...re STOP1 2 mode start Figure 12 5 Interrupt Enable Flag of All EA of IE should be set to 1 Released by only interrupt which each interrupt enable flag 1 and jump to the relevant interrupt service rout...

Page 152: ...l Register 87H 7 6 5 4 3 2 1 0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R W R W R W R W R W R W R W R W Initial value 00H IDLE Mode 01H IDLE mode enable STOP1 2 Mode 03H STOP1 2 mode enable Note 1 To e...

Page 153: ...es External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 BOD Reset In the case of BODEN 1 OCD Reset 13 3 Block Diagram On Chip Hardware Initial Value Program Counter PC 0000h Ac...

Page 154: ...r ON RESET When rising device power the POR Power ON Reset have a function to reset the device If using POR it executes the device RESET function instead of the RESET IC or the RESET circuits And Exte...

Page 155: ...out 16ms 00 01 02 03 00 01 02 03 00 01 02 2F 30 31 3E 3F 00 01 02 03 Ext_reset have not an effect on counter value for config read Counting for config read start after POR is released H INT OSC 128KHz...

Page 156: ...an Flash operating voltage for Config read Slew Rate 0 025V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR...

Page 157: ...abilization time with 16ms and after the stable state the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at add...

Page 158: ...6V 2 5V 3 6V or 4 2V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the BODEN bit is set to off by software VDD Internal R...

Page 159: ...ation Register description Reset control Register consists of the BOD Control Register BODR VDD Internal nPOR PAD RESETB BIT for Config BOD_RESETB BIT for Reset INT OSC 128KHz 32 INT OSC 128KHz RESET_...

Page 160: ...The bit is reset by writing 0 to this bit or by Power ON reset 0 No detection 1 Detection WDTRF Watch Dog Reset flag bit The bit is reset by writing 0 to this bit or by Power ON reset 0 No detection 1...

Page 161: ...nterface and the On chip Debug system 14 1 2 Feature Two wire external interface 1 wire serial clock input 1 wire bi directional serial data bus Debugger Access to All Internal Peripheral Units Intern...

Page 162: ...nsmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge error is generated host PC makes stop condition and transmits command which ha...

Page 163: ...60 14 2 2 Packet transmission timing 14 2 2 1 Data transfer St Sp START STOP DSDA DSCL LSB acknowledgement signal from receiver ACK ACK 1 10 1 10 acknowledgement signal from receiver LSB Figure 14 2 1...

Page 164: ...transmitter Data output By receiver DSCL from master clock pulse for acknowledgement no acknowledge acknowledge St Sp START condition STOP condition DSDA DSCL DSDA DSCL data line stable data valid ex...

Page 165: ...Machine Master Target Device Slave VDD VDD Current source for DSCL to fast 0 to 1 transition in high speed mode pull up resistors Rp Rp VDD DSCL IN DSCL OUT DSCL IN Start wait start HIGH Host PC DSCL...

Page 166: ...rol and status register Registers to control Flash and Data EEPROM are Mode Register FEMR Control Register FECR Status Register FESR Time Control Register FETCR Address Low Register FEARL Address Midd...

Page 167: ...OTP area VFY Set program or erase verify mode with PGM or ERASE Program Verify PGM 1 VFY 1 Erase Verify ERASE 1 VFY 1 FEEN Enable program and erase of Flash When inactive it is possible to read as nor...

Page 168: ...SY is cleared when program erase or verify starts and set when program erase or verify stops Max program erase time at 14 7456Mhz system clock 255 1 2 1 fx 128 4 44ms In the case of 10 of error rate o...

Page 169: ...ata register In no program erase verify mode READ WRITE of FECR read or write data from Flash to this register or from this register to Flash The sequence of writing data to this register is used for...

Page 170: ...ite checksum reset WRITE and READ bits can be used in program erase and verify mode with FEAR registers Read or writes for memory cell or page buffer uses read and write enable signals from memory con...

Page 171: ...0212 P R E L I M I N A R Y 168 PAGE ADDRESS WORD ADDRESS Program Memory 0x3F 0x00 0x000 0x3FF Page buffer size 64Bytes Page 1023 Page 1022 Page 0 Page 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 15...

Page 172: ...7 6 5 4 3 2 1 0 FEMR 4 1 FEMR 5 1 FEMR 2 FECR 6 FECR 7 ERASE VFY PGM VFY OTPE AEE AEF Page Buffer Reset Page Buffer Load 0X00H Erase Erase Latency 500us Page Buffer Reset Configuration Reg setting Ce...

Page 173: ...rogram mode Step 1 Enter OCD ISP mode 1 Step 2 Set ENBDM bit of BCR Step 3 Enable debug and Request debug mode Step 4 Enter program erase mode sequence 2 1 Write 0xAA to 0xF555 2 Write 0x55 to 0xFAAA...

Page 174: ...all pages are written 15 4 1 4 Flash page erase mode Step 1 Enable program mode Step 2 Reset page buffer FEMR 1000_0001 FECR 0000_0010 Step 3 Select page buffer FEMR 1000_1001 Step 4 Write h00 to page...

Page 175: ...d select OTP area FEMR 1010_0101 Step 6 Set page address FEARH FEARM FEARL 20 hx_xxxx Step 7 Set FETCR Step 8 Start program FECR 0000_1011 Step 9 Insert one NOP operation Step 10 Read FESR until PEVBS...

Page 176: ...1 12 Flash page buffer read Step 1 Enable program mode Step 2 Select page buffer FEMR 1000_1001 Step 3 Read data from Flash 15 4 2 Summary of Flash Program Erase Mode Table 15 3 Operation Mode Operat...

Page 177: ...Address auto increment is supported when read or write data without address Table 15 4 The selection of memory type by ADDRH 7 4 ADDRH 7 4 Memory Type 0 0 0 0 Program Memory 0 0 0 1 External Memory 0...

Page 178: ...H nRD H H L H H H H H H H H H H H PDATA ADDRL DATA0 DATA1 DATA2 DATA3 DATAn n byte data write with 1 byte address nALE L H H H H H H nWR L H L H L H L H L H L H L H nRD H H H H H H H H H H H H H H PD...

Page 179: ...1 Write Write Write Write Write Write Write Write TAS TAH TWE Read address auto increment AH 00H Write AL AM AH Data AL AM Data AL Data Out Data 1 byte write with 3 byte address 1 byte write with 2 by...

Page 180: ...2 Mode entrance of Byte parallel TARGET MODE P0 3 0 P0 3 0 P0 3 0 Byte Parallel Mode 4 h5 4 hA 4 h5 Power on reset nTEST DSDA R0 3 0 RESET_SYSB h5 hA h5 Release from worst 1 7V Low period required du...

Page 181: ...he Lock bit can only be erased to 0 with the bulk erase command and a value of more than 0x80 at FETCR Table 15 5 Security policy using lock bits LOCK MODE USER MODE ISP PMODE Flash OTP Flash OTP LOCK...

Page 182: ...36B 8KB 256B 0x0FF 0x1FFF SXINEN External Sub Oscillator Enable Bit 0 Sub OSC disable default 1 Sub OSC enable XINENA External Main Oscillator Enable Bit 0 Main OSC disable default 1 Main OSC Enable O...

Page 183: ...a Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC A Decrem...

Page 184: ...ve indirect memory to direct byte 2 2 75 MOV dir data Move immediate to direct byte 3 2 F6 F7 MOV Ri A Move A to indirect memory 1 1 A6 A7 MOV Ri dir Move direct byte to indirect memory 2 2 76 77 MOV...

Page 185: ...ompare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne re...

Page 186: ...tial error used with input port condition JB bit rel jump on direct bit 1 JNB bit rel jump on direct bit 0 JBC bit rel jump on direct bit 1 and clear CJNE A dir rel compare A direct jne relative DJNZ...

Page 187: ...as intern al parameter or carry bit and then use compare jump instruction unsigned char ret_bit_err void return P00 MOV R7 000 JB 080 0 xxx it possible to be error MOV R7 001 xxx RET while 1 if P0 0x...

Page 188: ...visit Zilog s Technical Support page at http support zilog com To learn more about this product find additional documentation or to discover other fac ets about Zilog product offerings please visit th...

Page 189: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information ZiLOG Z51F6412ARX Z51F6412ATX Z51F6412000ZCOG...

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