Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
60
CS[1:0]
Determine System Clock
Note) by CBYS bit, reflection point is decided
CS1 CS0 Description
0 0 fINTRC
INTRC
(16
MHz)
0
1
fXIN Main Clock (1~10 MHz)
1
0
fSUB / fPLL (32.768 KHz, 14.75MHz)
1 1 fRING
(125
KHz)
PLLCR (Phase Locked Loop Control Register) : D9H
7
6
5
4
3
2
1
0
PLLSTAT
PLLCKS
VDConSUB
PLLFB
PLLPD
PLLEN
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
PLLSTAT
PLL Status flag (read only bit)
0
PLL output is Fvcoin (32.768KHz bypass)
1
PLL output is Fpll
PLLCKS
PLL output clock selection control
PLLEN should be set “1” to use bypass control. PLL VCO would
not stop in the case of PLLCKS is “0” (32KHz). In addition, this bit
automatically set by interrupt event on sub-active or power down.
0
PLL output is Fvcoin (32.768KHz bypass, default)
1
PLL output is Fpll
VDConSUB
Normal Power Selection for PLLCKS control
0
Limited VDC power when PLLCKS is “0” (32.768KHz)
- Limited VDC consumes about 0.1mA to drive 1mA
(default)
- In this mode, user must care about power consumption
1
Normal VDC power when PLLCKS is “0” (32.768KHz)
- Normal VDC consumes about 1mA to drive about 10mA
PLLFB[1:0]
PLL Feedback Divider control
PLLFB1 PLLFB0 description
0 0 FBdiv
=
674
(Not
valid)
0 1 FBdiv
=
562
(Not
valid)
1 0 FBdiv
=
450
1 1 FBdiv
=
338
PLLPD[1:0]
PLL Post Divider Control
PLLPD1 PLLPD0 description
0 0 M
=
1
0 1 M
=
2
1 0 M
=
4
1 1 M
=
8
PLLEN
PLL Enable control
0
PLL disable (2 SUB-OSC clock need for disable, default)
1 PLL
enable
Fvco = Fvcoin * FBdiv
Fpll = Fvco / M
