Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
117
11.9 I
2
C
11.9.1 Overview
The I
2
C is one of industrial standard serial communication protocols, and which uses 2 bus lines
Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL
lines are open-drain output, each line needs pull-up resistor. The features are as shown below.
- Compatible
with
I
2
C bus standard
- Multi-master
operation
-
Up to 400 KHz data transfer speed
-
7 bit address
-
Support 2 slave addresses
-
Both master and slave operation
- Bus
busy
detection
11.9.2 Block Diagram
11.9.3 I
2
C Bit Transfer
The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions
are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line
is high.
SDA
F/F
8-bit Shift Register
(SHFTR)
Slave Addr. Register1
(I2CSAR1)
Noise
Canceller
(debounce)
Data Out Register
(I2CDR)
SCL High Period Register
(I2CSCLHR)
SCL Low Period Register
(I2CSCLLR)
SDA Hold Time Register
(I2CDAHR)
SDA
Out Controller
SCL
Out Controller
SCL
Noise
Canceller
(debounce)
I
n
t
e
r
n
a
l
B
u
s
L
i
n
e
SDAIN
SDAOUT
SCLIN
SCLOUT
1
0
1
0
Debounce
enable
Debounce
enable
Slave Addr. Register
(I2CSAR)
Figure 11-34 I
2
C Block Diagram
