Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
59
11.1.3 Register Map
Table 11-1 Register Map
Name
Address
Dir
Default
Description
SCCR
8AH
R/W
24H
System and Clock Control Register
PLLCR D9H
R/W
00H PLL
Control
Register
11.1.4 Clock Generator Register description
The Clock Generation Register uses clock control for system operation. The clock generation
consists of System and Clock register.
11.1.5 Register description for Clock Generator
SCCR (System and Clock Control Register) : 8AH
7
6
5
4
3
2
1
0
STOP1
DIV1
DIV0
CBYS
ISTOP
XSTOP
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 24H
STOP1
Control the STOP Mode.
Note) when PCON=0x03, It is applied. But when PCON=0x01,
don’t set this bit.
0
STOP2 Mode (at PCON=0x03) (default)
1
STOP1 Mode (at PCON=0x03)
DIV[1:0]
When using fINTRC as system clock, determine division rate.
Note) when using fINTRC as system clock, only division rate come
into effect.
Note) To change by software, CBYS set to ‘1’
DIV1 DIV0 description
0 0 fINTRC/1
(16MHz)
0 1 fINTRC/2
(8MHz)
(default)
1 0 fINTRC/4
(4MHz)
1 1 fINTRC/8
(2MHz)
CBYS
Control the scheme of clock change. If this bit set to ‘0’, clock
change is controlled by hardware. But if this set to ‘1’, clock
change is controlled by software. Ex) when setting CS[1:0], if
CBYS bit set to ‘0’, it is not changed right now, CPU goes to STOP
mode and then when wake-up, it applies to clock change.
Note) when clear this bit, keep other bits in SCCR.
0
Clock changed by hardware during stop mode (default)
1
Clock changed by software
ISTOP
Control the operation of INT-RC Oscillation
Note) when CBYS=’1’, It is applied
0 RC-Oscillation
enable
(default)
1 RC-Oscillation
disable
XSTOP
Control the operation of X-Tal Oscillation
Note1) when CBYS=’1’, It is applied
Note2) if XINENA bit in FUSE_CONF to ‘0’, XSTOP is fixed to ‘1’
0 X-Tal
Oscillation
enable
1
X-Tal Oscillation disable (default)
