Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
31
8. Memory
The Z51F6412 MCU addresses two separate address memory stores: Program memory and Data
memory. The logical separation of Program and Data memory allows Data memory to be assessed by
8-bit addresses, which can be more quickly stored and manipulated by 8-bit CPU. Nevertheless, 16-
bit Data memory addresses can also be generated through the DPTR register.
Program memory can only be read, not written to. There can be up to 64K bytes of Program memory
in a bank. In the Z51F6412 Flash version of these devices the 64K bytes of Program memory are
provided on-chip. Data memory can be read and written to up to 256 bytes internal memory (DATA)
including the stack area and 3K bytes of external data memory(XRAM).
8.1 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes for one bank of memory space.
Figure 8-1 shows a map of the lower part of the program memory. After reset, the CPU begins
execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The
interrupt causes the CPU to jump to that location, where it commences execution of the service
routine. External interrupt 0, for example, is assigned to location 0003H. If external interrupt 0 is going
to be used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its
service location is available as general purpose program memory. If an interrupt service routine is
short enough (as is often the case in control applications), it can reside entirely within that 8 byte
interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations,
if other interrupts are in use.
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User Function Mode: 64KBytes Included Interrupt Vector Region
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Non-volatile and reprogramming memory: Flash memory
FFFFH
0000H
64K Bytes
Bank 0
Total
64K Bytes
Flash
Figure 8-1 Program memory
