Z51F6412
Product Specification
PS030302-0212
P R E L I M I N A R Y
61
Fvco = (32.768 KHz * 450) = 14.7456 MHz
Fvco = (32.768 KHz * 338) = 11.075584 MHz
11.1.6 Power control for 32.768KHz Clock operation
The Z51F6412 MCU features two different way to use 32.768KHz operation.
First, user can select 32.768KHz clock on PLL disable as a low power operation(Sub-active mode,
CS[1:0] = 0x2 of SCCR, PLLCKS = ”0” and PLLEN = “0” of PLLCR). In this mode, user also has to
care about power consumption of whole chip. Because, to achieve lower power consumption in sub-
active mode, The Z51F6412 MCU has a smaller SUB-ACTIVE VDC(voltage Down Converter) which
is automatically enable in sub-active mode and has only 1mA current capability while main VDC(for
normal operation) is off.
Second, if user wanted to use 32.768KHz on PLL enable(CS[1:0] = 0x2 of SCCR, PLLCKS = “0” and
PLLEN = “1” of PLLCR), in this case PLL VCO block would not stop so need more power than the first
case. In this case, user can select VDC mode with VDConSUB bit of PLLCR. If VDConSUB = “0”,
then main 10mA VDC is off and only SUB_ACTIVE VDC of 1mA is available. If user set VDConSUB =
“1”, main VDC, which has 10mA of current drive capability for 1.8V output, will work for 32.768KHz
and main VDC itself will consume about 1mA current to operate while SUB_ACTIVE VDC consume
0.1mA.
Table 11-2 VDC current consumption
PLLEN@PLLCR
(PLLCKS = 0)
VDConSUB@PLLCR
(PLLCKS = 0)
MAIN
VDC
SUB
VDC
VDC current
capability
VDC current
consumption
1
1 ON
OFF
1mA
0 OFF
ON
0.1mA
0
X (don’t care)
OFF
ON
0.1mA
