HP 8112A, Operating, Programming And Servicing Manual

Page: 264 / 406

Counter
Burst is triggered by external trigger or operation of the
key. The counter is then clocked by output pulses from the period
generator on the main board Al.
Blocking Flip-flop
The 1 1-bit counter consists of two 4-bit counter ICs (Ul l l and
U112) and three flip-flops U105 and U106A which handle the three
least-significant bits. The whole counter counts down when clocked
by the burst-clock signal from the main board. The burst-clock
signal is enabled by the burst-on signal which is withdrawn when the
counter reaches "1" (See "Blocking Flip-flop" ).
The blocking flip-flop U109A performs two functions:
•
Period Generator control
•
Counter resetting
Period Generator Control
When counters Ul 1 1 and Ul12 have both cleared, the TC output
from them (pin 12), gated by Ul lO, sets the flip-flop U109A. The Q
output disables counter U l l l and the Q output enables the wired-or
"Burst On" circuit via U107B. In this configuration the BURST ON
signal is active (low), only when all the the counter inputs are low
signifying the burst is complete.
Counter reset
For the counter to be re-enabled, the logic signal LBC from the
address decoder U16 must be set true (low). This resets the blocking
flip-flop, re-loads the burst counter and sets the counter enable input
(CE) low. The burst circuitry is then in a stand-by state awaiting
the next period generator pulse train.
Once started, count-down continues until the counter flip-flops (U105
and U106A) reach 1 and the burst-on signal ·is withdrawn, stopping
the burst-clock signal.
1 0.6-2 Servicing the Burst Control Circuit