HP 8112A, Operating, Programming And Servicing Manual

Page: 202 / 406

Address Decoder
An eight line decoder UlOO is controlled by address lines LA3 to LA5
with WS 1 . The decoder output lines determine which timing, mode
or range circuit latches data from the data bus
(
LDO to LD7
)
as
shown in Table 10.3- 1. The address decoder also controls the output
of the contents of the error latches onto the data bus.
Mode and Range
Decoders
Control Input Circuits
Timing IC
1 0.3-2 Servicing the Timing and
Slope Generators
Table 1 0.3-1. Address decoder enable outputs
UlOO pin
Mnemonic
IC
Circuit Action
7
SRC
U300
Load Range Decoder
10
PIC
U200
Load Period Generator
11
CLR U 142
Output Error Latches
12
MAMO U l O l Load Mode Decoder
13
WIC
U240
Load Width Generator
14
DIC U220
Load Delay Generator
Under the control of the Address Decoder, these decoders latch data
from the data bus and input it to the various switches that select
control and trigger modes and the switching transistors which select
the range capacitor to be used by the slope IC.
Refer to Figure 10.3-4. The control input signal is clamped within
±5 V by the protection diodes CR130 to CR132. For Period, Delay,
and Width control the input voltage is rectified by precision rectifier
U132B and associated components. The signal then passes to the
control mode selector switch U130 where microprocessor control
signals ACO and ACl from the mode decoder UlOl select its route to
the appropriate timing IC.
When the High Level Control
(
HILC
)
is selected, the control input
signal is routed through the switch
(
U131
)
and low pass filter
(
U132a
with associated components
)
, to the output stages. See chapter
10.5. The low pass filter is needed because of the 20 µs settling time
inherant in HILC mode operation.
The timing ICs used in the HP 8 1 12A are programmable timers
which can be used to produce repetition rates, pulse widths and
delay times by utilizing a variety of trigger and gate mode inputs.