HP 8112A, Operating, Programming And Servicing Manual

Page: 203 / 406

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Figure 1 0.3· 1 . Timing IC block diagram
Refer to Figure 10.3- 1 and Figure 10.3-6. The timing IC has an input
store containing 8 control bits which control the mode of the IC:
Table 1 0.3-2. IC Digital Control Signals
Pin
Naine Signal
Function
10 CONTROL WS3
A positive TTL edge on this pin latches all
ENABLE the digital control signals into the input
store.
1 1 GATE
/
TRIG LD7 Selects trigger or gate
12 TRIG POS
LD6
Positive trigger
13 TRIG NEG LD5 Negative trigger
14 TIME
/
RATE LD4 Selects TIME or RATE mode
15 MODE LD3 Always 0 in this application
16 RANGE C LD2 Range selection, refer to Table 10.3-3
17 RANGE B LDl
18 RANGE A LDO
Timing Generation
The main timing element of the IC is a voltage controlled oscillator
(VCO) which has two ranges of operation in each of the two
operating modes (see TIME and RATE below) . These two basic
ranges, time and frequency, are further divided if necessary by
switching divider circuits
(
6
x
decade counters) into operation under
control of the range setting.
Servicing the Timing and 10.3-3
Slope Generators