Rev. 3.0, 04/02, page 73 of 1064
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN [28:10] SZ [1:0]
SH C PR [1:0]
SA [2:0]
SA [2:0]
SA [2:0]
TC
TC
TC
SA [2:0] TC
ASID [7:0]
VPN [31:10]
V
Entry 63
D WT
31
29 28
9 8 7 6 5 4 3 2 1 0
—
— V SZ PR SZ C D SHWT
PTEL
Write
UTLB
31
10 9 8 7
0
—
ASID
PTEH
31
26 25 24 23
18 17 16 15
10 9 8 7
3 2 1 0
LRUI
—
URB
—
URC
SV
SQMD
—
TI — AT
MMUCR
VPN
10
PPN
31
4 3 2
0
—
SA
TC
PTEA
Entry specification
Figure 3.12 Operation of LDTLB Instruction
3.5.4
Hardware ITLB Miss Handling
In an instruction access, the SH7751 Series searches the ITLB. If it cannot find the necessary
address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by
hardware, and if the necessary address translation information is present, it is recorded in the
ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address
translation information is not found in the UTLB search, an instruction TLB miss exception is
generated and processing passes to software.
Summary of Contents for SH7751
Page 39: ...Rev 3 0 04 02 page xxxviii of xxxviii ...
Page 89: ...Rev 3 0 04 02 page 50 of 1064 ...
Page 157: ...Rev 3 0 04 02 page 118 of 1064 ...
Page 193: ...Rev 3 0 04 02 page 154 of 1064 ...
Page 225: ...Rev 3 0 04 02 page 186 of 1064 ...
Page 253: ...Rev 3 0 04 02 page 214 of 1064 ...
Page 301: ...Rev 3 0 04 02 page 262 of 1064 ...
Page 343: ...Rev 3 0 04 02 page 304 of 1064 ...
Page 607: ...Rev 3 0 04 02 page 568 of 1064 ...
Page 671: ...Rev 3 0 04 02 page 632 of 1064 ...
Page 745: ...Rev 3 0 04 02 page 706 of 1064 ...
Page 767: ...Rev 3 0 04 02 page 728 of 1064 ...
Page 1061: ...Rev 3 0 04 02 page 1022 of 1064 NMI tNMIL tNMIH Figure 23 69 NMI Input Timing ...
Page 1069: ...Rev 3 0 04 02 page 1030 of 1064 ...
Page 1103: ...Rev 3 0 04 02 page 1064 of 1064 ...