Rev. 3.0, 04/02, page vii of xxxviii
4.5
Memory-Mapped Cache Configuration (SH7751) ............................................................ 103
4.5.1
IC Address Array ................................................................................................. 103
4.5.2
IC Data Array ....................................................................................................... 104
4.5.3
OC Address Array ................................................................................................ 105
4.5.4
OC Data Array ..................................................................................................... 106
4.6
Memory-Mapped Cache Configuration (SH7751R) ......................................................... 107
4.6.1
IC Address Array ................................................................................................. 108
4.6.2
IC Data Array ....................................................................................................... 109
4.6.3
OC Address Array ................................................................................................ 110
4.6.4
OC Data Array ..................................................................................................... 111
4.6.5
Summary of Memory-Mapped OC Addresses ..................................................... 112
4.7
Store Queues ..................................................................................................................... 113
4.7.1
SQ Configuration ................................................................................................. 113
4.7.2
SQ Writes ............................................................................................................. 113
4.7.3
Transfer to External Memory ............................................................................... 113
4.7.4
Determination of SQ Access Exception ............................................................... 115
4.7.5
SQ Read (SH7751R only) .................................................................................... 115
4.7.6
SQ Usage Notes ................................................................................................... 116
Section 5
Exceptions
......................................................................................................... 119
5.1
Overview ........................................................................................................................... 119
5.1.1
Features ................................................................................................................ 119
5.1.2
Register Configuration ......................................................................................... 119
5.2
Register Descriptions......................................................................................................... 120
5.3
Exception Handling Functions .......................................................................................... 121
5.3.1
Exception Handling Flow..................................................................................... 121
5.3.2
Exception Handling Vector Addresses................................................................. 121
5.4
Exception Types and Priorities.......................................................................................... 122
5.5
Exception Flow ................................................................................................................. 125
5.5.1
Exception Flow .................................................................................................... 125
5.5.2
Exception Source Acceptance .............................................................................. 126
5.5.3
Exception Requests and BL Bit............................................................................ 128
5.5.4
Return from Exception Handling ......................................................................... 128
5.6
Description of Exceptions ................................................................................................. 128
5.6.1
Resets ................................................................................................................... 129
5.6.2
General Exceptions .............................................................................................. 134
5.6.3
Interrupts .............................................................................................................. 148
5.6.4
Priority Order with Multiple Exceptions .............................................................. 151
5.7
Usage Notes....................................................................................................................... 152
5.8
Restrictions........................................................................................................................ 153
Section 6
Floating-Point Unit
........................................................................................ 155
6.1
Overview ........................................................................................................................... 155
Summary of Contents for SH7751
Page 39: ...Rev 3 0 04 02 page xxxviii of xxxviii ...
Page 89: ...Rev 3 0 04 02 page 50 of 1064 ...
Page 157: ...Rev 3 0 04 02 page 118 of 1064 ...
Page 193: ...Rev 3 0 04 02 page 154 of 1064 ...
Page 225: ...Rev 3 0 04 02 page 186 of 1064 ...
Page 253: ...Rev 3 0 04 02 page 214 of 1064 ...
Page 301: ...Rev 3 0 04 02 page 262 of 1064 ...
Page 343: ...Rev 3 0 04 02 page 304 of 1064 ...
Page 607: ...Rev 3 0 04 02 page 568 of 1064 ...
Page 671: ...Rev 3 0 04 02 page 632 of 1064 ...
Page 745: ...Rev 3 0 04 02 page 706 of 1064 ...
Page 767: ...Rev 3 0 04 02 page 728 of 1064 ...
Page 1061: ...Rev 3 0 04 02 page 1022 of 1064 NMI tNMIL tNMIH Figure 23 69 NMI Input Timing ...
Page 1069: ...Rev 3 0 04 02 page 1030 of 1064 ...
Page 1103: ...Rev 3 0 04 02 page 1064 of 1064 ...