Rev. 3.0, 04/02, page 476 of 1064
Bit 19—
Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the
pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR3.
Bit 19: DS
Description
0
Low level detection
(Initial value)
1
Falling edge detection
Notes: Level detection burst mode when TM = 1 and DS = 0
Edge detection burst mode when TM = 1 and DS = 1
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of
) is an active-high or active-low output.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 18: RL
Description
0
DRAK is an active-high output
(Initial value)
1
DRAK is an active-low output
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR1–CHCR3. (DDT mode: TDACK)
Bit 17: AM
Description
0
DACK is output in read cycle
(Initial value)
1
DACK is output in write cycle
Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 16: AL
Description
0
Active-high output
(Initial value)
1
Active-low output
Summary of Contents for SH7751
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