Rev. 3.0, 04/02, page 975 of 1064
Tw
T1
Twe
TB2
TB1
Twb
Twbe
TB1
TB2
Twb
Twbe
Twb
T2
TB2
Twbe
TB1
CKIO
A25–A5
A4–A0
D31–D0
(read)
t
AD
t
AD
t
AD
t
RDH
t
RDS
t
RDH
t
RDS
DACKn
(DA)
t
DACD
t
DACD
t
DACD
t
BSD
t
BSD
t
BSD
t
BSD
t
RSD
t
RSD
t
RWD
t
CSD
t
RWD
t
CSD
t
DACD
t
DACD
t
RSD
RD/
t
RDYH
t
RDYS
t
RDYH
t
RDYS
t
RDYH
t
RDYS
t
RDYH
t
RDYS
DACKn
(SA: IO
←
memory)
Notes:
IO:
DACK device
SA:
Single address DMA transfer
DA:
Dual address DMA transfer
DACK set to active-high
Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
Summary of Contents for SH7751
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