Rev. 3.0, 04/02, page 731 of 1064
19.1.3
Pin Configuration
Table 19.1 shows the INTC pin configuration.
Table 19.1
INTC Pins
Pin Name
Abbreviation
I/O
Function
Nonmaskable interrupt
input pin
NMI
Input
Input of nonmaskable interrupt request
signal
Interrupt input pins
–
Input
Input of interrupt request signals
(maskable by I3–I0 in SR)
19.1.4
Register Configuration
The INTC has the registers shown in table 19.2.
Table 19.2
INTC Registers
Name
Abbreviation
R/W
Initial
Value*
1
P4 Address
Area 7
Address
Access
Size
Interrupt control
register
ICR
R/W
*
2
H'FFD00000
H'1FD00000
16
Interrupt priority
register A
IPRA
R/W
H'0000
H'FFD00004
H'1FD00004
16
Interrupt priority
register B
IPRB
R/W
H'0000
H'FFD00008
H'1FD00008
16
Interrupt priority
register C
IPRC
R/W
H'0000
H'FFD0000C H'1FD0000C
16
Interrupt priority
register D
IPRD
R/W
H'DA74
H'FFD00010
H'1FD00010
16
Interrupt priority
register 00
INTPRI00
R/W
H'00000000
H'FE080000
H'1E080000
32
Interrupt request
register 00
INTREQ00
R
H'00000000
H'FE080020
H'1E080020
32
Interrupt mask
register 00
INTMSK00
R/W
H'000003FF
H'FE080040
H'1E080040
32
Interrupt mask
clear register 00
INTMSKCLR00 W
—
H'FE080060
H'1E080060
32
Notes: *1 Initialized by a power-on reset or manual reset.
*2 H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
Summary of Contents for SH7751
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