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Hitachi SH7751, Hardware Manual

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Rev. 3.0, 04/02, page 774 of 1064

 

Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00

Data: H'00000000 / data mask: H'00000000

Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not
included in conditions)

A user break interrupt is not generated on channel A since the instruction access is not a write
cycle.

A user break interrupt is not generated on channel B since instruction access is performed on
an even address.

Operand Access Cycle Break Condition Settings

 

Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 /
BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 /
BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080

Conditions set: Independent channel A/channel B mode

 

Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00

Bus cycle: operand access, read (operand size not included in conditions)

 

Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02

Data: H'0000A512 / data mask: H'00000000

Bus cycle: operand access, write, word

Data break enabled

On channel A, a user break interrupt is generated in the event of a longword read at address
H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with
ASID = H'80.

On channel B, a user break interrupt is generated when H'A512 is written by word access to
any address from H'000AB000 to H'000ABFFE with ASID = H'70.

Summary of Contents for SH7751

Page 1: ...emory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not ...

Page 2: ...Hitachi SuperH RISC engine SH7751 Series SH7751 SH7751R Hardware Manual ADE 602 201B Rev 3 0 4 11 2002 Hitachi Ltd ...

Page 3: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 4: ...sic knowledge of electric circuits logic circuits and microcomputers is required This hardware manual contains revisions related to the addition of R mask functionality Be sure to check the text for the updated content Purpose This manual provides the information of the hardware functions and electrical characteristics of the SH7751 and SH7751R The SH 4 Programming Manual contains detailed informa...

Page 5: ...Series Hardware Manual This manual SH 4 Programming Manual ADE 602 156 User manuals for development tools Name of Document Document No C C Compiler Assembler Optimizing Linkage Editor User s Manual ADE 702 246 Simulator Debugger User s Manual ADE 702 186 Hitachi Embedded Workshop User s Manual ADE 702 201 ...

Page 6: ... 2 3 Memory Mapped Registers 46 2 4 Data Format in Registers 47 2 5 Data Formats in Memory 47 2 6 Processor States 48 2 7 Processor Modes 49 Section 3 Memory Management Unit MMU 51 3 1 Overview 51 3 1 1 Features 51 3 1 2 Role of the MMU 51 3 1 3 Register Configuration 54 3 1 4 Caution 54 3 2 Register Descriptions 55 3 3 Address Space 58 3 3 1 Physical Address Space 58 3 3 2 External Memory Space 6...

Page 7: ...otection Violation Exception 79 3 6 7 Initial Page Write Exception 79 3 7 Memory Mapped TLB Configuration 80 3 7 1 ITLB Address Array 81 3 7 2 ITLB Data Array 1 82 3 7 3 ITLB Data Array 2 83 3 7 4 UTLB Address Array 83 3 7 5 UTLB Data Array 1 85 3 7 6 UTLB Data Array 2 86 Section 4 Caches 87 4 1 Overview 87 4 1 1 Features 87 4 1 2 Register Configuration 88 4 2 Register Descriptions 89 4 3 Operand ...

Page 8: ... 5 SQ Read SH7751R only 115 4 7 6 SQ Usage Notes 116 Section 5 Exceptions 119 5 1 Overview 119 5 1 1 Features 119 5 1 2 Register Configuration 119 5 2 Register Descriptions 120 5 3 Exception Handling Functions 121 5 3 1 Exception Handling Flow 121 5 3 2 Exception Handling Vector Addresses 121 5 4 Exception Types and Priorities 122 5 5 Exception Flow 125 5 5 1 Exception Flow 125 5 5 2 Exception Sou...

Page 9: ...173 Section 8 Pipelining 187 8 1 Pipelines 187 8 2 Parallel Executability 194 8 3 Execution Cycles and Pipeline Stalling 198 Section 9 Power Down Modes 215 9 1 Overview 215 9 1 1 Types of Power Down Modes 215 9 1 2 Register Configuration 217 9 1 3 Pin Configuration 217 9 2 Register Descriptions 218 9 2 1 Standby Control Register STBCR 218 9 2 2 Peripheral Module Pin High Impedance Control 220 9 2 ...

Page 10: ...s 241 10 1 Overview 241 10 1 1 Features 241 10 2 Overview of CPG 243 10 2 1 Block Diagram of CPG 243 10 2 2 CPG Pin Configuration 246 10 2 3 CPG Register Configuration 246 10 3 Clock Operating Modes 247 10 4 CPG Register Description 249 10 4 1 Frequency Control Register FRQCR 249 10 5 Changing the Frequency 251 10 5 1 Changing PLL Circuit 1 Starting Stopping When PLL Circuit 2 is Off 251 10 5 2 Ch...

Page 11: ...of Week Counter RWKCNT 269 11 2 6 Day Counter RDAYCNT 270 11 2 7 Month Counter RMONCNT 270 11 2 8 Year Counter RYRCNT 271 11 2 9 Second Alarm Register RSECAR 272 11 2 10 Minute Alarm Register RMINAR 272 11 2 11 Hour Alarm Register RHRAR 273 11 2 12 Day of Week Alarm Register RWKAR 273 11 2 13 Day Alarm Register RDAYAR 274 11 2 14 Month Alarm Register RMONAR 275 11 2 15 RTC Control Register 1 RCR1 ...

Page 12: ...2 5 1 Register Writes 303 12 5 2 TCNT Register Reads 303 12 5 3 Resetting the RTC Frequency Divider 303 12 5 4 External Clock Frequency 303 Section 13 Bus State Controller BSC 305 13 1 Overview 305 13 1 1 Features 305 13 1 2 Block Diagram 307 13 1 3 Pin Configuration 308 13 1 4 Register Configuration 310 13 1 5 Overview of Areas 311 13 1 6 PCMCIA Support 314 13 2 Register Descriptions 318 13 2 1 B...

Page 13: ... 13 3 13 Slave Mode 461 13 3 14 Cooperation between Master and Slave 461 13 3 15 Notes on Usage 462 Section 14 Direct Memory Access Controller DMAC 463 14 1 Overview 463 14 1 1 Features 463 14 1 2 Block Diagram SH7751 466 14 1 3 Pin Configuration SH7751 467 14 1 4 Register Configuration SH7751 468 14 2 Register Descriptions 470 14 2 1 DMA Source Address Registers 0 3 SAR0 SAR3 470 14 2 2 DMA Desti...

Page 14: ... 5 DMA Operation Register DMAOR 559 14 8 Operation SH7751R 562 14 8 1 Channel Specification for a Normal DMA Transfer 562 14 8 2 Channel Specification for DDT Mode DMA Transfer 562 14 8 3 Transfer Channel Notification in DDT Mode 562 14 8 4 Clearing Request Queues by DTR Format 563 14 8 5 Interrupt Request Codes 564 14 9 Usage Notes 567 Section 15 Serial Communication Interface SCI 569 15 1 Overvi...

Page 15: ...5 Serial Mode Register SCSMR2 639 16 2 6 Serial Control Register SCSCR2 641 16 2 7 Serial Status Register SCFSR2 644 16 2 8 Bit Rate Register SCBRR2 650 16 2 9 FIFO Control Register SCFCR2 651 16 2 10 FIFO Data Count Register SCFDR2 654 16 2 11 Serial Port Register SCSPTR2 655 16 2 12 Line Status Register SCLSR2 662 16 3 Operation 663 16 3 1 Overview 663 16 3 2 Serial Operation 664 16 4 SCIF Inter...

Page 16: ...CSPTR1 723 18 2 7 Serial Port Register SCSPTR2 725 Section 19 Interrupt Controller INTC 729 19 1 Overview 729 19 1 1 Features 729 19 1 2 Block Diagram 729 19 1 3 Pin Configuration 731 19 1 4 Register Configuration 731 19 2 Interrupt Sources 732 19 2 1 NMI Interrupt 732 19 2 2 IRL Interrupts 733 19 2 3 On Chip Peripheral Module Interrupts 735 19 2 4 Interrupt Exception Handling and Priority 736 19 ...

Page 17: ...0 2 11 Break Bus Cycle Register B BBRB 761 20 2 12 Break Control Register BRCR 761 20 3 Operation 763 20 3 1 Explanation of Terms Relating to Accesses 763 20 3 2 Explanation of Terms Relating to Instruction Intervals 764 20 3 3 User Break Operation Sequence 765 20 3 4 Instruction Access Cycle Break 766 20 3 5 Operand Access Cycle Break 767 20 3 6 Condition Match Flag Setting 768 20 3 7 Program Cou...

Page 18: ...uration Register 1 PCICONF1 812 22 2 3 PCI Configuration Register 2 PCICONF2 817 22 2 4 PCI Configuration Register 3 PCICONF3 819 22 2 5 PCI Configuration Register 4 PCICONF4 821 22 2 6 PCI Configuration Register 5 PCICONF5 823 22 2 7 PCI Configuration Register 6 PCICONF6 825 22 2 8 PCI Configuration Register 7 PCICONF7 to PCI Configuration Register 10 PCICONF10 827 22 2 9 PCI Configuration Regist...

Page 19: ...nt Interrupt Mask Register PCIPINTM 871 22 2 37 PCI Clock Control Register PCICLKR 872 22 2 38 PCIC BSC Registers 873 22 2 39 Port Control Register PCIPCTR 874 22 2 40 Port Data Register PCIPDTR 877 22 2 41 PIO Data Register PCIPDR 878 22 3 Description of Operation 879 22 3 1 Operating Modes 879 22 3 2 PCI Commands 880 22 3 3 PCIC Initialization 881 22 3 4 Local Register Access 882 22 3 5 Host Fun...

Page 20: ...aracteristics 948 23 3 1 Clock and Control Signal Timing 950 23 3 2 Control Signal Timing 961 23 3 3 Bus Timing 964 23 3 4 Peripheral Module Signal Timing 1015 23 3 5 AC Characteristic Test Conditions 1027 23 3 6 Change in Delay Time Based on Load Capacitance 1028 Appendix A Address List 1031 Appendix B Package Dimensions 1039 Appendix C Mode Pin Settings 1041 Appendix D Pin Functions 1044 D 1 Pin...

Page 21: ... 71 Figure 3 12 Operation of LDTLB Instruction 73 Figure 3 13 Memory Mapped ITLB Address Array 81 Figure 3 14 Memory Mapped ITLB Data Array 1 82 Figure 3 15 Memory Mapped ITLB Data Array 2 83 Figure 3 16 Memory Mapped UTLB Address Array 84 Figure 3 17 Memory Mapped UTLB Data Array 1 85 Figure 3 18 Memory Mapped UTLB Data Array 2 86 Figure 4 1 Cache and Store Queue Control Registers CCR 89 Figure 4...

Page 22: ... Figure 9 10 STATUS Output in Deep Sleep Power On Reset Sequence 236 Figure 9 11 STATUS Output in Deep Sleep Manual Reset Sequence 237 Figure 9 12 Hardware Standby Mode Timing When CA Low in Normal Operation 238 Figure 9 13 Hardware Standby Mode Timing When CA Low in WDT Operation 239 Figure 9 14 Timing When Power Other than VDD RTC is Off 239 Figure 9 15 Timing When VDD RTC Power is Off On 240 Fi...

Page 23: ...2 Figure 13 17 DRAM Bus Cycle EDO Mode RCD 0 AnW 0 TPC 1 383 Figure 13 18 Burst Access Timing in DRAM EDO Mode 384 Figure 13 19 1 DRAM Burst Bus Cycle RAS Down Mode Start Fast Page Mode RCD 0 Anw 0 385 Figure 13 19 2 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 0 Anw 0 386 Figure 13 19 3 DRAM Burst Bus Cycle RAS Down Mode Start EDO Mode RCD 0 Anw 0 387 Figure 13 19 4 DRAM Bur...

Page 24: ...for PCMCIA I O Card Interface 430 Figure 13 49 Wait Timing for PCMCIA I O Card Interface 431 Figure 13 50 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface 432 Figure 13 51 Example of 32 Bit Data Width MPX Connection 434 Figure 13 52 MPX Interface Timing 1 Single Read Cycle AnW 0 No External Wait 435 Figure 13 53 MPX Interface Timing 2 Single Read AnW 0 One External Wait Inserted 436 Figure ...

Page 25: ... 13 70 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle 453 Figure 13 71 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait 454 Figure 13 72 Waits between Access Cycles 456 Figure 13 73 Arbitration Sequence 459 Figure 14 1 Block Diagram of DMAC 466 Figure 14 2 DMAC Transfer Flowchart 485 Figure 14 3 Round Robin Mode 491 Figure 14 4 Example of Changes in Priority Order...

Page 26: ...M Auto Precharge Read Bus Cycle Burst RCD 1 CAS latency 3 TPC 3 526 Figure 14 27 Single Address Mode External Device Synchronous DRAM Longword Transfer SDRAM Auto Precharge Write Bus Cycle Burst RCD 1 TRWL 2 TPC 1 527 Figure 14 28 Dual Address Mode Synchronous DRAM SRAM Longword Transfer 528 Figure 14 29 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 O...

Page 27: ...t to Channel 2 543 Figure 14 50 Single Address Mode Burst Mode External Device External Bus Data Transfer Direct Data Transfer Request to Channel 2 544 Figure 14 51 Single Address Mode Burst Mode External Bus External Device Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 545 Figure 14 52 Single Address Mode Burst Mode External Device External Bus Data Transfer Active B...

Page 28: ... Reception 626 Figure 15 24 Receive Data Sampling Timing in Asynchronous Mode 630 Figure 15 25 Example of Synchronous Transmission by DMAC 631 Figure 16 1 Block Diagram of SCIF 635 Figure 16 2 MD8 RTS2 Pin 658 Figure 16 3 MD7 CTS2 Pin 659 Figure 16 4 MD1 TxD2 Pin 660 Figure 16 5 MD2 RxD2 Pin 660 Figure 16 6 MD0 SCK2 Pin 661 Figure 16 7 Sample SCIF Initialization Flowchart 667 Figure 16 8 Sample Se...

Page 29: ...hart 772 Figure 21 1 Block Diagram of H UDI Circuit 778 Figure 21 2 TAP Control State Transition Diagram 798 Figure 21 3 H UDI Reset 799 Figure 22 1 PCIC Block Diagram 803 Figure 22 2 PIO Memory Space Access 887 Figure 22 3 PIO I O Space Access 888 Figure 22 4 Local Address Space Accessing Method 889 Figure 22 5 Example of DMA Transfer Control Register Settings 893 Figure 22 6 Example of DMA Trans...

Page 30: ...on Settling Time in Case of IRL Interrupt 960 Figure 23 11 Control Signal Timing 963 Figure 23 12 Pin Drive Timing for Standby Mode 963 Figure 23 13 SRAM Bus Cycle Basic Bus Cycle No Wait 968 Figure 23 14 SRAM Bus Cycle Basic Bus Cycle One Internal Wait 969 Figure 23 15 SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait 970 Figure 23 16 SRAM Bus Cycle Basic Bus Cycle No Wait Addres...

Page 31: ... 2 0 000 TPC 2 0 001 2 RCD 1 0 01 AnW 2 0 001 TPC 2 0 010 991 Figure 23 36 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 992 Figure 23 37 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 993 Figure 23 38 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 994 Figure 23 39 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cycle CAS Negate Pulse W...

Page 32: ...3 55 MPX Bus Cycle Burst Read 1 1st Data One Internal Wait 2nd to 8th Data One Internal Wait 2 1st Data One Internal Wait 2nd to 8th Data One Internal Wait One External Wait 1011 Figure 23 56 MPX Bus Cycle Burst Write 1 No Internal Wait 2 1st Data One Internal Wait 2nd to 8th Data No Internal Wait External Wait Control 1012 Figure 23 57 Memory Byte Control SRAM Bus Cycles 1 Basic Read Cycle No Wai...

Page 33: ...5 Figure 23 71 Output Signal Timing 1025 Figure 23 72 Output Signal Timing 1026 Figure 23 73 I O Port Input Output Timing 1027 Figure 23 74 Output Load Circuit 1028 Figure 23 75 Load Capacitance Delay Time 1029 Figure B 1 Package Dimensions 256 pin QFP 1039 Figure B 2 Package Dimensions 256 pin BGA 1040 Figure F 1 Instruction Prefetch 1061 Figure G 1 Power On and Power Off Procedures 1062 ...

Page 34: ...ation Instructions 178 Table 7 6 Shift Instructions 179 Table 7 7 Branch Instructions 180 Table 7 8 System Control Instructions 181 Table 7 9 Floating Point Single Precision Instructions 183 Table 7 10 Floating Point Double Precision Instructions 184 Table 7 11 Floating Point Control Instructions 184 Table 7 12 Floating Point Graphics Acceleration Instructions 185 Table 8 1 Instruction Groups 194 ...

Page 35: ...us DRAM Address Pins 32 Bit Bus Width AMX2 AMX0 000 AMXEXT 0 395 Table 13 16 Cycles in Which Pipelined Access Can Be Used 409 Table 13 17 Relationship between Address and CE When Using PCMCIA Interface 424 Table 14 1 DMAC Pins 467 Table 14 2 DMAC Pins in DDT Mode 468 Table 14 3 DMAC Registers 468 Table 14 4 Selecting External Request Mode with RS Bits 487 Table 14 5 Selecting On Chip Peripheral Mo...

Page 36: ...fer Formats 665 Table 16 6 SCIF Interrupt Sources 675 Table 17 1 Smart Card Interface Pins 681 Table 17 2 Smart Card Interface Registers 681 Table 17 3 Smart Card Interface Register Settings 689 Table 17 4 Values of n and Corresponding CKS1 and CKS0 Settings 691 Table 17 5 Examples of Bit Rate B bits s for Various SCBRR1 Settings When n 0 692 Table 17 6 Examples of SCBRR1 Settings for Bit Rate B b...

Page 37: ...C Characteristics HD6417751RF200 936 Table 23 6 DC Characteristics HD6417751BP167 938 Table 23 7 DC Characteristics HD6417751BP167I 940 Table 23 8 DC Characteristics HD6417751F167 942 Table 23 9 DC Characteristics HD6417751F167I 944 Table 23 10 DC Characteristics HD6417751VF133 946 Table 23 11 Permissible Output Currents 948 Table 23 12 Clock Timing HD6417751RBP240 948 Table 23 13 Clock Timing HD6...

Page 38: ...g With PCIREQ PCIGNT Port Settings in Non Host Mode 1027 Table A 1 Address List 1031 Table C 1 Clock Operating Modes SH7751 1041 Table C 2 Clock Operating Modes SH7751R 1041 Table C 3 Area 0 Memory Map and Bus Width 1042 Table C 4 Endian 1042 Table C 5 Master Slave 1042 Table C 6 Clock Input 1042 Table C 7 PCI Mode 1043 Table D 1 Pin States in Reset Power Down State and Bus Released State PCI Enab...

Page 39: ...Rev 3 0 04 02 page xxxviii of xxxviii ...

Page 40: ...and SH 3 microcomputers The SH7751 Series have an instruction cache an operand cache that can be switched between copy back and write through modes a 4 entry full associative instruction TLB table look aside buffer and MMU memory management unit with 64 entry full associative shared TLB The SH7751 Series also feature a bus state controller BSC that can be directly coupled to DRAM page EDO and sync...

Page 41: ...PS 167 MHz 0 93 GFLOPS 133 MHz 1 7 GFLOPS 240 MHz 1 4 GFLOPS 200 MHz Superscalar architecture Parallel execution of two instructions Packages 256 pin QFP 256 pin BGA External buses SH buses Separate 26 bit address and 32 bit data buses External bus frequency of 1 1 2 1 3 1 4 1 6 or 1 8 times internal bus frequency External bus PCI bus 32 bit address data multiplexing Selection of internal clock or...

Page 42: ...uction set upward compatible with SuperH Series Fixed 16 bit instruction length for improved code efficiency Load store architecture Delayed branch instructions Conditional execution C based instruction set Superscalar architecture providing simultaneous execution of two instructions including FPU Instruction execution time Maximum 2 instructions cycle Virtual address space 4 Gbytes 448 Mbyte exte...

Page 43: ...words 2 banks 32 bit CPU FPU floating point communication register FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constant 0 1 instructions Instruction execution times Latency FMAC FADD FSUB FMUL 3 cycles single precision 8 cycles double precision Pitch FMAC FADD FSUB FMUL 1 cycle single precision 6 cycles do...

Page 44: ...clock Power down modes Sleep mode Deep sleep mode Pin sleep mode Standby mode Hardware standby mode Module standby function Single channel watchdog timer Memory management unit MMU 4 Gbyte address space 256 address space identifiers 8 bit ASIDs Single virtual mode and multiple virtual memory mode Supports multiple page sizes 1 kbyte 4 kbytes 64 kbytes 1 Mbyte 4 entry fully associative TLB for inst...

Page 45: ...by address mapping usable as on chip memory Store queue 32 bytes 2 entries Cache memory SH7751R Instruction cache IC 16 kbytes 2 way set associative 256 entries way 32 byte block length Cache double mode 16 kbyte cache Index mode SH7751 compatible mode 8 kbytes direct mapping Operand cache OC 32 kbytes 2 way set associative 512 entries way 32 byte block length Cache double mode 32 kbyte cache Inde...

Page 46: ...state controller BSC Supports external memory access 32 16 8 bit external data bus External memory space divided into seven areas each of up to 64 Mbytes with the following parameters settable for each area Bus size 8 16 or 32 bits Number of wait cycles hardware wait function also supported Direct connection of DRAM synchronous DRAM and burst ROM possible by setting space type Supports fast page m...

Page 47: ...e external bus 32 bit Timer unit TMU 5 channel auto reload 32 bit timer Input capture function on one channel Selection from 7 counter input clocks in 3 of 5 channels and from 5 counter input clocks on remaining 2 of 5 channels Realtime clock RTC On chip clock and calendar functions Built in 32 kHz crystal oscillator with maximum 1 256 second resolution cycle interrupts Serial communication interf...

Page 48: ... byte FIFO Selection of built in clock or external PCI dedicated clock Interrupt requests can be sent to CPU Product lineup Abbreviation Voltage Operating Frequency Model No Package SH7751 1 8 V 167 MHz HD6417751BP167 256 pin BGA HD6417751F167 256 pin QFP 1 5 V 133 MHz HD6417751VF133 SH7751R 1 5 V 240 MHz HD6417751RBP240 256 pin BGA HD6417751RF240 256 pin QFP 200 MHz HD6417751RBP200 256 pin BGA HD...

Page 49: ... data 32 bit SH bus data Peripheral data bus UBC 32 bit data store 32 bit data load CPU I cache O cache ITLB UTLB Cache and TLB controller FPU BSC Bus state controller CPG Clock pulse generator DMAC Direct memory access controller FPU Floating point unit INTC Interrupt controller ITLB Instruction TLB translation lookaside buffer UTLB Unified TLB translation lookaside buffer RTC Realtime clock SCI ...

Page 50: ... D18 D17 D16 DQM3 DQM2 A17 A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TMS TCK TDI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DQM0 DQM1 RD CKIO Reserved Reserved CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 192 191 190 189 188 187 18...

Page 51: ...DD internal VSS internal NC VSS PLL1 2 VDD PLL1 2 VDD CPG RTC VSS CPG RTC Note Power must be supplied to the on chip PLL power supply pins VDD PLL1 VDD PLL2 VSS PLL1 VSS PLL2 VDD CPG VSS CPG VDD RTC and VSS RTC regardless of whether or not the PLL circuits crystal resonator and RTC are used May be connected to VSSQ Figure 1 3 Pin Arrangement 256 Pin BGA ...

Page 52: ...D 4 VSSQ Power IO GND 5 TDI I Data in H UDI 6 O Chip select 0 7 O Chip select 1 8 O Chip select 4 9 O Chip select 5 10 O Chip select 6 11 O Bus start 12 O D7 D0 select signal 13 O D15 D8 select signal 14 D0 I O Data A0 15 VDDQ Power IO VDD 16 VSSQ Power IO GND 17 VDD Power Internal VDD 18 VSS Power Internal GND 19 D1 I O Data A1 20 D2 I O Data A2 21 D3 I O Data A3 22 D4 I O Data A4 23 D5 I O Data ...

Page 53: ...A13 34 D14 I O Data A14 35 D15 I O Data A15 36 DQM0 O D7 D0 select signal DQM0 37 DQM1 O D15 D8 select signal DQM1 38 RD O Read write RD RD RD 39 CKIO O Clock output CKIO 40 Reserved Do not connect 41 VDDQ Power IO VDD 42 VSSQ Power IO GND 43 Reserved Do not connect 44 O Read 45 CKE O Clock output enable CKE 46 O 47 VDD Power Internal VDD 48 VSS Power Internal GND 49 O Chip select 2 50 O Chip sele...

Page 54: ...Address 65 A12 O Address 66 A13 O Address 67 VDDQ Power IO VDD 68 VSSQ Power IO GND 69 A14 O Address 70 A15 O Address 71 A16 O Address 72 A17 O Address 73 DQM2 O D23 D16 select signal DQM2 74 DQM3 O D31 D24 select signal DQM3 75 D16 I O Data A16 76 D17 I O Data A17 77 D18 I O Data A18 78 D19 I O Data A19 79 VDDQ Power IO VDD 80 VSSQ Power IO GND 81 VDD Power Internal VDD 82 VSS Power Internal GND ...

Page 55: ...er IO GND 95 D30 I O Data ACCSIZE1 96 D31 I O Data ACCSIZE2 97 VDD Power Internal VDD 98 VSS Power Internal GND 99 A18 O Address 100 A19 O Address 101 A20 O Address 102 A21 O Address 103 A22 O Address 104 A23 O Address 105 VDDQ Power IO VDD 106 VSSQ Power IO GND 107 A24 O Address 108 A25 O Address 109 O D23 D16 select signal 110 O D31 D24 select signal 111 VDD Power Internal VDD 112 VSS Power Inte...

Page 56: ...ND 121 MD9 I Bus request host function mode MD9 122 IDSEL I Configuration device select 123 O Interrupt async 124 O Reset output 125 PCICLK I PCI input clock 126 O Bus grant host function bus request 127 I Bus request host function bus grant 128 I O System error 129 AD31 I O PCI address data port Port Port Port Port Port 130 AD30 I O PCI address data port Port Port Port Port Port 131 VDDQ Power IO...

Page 57: ...0 AD23 I O PCI address data port Port Port Port Port Port 141 AD22 I O PCI address data port Port Port Port Port Port 142 AD21 I O PCI address data port Port Port Port Port Port 143 VDDQ Power IO VDD 144 VSSQ Power IO GND 145 VDD Power Internal VDD 146 VSS Power Internal GND 147 AD20 I O PCI address data port Port Port Port Port Port 148 AD19 I O PCI address data port Port Port Port Port Port 149 ...

Page 58: ...ort Port Port Port 166 AD13 I O PCI address data port Port Port Port Port Port 167 AD12 I O PCI address data port Port Port Port Port Port 168 AD11 I O PCI address data port Port Port Port Port Port 169 VDDQ Power IO VDD 170 VSSQ Power IO GND 171 AD10 I O PCI address data port Port Port Port Port Port 172 AD9 I O PCI address data port Port Port Port Port Port 173 AD8 I O PCI address data port Port...

Page 59: ...t Port Port Port Port Port 183 VDDQ Power I O VDD 184 VSSQ Power I O GND 185 AD1 I O PCI address data port Port Port Port Port Port 186 AD0 I O PCI address data port Port Port Port Port Port 187 I Interrupt 0 188 I Interrupt 1 189 I Interrupt 2 190 I Interrupt 3 191 VSSQ Power I O GND 192 VDDQ Power I O VDD 193 XTAL2 O RTC crystal resonator pin 194 EXTAL2 I RTC crystal resonator pin 195 VDD RTC Po...

Page 60: ...wer Internal VDD 210 VSS Power Internal GND 211 MD2 RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 212 RXD I SCI data input 213 TCLK I O RTC TMU clock 214 MD8 I O Mode SCIF data control RTS MD8 215 SCK I O SCIF clock 216 MD1 TXD2 I O Mode SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 MD0 SCK2 I O Mode SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 MD7 I O Mode SCIF data control CTS MD7 ...

Page 61: ... Mode PCMCIA CE MD3 231 MD4 I O Mode PCMCIA CE MD4 232 MD5 I Mode MD5 233 VDDQ Power IO VDD 234 VSSQ Power IO GND 235 DACK0 O DMAC0 bus acknowledge 236 DACK1 O DMAC1 bus acknowledge 237 DRAK0 O DMAC0 request acknowledge 238 DRAK1 O DMAC1 request acknowledge 239 VDD Power Internal VDD 240 VSS Power Internal GND 241 STATUS0 O Status 242 STATUS1 O Status 243 I Request from DMAC0 244 I Request from DM...

Page 62: ...Output I O Input output Power Power supply Notes 1 Except in hardware standby mode supply power to all power pins In hardware standby mode supply power to RTC as a minimum 2 Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used 3 Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal resonator is u...

Page 63: ...1 O Chip select 0 7 C2 O Chip select 1 8 C1 O Chip select 4 9 D3 O Chip select 5 10 D2 O Chip select 6 11 D1 O Bus start 12 E4 O D7 D0 select signal 13 E3 O D15 D8 select signal 14 E2 D0 I O Data A0 15 G2 VDDQ Power IO VDD 16 L4 VSSQ Power IO GND 17 G4 VDD Power Internal VDD 18 F4 VSS Power Internal GND 19 E1 D1 I O Data A1 20 F3 D2 I O Data A2 21 F1 D3 I O Data A3 22 G1 D4 I O Data A4 23 H4 D5 I ...

Page 64: ...K1 D15 I O Data A15 36 L2 DQM0 O D7 D0 select signal DQM0 37 M4 DQM1 O D15 D8 select signal DQM1 38 M3 RD O Read write RD RD RD 39 M1 CKIO O Clock output CKIO 40 M2 NC Do not connect 41 P3 VDDQ Power IO VDD 42 L1 VSSQ Power IO GND 43 N3 NC Do not connect 44 P1 O Read 45 N2 CKE O Clock output enable CKE 46 N1 O 47 P4 VDD Power Internal VDD 48 R4 VSS Power Internal GND 49 N4 O Chip select 2 50 R3 O ...

Page 65: ...A12 O Address 66 Y2 A13 O Address 67 V7 VDDQ Power IO VDD 68 V3 VSSQ Power IO GND 69 W3 A14 O Address 70 Y3 A15 O Address 71 V4 A16 O Address 72 W4 A17 O Address 73 Y4 DQM2 O D23 D16 select signal DQM2 74 U5 DQM3 O D31 D24 select signal DQM3 75 V5 D16 I O Data A16 76 W5 D17 I O Data A17 77 Y5 D18 I O Data A18 78 V6 D19 I O Data A19 79 W7 VDDQ Power IO VDD 80 W2 VSSQ Power IO GND 81 U7 VDD Power In...

Page 66: ... Data ACCSIZE1 96 Y10 D31 I O Data ACCSIZE2 97 U10 VDD Power Internal VDD 98 U11 VSS Power Internal GND 99 V11 A18 O Address 100 Y11 A19 O Address 101 U12 A20 O Address 102 V12 A21 O Address 103 W12 A22 O Address 104 Y12 A23 O Address 105 V14 VDDQ Power IO VDD 106 W11 VSSQ Power IO GND 107 U13 A24 O Address 108 V13 A25 O Address 109 W13 O D23 D16 select signal 110 Y13 O D31 D24 select signal 111 U...

Page 67: ...iguration device select 123 V17 O Interrupt async 124 W17 O Reset output 125 Y17 PCICLK I PCI input clock 126 W18 O Bus grant host function bus request 127 Y18 I Bus request host function bus grant 128 Y19 I O System error 129 Y20 AD31 I O PCI address data port Port Port Port Port Port 130 W20 AD30 I O PCI address data port Port Port Port Port Port 131 P18 VDDQ Power IO VDD 132 V18 VSSQ Power IO G...

Page 68: ...rt Port Port Port Port 142 T19 AD21 I O PCI address data port Port Port Port Port Port 143 N19 VDDQ Power IO VDD 144 W19 VSSQ Power IO GND 145 P17 VDD Power Internal VDD 146 R17 VSS Power Internal GND 147 R20 AD20 I O PCI address data port Port Port Port Port Port 148 P20 AD19 I O PCI address data port Port Port Port Port Port 149 P19 AD18 I O PCI address data port Port Port Port Port Port 150 N20...

Page 69: ...Port Port Port Port Port 167 J17 AD12 I O PCI address data port Port Port Port Port Port 168 H20 AD11 I O PCI address data port Port Port Port Port Port 169 G18 VDDQ Power IO VDD 170 K17 VSSQ Power IO GND 171 H19 AD10 I O PCI address data port Port Port Port Port Port 172 G20 AD9 I O PCI address data port Port Port Port Port Port 173 H18 AD8 I O PCI address data port Port Port Port Port Port 174 H...

Page 70: ...O GND 185 D19 AD1 I O PCI address data port Port Port Port Port Port 186 D18 AD0 I O PCI address data port Port Port Port Port Port 187 E17 I Interrupt 0 188 C20 I Interrupt 1 189 C19 I Interrupt 2 190 B20 I Interrupt 3 191 B18 NC Do not connect 2 192 D17 VDDQ Power I O VDD 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD RTC Power RTC VDD 196 B19 VS...

Page 71: ... RXD2 I Mode SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2 212 C13 RXD I SCI data input 213 B13 TCLK I O RTC TMU clock 214 A13 MD8 I O Mode SCIF data control RTS MD8 215 D12 SCK I O SCIF clock 216 B11 MD1 TXD2 I O Mode SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 C12 MD0 SCK2 I O Mode SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 A12 MD7 I O Mode SCIF data control CTS MD7 219 B12 AUDSYNC AUD syn...

Page 72: ...DDQ Power IO VDD 234 C17 VSSQ Power IO GND 235 B8 DACK0 O DMAC0 bus acknowledge 236 A8 DACK1 O DMAC1 bus acknowledge 237 B7 DRAK0 O DMAC0 request acknowledge 238 A7 DRAK1 O DMAC1 request acknowledge 239 D7 VDD Power Internal VDD 240 D6 VSS Power Internal GND 241 C6 STATUS0 O Status 242 B6 STATUS1 O Status 243 A6 I Request from DMAC0 244 C5 I Request from DMAC1 245 D5 BRKACK I O Pin break acknowled...

Page 73: ... supply Notes 1 Except in hardware standby mode supply power to all power pins In hardware standby mode supply power to RTC as a minimum 2 Power must be supplied to VDD PLL1 2 and VSS PLL1 2 regardless of whether or not the on chip PLL circuits are used 3 Power must be supplied to VDD CPG and VSS CPG regardless of whether or not the on chip crystal resonator is used 4 Power must be supplied to VDD...

Page 74: ...e data formats handled by the SH7751 Series are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 fraction exp s 0 63 62 51 exp s fraction Figure 2 1 Data Formats ...

Page 75: ...ANK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC STC instruc...

Page 76: ... XMTRX Register values after a reset are shown in table 2 1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0_BANK0 R7_BANK0 R0_BANK1 R7_BANK1 R8 R15 Undefined SR MD bit 1 RB bit 1 BL bit 1 FD bit 0 I3 I0 1111 H F reserved bits 0 others undefined GBR SSR SPC SGR DBR Undefined Control registers VBR H 00000000 MACH MACL PR FPUL Undefined PC H A0000000 System registe...

Page 77: ..._BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR Notes 1 The R0 register is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode 2 Banked registers 3...

Page 78: ...ed as general registers R0 R15 in one processor mode The SH7751 Series has two processor modes user mode and privileged mode in which R0 R7 are assigned as shown below R0_BANK0 R7_BANK0 In user mode SR MD 0 R0 R7 are always assigned to R0_BANK0 R7_BANK0 In privileged mode SR MD 1 R0 R7 are assigned to R0_BANK0 R7_BANK0 only when SR RB 0 R0_BANK1 R7_BANK1 In user mode R0_BANK1 R7_BANK1 cannot be ac...

Page 79: ...ANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 SR MD 1 SR RB 1 Figure 2 3 General Registers Programming Note As the user s R0 R7 are assigned to R0_BANK0 R7_BANK0 and after an exception or interrupt R0 R7 are assigned to R0_BANK1 R7_BANK1 it is not necessary for the interrupt handler to save an...

Page 80: ...1 FPR15_BANK1 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 FR15 are assigned to FPR0_BANK0 FPR15_BANK0 When FPSCR FR 1 FR0 FR15 are assigned to FPR0_BANK1 FPR15_BANK1 Double precision floating point registers or single precision floating point register pairs DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR...

Page 81: ...3 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF1...

Page 82: ...K1 can be accessed using LDC STC instructions RB 1 R0_BANK1 R7_BANK1 are accessed as general registers R0 R7 R0_BANK0 R7_BANK0 can be accessed using LDC STC instructions BL Exception interrupt block bit set to 1 by a reset exception or interrupt BL 1 Interrupt requests are masked If a general exception other than a user break occurs while BL 1 the processor switches to the reset state FD FPU disab...

Page 83: ...privilege protection initial value undefined The contents of R15 are saved to SGR in the event of an exception or interrupt Debug base register DBR 32 bits privilege protection initial value undefined When the user break debug function is enabled BRCR UBDE 1 DBR is referenced as the user break handler branch destination address instead of VBR 2 2 5 System Registers Multiply and accumulate register...

Page 84: ...PR 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operations the result of instructions for which double precision is not supported is undefined Do not set SZ and PR to 1 simultaneously this setting is reserved SZ PR 11 Reserved FPU operation instruction is undefined DN Denormalization mode DN 0 A denormal...

Page 85: ...ouble precision floating point data 2 3 Memory Mapped Registers Appendix A shows the control registers mapped to memory The control registers are double mapped to the following two memory areas All registers have two addresses H 1C00 0000 H 1FFF FFFF H FC00 0000 H FFFF FFFF These two areas are used as follows H 1C00 0000 H 1FFF FFFF This area must be accessed using the address translation function...

Page 86: ... rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be selected for the data format The endian should be set with the MD5 external pin in a power on reset Big endian is selected when the MD5 pin is low and little endian when high The endian cannot be changed dynamically Bit positions are numbered left to right from most significant to le...

Page 87: ...xception Handling State This is a transient state during which the CPU s processor state flow is altered by a reset general exception or interrupt exception source In the case of a reset the CPU branches to address H A000 0000 and starts executing the user coded exception handling program In the case of a general exception or interrupt the program counter PC contents are saved in the saved program...

Page 88: ...m any state when RESET 0 From any state when RESET 1 and MRESET 0 Reset state Power down state Bus request Bus request Standby mode Sleep mode Figure 2 6 Processor State Transitions 2 7 Processor Modes There are two processor modes user mode and privileged mode The processor mode is determined by the processor mode bit MD in the status register SR User mode is selected when the MD bit is cleared t...

Page 89: ...Rev 3 0 04 02 page 50 of 1064 ...

Page 90: ...ring execution onto physical memory on an ad hoc basis 1 Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 With a virtual memory system the size of the available virtual memory is much larger than the actual physica...

Page 91: ...requently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally performed by software Thus memory management can be performed in a flexible manner by software There are two methods by wh...

Page 92: ...cess 1 Process 1 Physical memory Process 1 Process 2 Process 3 Virtual memory Process 1 Process 1 Process 2 Process 3 MMU MMU 4 3 1 Physical memory Physical memory Physical memory Physical memory Virtual memory Figure 3 1 Role of the MMU ...

Page 93: ...0034 H 1F00 0034 32 Translation table base register TTB R W Undefined H FF00 0008 H 1F00 0008 32 TLB exception address register TEA R W Undefined H FF00 000C H 1F00 000C 32 MMU control register MMUCR R W H 0000 0000 H FF00 0010 H 1F00 0010 32 Notes 1 The initial value is the value after a power on reset or manual reset 2 P4 address is the address when using the virtual physical address space P4 ar...

Page 94: ... 5 4 3 2 1 0 V SZ PR SZ C D SH WT 2 PTEL 31 4 3 2 0 TC SA 3 PTEA 31 0 0 TTB 4 TTB 31 Virtual address at which MMU exception or address error occurred 5 TEA 31 26 24 23 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 LRUI URC SQMD SV TI AT 6 MMUCR indicates a reserved bit the write value must be 0 and a read will return 0 URB 25 Figure 3 2 MMU Related Registers ...

Page 95: ...e directive is issued 3 Page table entry assistance register PTEA Longword access to PTEA can be performed from H FF00 0034 in the P4 area and H 1F00 0034 in area 7 PTEA is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction When performing PCMCIA access with the MMU off access is always performed using the values of the SA and TC bits in this register Acc...

Page 96: ... of an ITLB miss The entry to be purged from the ITLB can be confirmed using the LRUI bits LRUI is updated by means of the algorithm shown below A dash in this table means that updating is not performed LRUI 5 4 3 2 1 0 When ITLB entry 0 is used 0 0 0 When ITLB entry 1 is used 1 0 0 When ITLB entry 2 is used 1 1 0 When ITLB entry 3 is used 1 1 1 Other than the above When the LRUI bit settings are ...

Page 97: ...s bit invalidates clears to 0 all valid UTLB ITLB bits This bit always returns 0 when read AT Address translation enable bit Specifies MMU enabling or disabling 0 MMU disabled 1 MMU enabled MMU exceptions are not generated when the AT bit is 0 In the case of software that does not use the MMU therefore the AT bit should be cleared to 0 3 3 Address Space 3 3 1 Physical Address Space The SH7751 Seri...

Page 98: ... P1 P3 U0 Areas The P0 P1 P3 and U0 areas can be accessed using the cache Whether or not the cache is used is determined by the cache control register CCR When the cache is used with the exception of the P1 area switching between the copy back method and the write through method for write accesses is specified by the CCR WT bit For the P1 area switching is specified by the CCR CB bit Zeroizing the...

Page 99: ... store queues SQs When the MMU is disabled MMUCR AT 0 the SQ access right is specified by the MMUCR SQMD bit For details see section 4 7 Store Queues The area from H F000 0000 to H F0FF FFFF is used for direct access to the instruction cache address array For details see section 4 5 1 IC Address Array The area from H F100 0000 to H F1FF FFFF is used for direct access to the instruction cache data ...

Page 100: ...a arrays 1 and 2 For details see sections 3 7 5 UTLB Data Array 1 and 3 7 6 UTLB Data Array 2 The area from H FC00 0000 to H FFFF FFFF is the on chip peripheral module control register area For details see appendix A Address List 3 3 2 External Memory Space The SH7751 Series supports a 29 bit external memory space The external memory space is divided into eight areas as shown in figure 3 5 Areas 0...

Page 101: ... register area in the physical address space Virtual address space is illustrated in figure 3 6 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External memory space 256 256 U0 area Cacheable Address translation possible Address error Address error Store queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cacheable Address translation not possible P2...

Page 102: ... using the TLB cannot be performed for the P1 P2 or P4 area except for the store queue area Accesses to these areas are the same as for physical address space The store queue area can be mapped onto any external memory space by the MMU However operation in the case of an exception differs from that for normal P0 U0 and P3 spaces For details see section 4 7 Store Queues 3 3 4 On Chip RAM Space In t...

Page 103: ...nt physical addresses depending on the process The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method see section 3 4 3 Address Translation Method 3 3 7 Address Space Identifier ASID In multiple virtual memory mode the 8 bit address space identifier ASID is used to distinguish between processes running...

Page 104: ...table located in external memory is cached into the UTLB The address translation table contains virtual page numbers and address space identifiers and corresponding physical page numbers and page management information Figure 3 7 shows the overall configuration of the UTLB The UTLB consists of 64 fully associative type entries Figure 3 8 shows the relationship between the address format and page s...

Page 105: ...n Page Size and Address Format VPN Virtual page number For 1 kbyte page upper 22 bits of virtual address For 4 kbyte page upper 20 bits of virtual address For 64 kbyte page upper 16 bits of virtual address For 1 Mbyte page upper 12 bits of virtual address ASID Address space identifier Indicates the process that can access a virtual page In single virtual memory mode and user mode or in multiple vi...

Page 106: ...yte page PPN bits 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 3 5 5 Avoiding Synonym Problems PR Protection key data 2 bit data expressing the page access right as a code 00 Can be read only in privileged mode 01 Can be read and written in privileged mode 10 Can be read only in privileged or user mode 11 Can be read and written in privileged mode...

Page 107: ...e bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6 000 Undefined 001 Variable size I O space base size according to signal 010 8 bit I O space 011 16 bit I O space 100 8 bit common memory space 101 16 bit common memory space 110 8 bit attribute memory space 111 16 bit attribute memory space TC Timing control bit Used to select wait control register bits in the bus contr...

Page 108: ...mation is almost the same as that in the UTLB but with the following differences 1 D and WT bits are not supported 2 There is only one PR bit corresponding to the upper of the PR bits in the UTLB PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 VPN 31 10 V V V V Entry 0 Entry 1 Entr...

Page 109: ...eption Data TLB miss exception Initial page write exception Data TLB protection violation exception Cache access in copy back mode Data access to virtual address VA On chip I O access R W R W VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 0 Yes Yes No No Yes Yes Yes No No 1 Privileged 1 0 0 PR 0 User D R W W W W R R R R W R W Non cacheable WT C 1 and CCR OCE ...

Page 110: ...miss exception Instruction access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes No 1 0 Yes Yes No No Yes Yes No Non cacheable C 1 and CCR ICE 1 No PR Instruction TLB protection violation exception Match Record in ITLB Access prohibited 0 1 No Yes Yes No Hardware ITLB miss handling 0 User 1 Privileged Search UTLB Cache access Figure 3 11 Flow...

Page 111: ...1 Setting of MMU related registers Some registers are also partially updated by hardware automatically 2 Recording deletion and reading of TLB entries There are two methods of recording UTLB entries by using the LDTLB instruction or by writing directly to the memory mapped UTLB ITLB entries can only be recorded by writing directly to the memory mapped ITLB For deleting or reading UTLB ITLB entries...

Page 112: ...UI URB URC SV SQMD TI AT MMUCR VPN 10 PPN 31 4 3 2 0 SA TC PTEA Entry specification Figure 3 12 Operation of LDTLB Instruction 3 5 4 Hardware ITLB Miss Handling In an instruction access the SH7751 Series searches the ITLB If it cannot find the necessary address translation information i e in the event of an ITLB miss the UTLB is searched by hardware and if the necessary address translation informa...

Page 113: ...address translation information in UTLB entries 1 When address translation information whereby a number of 1 kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensure that the VPN 13 10 values are the same 2 When address translation information whereby a number of 4 kbyte page UTLB entries are translated into the same physical address is recorded in the U...

Page 114: ...xception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardware carries out the following processing 1 Sets the virtual address at which the exception occurred in TEA 2 Sets exception code H 140 in EXPEVT 3 Branches to the reset handling routine H A000 0000 Software Processing Reset Routine The ITLB en...

Page 115: ...y Software should carry out the following processing in order to find and assign the necessary page table entry 1 Write to PTEL the values of the PPN PR SZ C D SH V and WT bits in the page table entry recorded in the external memory address translation table If necessary the values of the SA and TC bits should be written to PTEA 2 When the entry to be replaced in entry replacement is specified by ...

Page 116: ...outine Resolve the instruction TLB protection violation execute the exception handling return instruction RTE terminate the exception handling routine and return control to the normal flow The RTE instruction should be issued at least one instruction after the LDTLB instruction 3 6 4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the ...

Page 117: ...n SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the data TLB miss exception handling routine Software Processing Data TLB Miss Exception Handling Routine Software is responsible for searching the external memory page table and assigning the necessary page table entry Sof...

Page 118: ...in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0100 to the contents of VBR and starts the data TLB protection violation exception handling routine Software Processing Data TLB...

Page 119: ...n entry replacement is specified by software write that value to URC in the MMUCR register If URC is greater than URB at this time the value should be changed to an appropriate value after issuing an LDTLB instruction 5 Execute the LDTLB instruction and write the contents of PTEH PTEL and PTEA to the UTLB 6 Finally execute the exception handling return instruction RTE terminate the exception handl...

Page 120: ...ITLB address array and the entry is selected by bits 9 8 As longword access is used 0 should be specified for address field bits 1 0 In the data field VPN is indicated by bits 31 10 V by bit 8 and ASID by bits 7 0 The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the ...

Page 121: ...ndicated by bits 28 10 V by bit 8 SZ by bits 7 and 4 PR by bit 6 C by bit 3 and SH by bit 1 The following two kinds of operation can be used on ITLB data array 1 1 ITLB data array 1 read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array 1 write PPN V SZ PR C and SH specified in the data field are written to t...

Page 122: ... SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field Address field 31 23 0 1 1 1 1 0 0 1 1 1 E Data field 31 4 0 TC E 24 Timing control bit Entry 8 9 7 3 2 SA Space attribute bits Reserved bits 0...

Page 123: ...rite is performed with the A bit in the address field set to 1 comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH ASID The usual address comparison rules are followed but if a UTLB miss occurs the result is no operation and an exception is not generated If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field D...

Page 124: ...SZ by bits 7 and 4 PR by bits 6 5 C by bit 3 D by bit 2 SH by bit 1 and WT by bit 0 The following two kinds of operation can be used on UTLB data array 1 1 UTLB data array 1 read PPN V SZ PR C D SH and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field 2 UTLB data array 1 write PPN V SZ PR C D SH and WT specified in the data field are written to...

Page 125: ...ing UTLB data array 2 and the entry is selected by bits 13 8 In the data field TC is indicated by bit 3 and SA by bits 2 0 The following two kinds of operation can be used on UTLB data array 2 1 UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field 2 UTLB data array 2 write SA and TC specified in the data field are wri...

Page 126: ...t in the CCR register is cleared to 0 in the SH7751R both the IC and OC are set to SH7751 compatible mode Operation is as shown in table 4 1 When the EMODE bit in the CCR register is set to 1 the cache characteristics are as shown in table 4 2 After a power on reset or manual reset the initial value of the EMODE bit is 0 The SH7751 Series supports two 32 byte store queues SQs for performing high s...

Page 127: ...tion PREF instruction Access right MMU off according to MMUCR SQMD MMU on according to individual page PR 4 1 2 Register Configuration Table 4 4 shows the cache control registers Table 4 4 Cache Control Registers Name Abbreviation R W Initial Value 1 P4 Address 2 Area 7 Address 2 Access Size Cache control register CCR R W H 0000 0000 H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR...

Page 128: ...d bit in SH7751 IIX IC index enable ICI IC invalidation ICE IC enable OIX OC index enable ORA OC RAM enable OCI OC invalidation CB Copy back enable WT Write through enable OCE OC enable CCR can be accessed by longword size access from H FF00001C in the P4 area and H 1F00001C in area 7 The CCR bits are used for the cache settings described below Consequently CCR modifications must only be made by a...

Page 129: ...s to be used When address translation is performed the IC cannot be used unless the C bit in the page management information is also 1 0 IC not used 1 IC used OIX OC index enable bit 2 0 Effective address bits 13 5 used for OC entry selection 1 Effective address bits 25 and 12 5 used for OC entry selection Note 2 In the SH7751R clear the OIX bit to 0 when the ORA bit is 1 ORA OC RAM enable bit 3 W...

Page 130: ...ess from H FF000038 in the P4 area and H 1F000038 in area 7 QACR0 specifies the area onto which store queue 0 SQ0 is mapped when the MMU is off 3 Queue Address Control Register 1 QACR1 QACR1 can be accessed by longword size access from H FF00003C in the P4 area and H 1F00003C in area 7 QACR1 specifies the area onto which store queue 1 SQ1 is mapped when the MMU is off 4 3 Operand Cache OC 4 3 1 Co...

Page 131: ...LW5 32 bits LW6 32 bits LW7 32 bits MMU RAM area determination ORA OIX 13 12 11 5 511 19 bits 1 bit 1 bit Tag U V Address array Data array Entry selection Longword LW selection Effective address 3 9 22 19 0 Write data Read data Hit signal Compare 13 1211 10 9 0 Figure 4 2 Configuration of Operand Cache SH7751 ...

Page 132: ...on Effective address 3 9 22 19 0 Write data Read data Hit signal Compare way 0 Compare way 1 13 12 10 0 Figure 4 3 Configuration of Operand Cache SH7751R Tag Stores the upper 19 bits of the 29 bit external address of the data line to be cached The tag is not initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cac...

Page 133: ...ays There is one LRU bit in each entry and it is controlled by hardware The LRU Last Recently Used algorithm that selects the most recently accessed way is used for way selection The LRU bit is initialized to 0 by a power on reset but is not initialized by a manual reset The LRU bit cannot be read from or written to by software 4 3 2 Read Operation When the OC is enabled CCR OCE 1 and data is read...

Page 134: ...ed to the CPU While the remaining one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the effective address is recorded in the cache 1 is written to the V bit and 0 to the U bit The data in the write back buffer is then written back to external memory 4 3 3 Write Operation When the OC is enabled CCR OCE...

Page 135: ...fective address is recorded in the cache and 1 is written to the V bit and U bit 3d Cache miss write through A write of the specified access size is performed to the external memory corresponding to the effective address In this case a write to cache is not performed 3e Cache miss copy back with write back The tag and data field of the cache line indexed by effective address bits 13 5 are first sa...

Page 136: ...uration of Write Through Buffer 4 3 6 RAM Mode Setting CCR ORA to 1 enables 8 kbytes of the operand cache to be used as RAM The operand cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511 In SH7751 compatible mode in the SH7751R the 8 kbytes of operand cache entries 256 to 511 are used as RAM In cache double mode in the SH7751R the total 16 kbytes of entries 256 to 511 ...

Page 137: ... FFFF 4 kB Corresponds to RAM area 2 As the distinction between RAM areas 1 and 2 is indicated by address bit 25 the area from H 7DFF F000 to H 7E00 0FFF should be used to secure a continuous 8 kbyte RAM area An example of RAM use in the SH7751R is shown below SH7751 compatible mode CCR EMODE 0 H 7C00 0000 to H 7C00 1FFF 8 kB Corresponds to RAM area entries 256 to 511 H 7C00 2000 to H 7C00 3FFF 8 ...

Page 138: ...ite back instruction OCBWB Rn Cache write back Allocate instruction MOVCA L R0 Rn Cache allocation 4 3 9 Prefetch Operation The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss If it is known that a cache miss will result from a read or write operation it is possible to fill the cache with data beforehand by means of the prefetch...

Page 139: ...che in the SH7751R LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 255 19 bits 1 bit Tag V Address array Longword LW selection Data array 0 Read data Hit signal Compare 31 26 25 5 4 3 2 1 MMU IIX 12 11 5 Entry selection Effective address 8 3 22 19 13 1211 10 9 0 Figure 4 6 Configuration of Instruction Cache SH7751 ...

Page 140: ...12 11 10 0 Figure 4 7 Configuration of Instruction Cache SH7751R Tag Stores the upper 19 bits of the 29 bit external address of the data line to be cached The tag is not initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains its v...

Page 141: ...V bit is 1 3a If the tag matches and the V bit is 0 3b If the tag does not match and the V bit is 0 3b If the tag does not match and the V bit is 1 3b 3a Cache hit The data indexed by effective address bits 4 2 is read as an instruction from the data field of the cache line indexed by effective address bits 12 5 3b Cache miss Data is read into the cache line from the external memory space correspo...

Page 142: ...the write tag and V bit are specified in the data field In the address field bits 31 24 have the value H F0 indicating the IC address array and the entry is specified by bits 12 5 CCR IIX has no effect on this entry specification The address array bit 3 association bit A bit specifies whether or not association is performed when writing to the IC address array As only longword access is used 0 sho...

Page 143: ... undefined read value Figure 4 8 Memory Mapped IC Address Array 4 5 2 IC Data Array The IC data array is allocated to addresses H F100 0000 to H F1FF FFFF in the P4 area A data array access requires a 32 bit address field specification when reading or writing and a 32 bit data field specification The entry to be accessed is specified in the address field and the longword data to be written is spec...

Page 144: ...y bits 13 5 CCR OIX and CCR ORA have no effect on this entry specification The address array bit 3 association bit A bit specifies whether or not association is performed when writing to the OC address array As only longword access is used 0 should be specified for address field bits 1 0 In the data field the tag is indicated by bits 31 10 the U bit by bit 1 and the V bit by bit 0 As the OC addres...

Page 145: ...r the comparison shows a mismatch an exception is not generated no operation is performed and the write is not executed If a data TLB multiple hit exception occurs during address translation processing switches to the data TLB multiple hit exception handling routine Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 13 14 2 U V U A Validity bit Dirty bit Associ...

Page 146: ...aged by software IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode Operation is not guaranteed if access is made from a program in another area In this case a branch to the P0 U0 P1 or P3 area should be made at least 8 instructions after this MOV instruction The OC contents can be read and written by a P1 or P2 area program with a MOV instruction in...

Page 147: ... The tag and V bit are read into the data field from the IC entry corresponding to the way and entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 IC address array write non associative The tag and V bit specified in the data field are written to the IC entry corresponding to the way an...

Page 148: ...ng the IC data array the way is specified by bit 13 and the entry is specified by bits 12 5 CCR IIX has no effect on this entry specification Address field bits 4 2 are used for the longword data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation ...

Page 149: ...or not association is performed when writing to the OC address array As only longword access is used 0 should be specified for address field bits 1 0 In the data field the tag is indicated by bits 31 10 the U bit by bit 1 and the V bit by bit 0 As the OC address array tag is 19 bits in length data field bits 31 29 are not used in the case of a write in which association is not performed Data field...

Page 150: ...a TLB multiple hit exception handling routine Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 13 14 15 2 U V U A Validity bit Dirty bit Association bit Reserved bits 0 write value undefined read value Way Figure 4 14 Memory Mapped OC Address Array 4 6 4 OC Data Array The OC data array is allocated to addresses H F500 0000 to H F5FF FFFF in the P4 area A data...

Page 151: ...dress array side Address field 31 23 5 4 2 1 0 1 1 1 1 0 1 0 1 Entry L Data field 31 0 Longword data 24 13 14 L Longword specification bits Reserved bits 0 write value undefined read value 15 Way Figure 4 15 Memory Mapped OC Data Array 4 6 5 Summary of Memory Mapped OC Addresses The memory mapped OC addresses in cache double mode in the SH7751R are summarized below using data area access as an exa...

Page 152: ...e performed using a store instruction on P4 area H E000 0000 to H E3FF FFFC A longword or quadword access size can be used The meaning of the address bits is as follows 31 26 111000 Store queue specification 25 6 Don t care Used for external memory transfer access right 5 0 1 0 SQ0 specification 1 SQ1 specification 4 2 LW specification Specifies longword position in SQ0 SQ1 1 0 00 Fixed at 0 4 7 3...

Page 153: ...erated in the same way as when the MMU is off External address bits 4 0 are fixed at 0 Transfer from the SQs to external is performed to this address When MMU is off The SQ area H E000 0000 to H E3FF FFFF is specified as the address at which a PREF instruction is issued The meaning of address bits 31 0 is as follows 31 26 111000 Store queue specification 25 6 Address External address bits 25 6 5 0...

Page 154: ...er from the SQs to external memory PREF instruction and a TLB miss exception protection violation exception or initial page write exception is generated However if SQ access is enabled in privileged mode only by MMUCR SQMD an address error will be flagged in user mode even if address translation is successful When MMU is off Operation is in accordance with MMUCR SQMD 0 Privileged user access possi...

Page 155: ...ed to external memory within an exception handling routine erroneous data may be transferred to external memory Example 1 When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction PREF instruction for transfer from SQ to external memory Address of this instruction is saved to SPC when exception occurs Instruction 1 instruct...

Page 156: ...en the two instructions 2 Do not place a PREF instruction for transfer from a store queue to external memory in the delay slot of a branch instruction B Do not execute a PREF instruction for transfer from a store queue to external memory within an exception handling routine If the above is executed and there is a store queue store instruction among the four instructions 2 including the instruction...

Page 157: ...Rev 3 0 04 02 page 118 of 1064 ...

Page 158: ...dling SH7751 Series exception handling is of three kinds for resets general exceptions and interrupts 5 1 2 Register Configuration The registers used in exception handling are shown in table 5 1 Table 5 1 Exception Related Registers Name Abbrevia tion R W Initial Value P4 Address 2 Area 7 Address 2 Access Size TRAPA exception register TRA R W Undefined H FF00 0020 H 1F00 0020 32 Exception event re...

Page 159: ...ains a 14 bit exception code The exception code set in INTEVT is that for an interrupt request The exception code is set automatically by hardware when an exception is accepted INTEVT can also be modified by software 3 The TRAPA exception register TRA resides at P4 address H FF00 0020 and contains 8 bit immediate data imm for the TRAPA instruction TRA is set automatically by hardware when a TRAPA ...

Page 160: ...ual SR bits 1 The PC SR and R15 contents are saved in SPC SSR and SGR 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 0 of the exception event register EXPEVT or to bits 13 0 of the interrupt event register INTEVT 7 The CPU branc...

Page 161: ...TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable exception 2 4 VBR H 100 H 820 Data address error read 2 5 VBR H 100 H 0E0 Data address error write 2 5 VBR H 100 H...

Page 162: ...H 260 4 H 280 5 H 2A0 6 H 2C0 7 H 2E0 8 H 300 9 H 320 A H 340 B H 360 C H 380 D H 3A0 External interrupts IRL3 IRL0 E 4 2 VBR H 600 H 3C0 TMU0 TUNI0 H 400 TMU1 TUNI1 H 420 TUNI2 H 440 TMU2 TICPI2 H 460 TMU3 TUNI3 H B00 TMU4 TUNI4 H B80 ATI H 480 PRI H 4A0 RTC CUI H 4C0 SCI ERI H 4E0 RXI H 500 TXI H 520 TEI H 540 WDT ITI H 560 RCMI H 580 Interrupt Completion type Peripheral module interrupt module ...

Page 163: ...pheral module interrupt module source PCIC 1 PCIDMA3 4 2 VBR H 600 H A20 Priority Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority Exception transition destination Control passes to H A000 0000 in a reset and to VBR offset in other cases Exception code Stored in EXPEVT for a reset or general exception and in INT...

Page 164: ...y hardware depending on the exception For details see section 5 6 Description of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions for exception handling during execution of a delayed branch instruction and a delay slot instruction and in the case of instructions in which two data accesses are performed Execute next instruction Is highest priority exception re exception typ...

Page 165: ...t FPU disable exception and unconditional trap exception are detected in the process of instruction decoding and do not occur simultaneously in the instruction pipeline These exceptions therefore all have the same priority General exceptions are detected in the order of instruction execution However exception handling is performed in the order of instruction flow program order Thus an exception fo...

Page 166: ...er 1 Instruction n 2 General illegal instruction exception IF ID EX MA WB IF ID EX MA WB TLB miss instruction access 2 3 4 IF Instruction fetch ID Instruction decode EX Instruction execution MA Memory access WB Write back Instruction n 3 TLB miss instruction n Re execution of instruction n General illegal instruction exception instruction n 1 Re execution of instruction n 1 TLB miss instruction n ...

Page 167: ...NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction is used to return from exception handling When the RTE instruction is executed the SPC contents are restored to PC and the SSR cont...

Page 168: ... are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections For some CPU functions the pin and pin must be driven low It is therefore essential to execute a power on reset and drive the pin low when powering on If the pin is driven high b...

Page 169: ... initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections Manual_reset EXPEVT H 00000020 VBR H 00000000 SR MD 1 SR RB 1 SR BL 1 SR I0 I3 B ...

Page 170: ... In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed For details see the register descriptions in the relevant sections H UDI_reset EXPEVT H 00000000 VBR H 00000000 SR MD 1 SR RB 1 SR BL 1 SR I0...

Page 171: ...n of VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset For details see the register descript...

Page 172: ...f VBR and SR is performed and a branch is made to PC H A000 0000 In the initialization processing the VBR register is set to H 0000 0000 and in SR the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask bits I3 I0 are set to B 1111 CPU and on chip peripheral module initialization is performed in the same way as in a manual reset For details see the register description...

Page 173: ...eption occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other...

Page 174: ...ates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other exceptions ITLB_mi...

Page 175: ...s is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TEA EXCEPTION_ADDRESS PTEH ...

Page 176: ...2 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 for a read access or H 0C0 for a write access...

Page 177: ... occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is m...

Page 178: ...t in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 for a read access or H 100 for a write access is set in EXPEVT The BL MD and RB bits are s...

Page 179: ...22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 For details see section 3 Memory Manageme...

Page 180: ...APA instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SGR R15 TRA imm 2 EXPEVT H ...

Page 181: ...luding LDC STC instructions that access GBR Transition address VBR H 0000 0100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation is not guaranteed if an ...

Page 182: ...ions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 0000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 1A0 is set i...

Page 183: ...R The R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and FPSCR General_fpu_disable...

Page 184: ...s The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 00000820 SR MD 1 SR RB 1 SR BL 1 PC VBR H 00000100 ...

Page 185: ...e execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data break is set see section 20 User Bre...

Page 186: ...ions The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 00000120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 00000100 ...

Page 187: ...eption code H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is to be masked or accepted For details see section 19 Interrupt Contr...

Page 188: ...e set in SPC The SR and R15 contents at the time of acceptance are set in SSR and SGR The code corresponding to the IRL 3 0 level is set in INTEVT See table 19 4 for the corresponding codes The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The acceptance level is not set in the interrupt mask bits in SR When the BL bit in SR is 1 the interrupt is masked For details see se...

Page 189: ... which the interrupt is accepted are set in SPC The SR and R15 contents at the time of acceptance are set in SSR and SGR The code corresponding to the interrupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 The module interrupt levels should be set as values between B 0000 and B 1111 in the interrupt priority registers IPRA IPRC in the interrup...

Page 190: ...elay slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible they are treated as a single instruction Consequently the priority order for exceptions that occur in these instructions differs from the usual priority order The priority order shown below is for the case where the delay slot instruction has only one data transfer a A check is performed...

Page 191: ...rrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software In the sleep or standby state however an interrupt is accepted even if the BL bit in SR is set to 1 3 SPC when an exception occurs a Re execution type exception The PC value for the ...

Page 192: ...F BT S BF S BRA or BSR instruction at address VBR H 100 VBR H 400 or VBR H 600 When the UBDE bit in the BRCR register is set to 1 and the user break debug support function is used do not locate a BT BF BT S BF S BRA or BSR instruction at the address indicated by the DBR register Note See section 20 4 User Break Debug Support Function ...

Page 193: ...Rev 3 0 04 02 page 154 of 1064 ...

Page 194: ...n Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support system control When the FD bit in SR is set to 1 the FPU cannot be used and an attempt to execute an FPU instruction will cause an FPU disable exception 6 2 Data Formats 6 2 1 Floating Point Format A floating point number consists of the following three fields Sign s Expone...

Page 195: ...1 Floating Point Number Formats and Parameters Parameter Single Precision Double Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias 127 1023 Emax 127 1023 Emin 126 1022 Floating point number value v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Em...

Page 196: ...egative zero H 80000000 H 80000000 00000000 Negative denormalized number H 80000001 to H 807FFFFF H 80000000 00000001 to H 800FFFFF FFFFFFFF Negative normalized number H 80800000 to H FF7FFFFF H 80100000 00000000 to H FFEFFFFF FFFFFFFF Negative infinity H FF800000 H FFF00000 00000000 Quiet non number H FF800001 to H FFBFFFFF H FFF00000 00000001 to H FFF7FFFF FFFFFFFF Signaling non number H FFC0000...

Page 197: ...on will not be generated in this case The qNAN values generated by the SH7751 Series as operation results are as follows Single precision qNaN H 7FBFFFFF Double precision qNaN H 7FF7FFFF FFFFFFFF See the individual instruction descriptions for details of floating point operations when a non number NaN is input 6 2 3 Denormalized Numbers For a denormalized number floating point value the exponent f...

Page 198: ...R0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 registers An FV register comprises four FR registers FV0 FR0 FR1 FR2 FR3 FV4 FR4 FR5 FR6 FR7 FV8 FR8 FR9 FR10 FR11 FV12 FR12 FR13 FR14 FR15 5 Single precision floating point extended registers XFi 16 registers When FPSCR FR 0 XF0 XF15 indicate...

Page 199: ...R2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 ...

Page 200: ...2 bit register pair 64 bits PR Precision mode PR 0 Floating point instructions are executed as single precision operations PR 1 Floating point instructions are executed as double precision operations graphics support instructions are undefined Do not set SZ and PR to 1 simultaneously this setting is reserved SZ PR 11 Reserved FPU operation instruction is undefined DN Denormalization mode DN 0 A de...

Page 201: ...register R1 to a single precision floating point number the processing flow is as follows R1 LDS instruction FPUL single precision FLOAT instruction FR1 6 4 Rounding In a floating point instruction rounding is performed when generating the final operation result from the intermediate result Therefore the result of combination instructions such as FMAC FTRV and FIPR will differ from the result when...

Page 202: ...and I and the FPSCR flag and enable fields contain bits corresponding to V Z O U and I but not E Thus FPU errors cannot be disabled When an FPU exception occurs the corresponding bit in the FPU exception cause field is set to 1 and 1 is added to the corresponding bit in the FPU exception flag field When an FPU exception does not occur the corresponding bit in the FPU exception cause field is clear...

Page 203: ...lue is generated Underflow U When FPSCR DN 0 a denormalized number with the same sign as the unrounded value or zero with the same sign as the unrounded value is generated When FPSCR DN 1 zero with the same sign as the unrounded value is generated Inexact exception I An inexact result is generated 6 6 Graphics Support Functions The SH7751 Series supports two kinds of graphics functions new instruc...

Page 204: ...trix the SH7751 Series supports 4 dimensional operations Matrix 4 4 matrix 4 4 This operation requires the execution of four FTRV instructions Since approximate value computations are performed to enable high speed computation the inexact exception I bit in the FPU exception cause field and FPU exception flag field is always set to 1 when an FTRV instruction is executed Therefore if the correspond...

Page 205: ... 4 6 8 10 12 14 n 0 to 15 These instructions enable two single precision 2 32 bit data items to be transferred that is the transfer performance of these instructions is doubled FSCHG This instruction changes the value of the SZ bit in FPSCR enabling fast switching between use and non use of pair single precision data transfer Programming Note When FPSCR SZ 1 and big endian mode is used FMOV can be...

Page 206: ...ry operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT the SH7751 Series branch instructions and RTE are delayed branches In a delayed branch the instruction following the branch is executed before the branch destination instruction This execution slot fo...

Page 207: ...STC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit constant values can be defined as literal constant values in memory and can be referenced by a PC relative load instruction MOV W disp PC Rn MOV L disp PC Rn There are no PC relative load instructions for floating poin...

Page 208: ...Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand 8 for a quadword operand Rn Rn 1 2 4 8 Rn 1 2 4 8 Rn EA After instru...

Page 209: ...1 2 4 disp zero extended Byte Rn disp EA Word Rn disp 2 EA Longword Rn disp 4 EA Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 EA GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to t...

Page 210: ...p is zero extended it is multiplied by 2 word or 4 longword according to the operand size With a longword operand the lower 2 bits of PC are masked PC H FFFFFFFC PC 4 disp 2 or PC H FFFFFFFC 4 disp 4 4 2 4 disp zero extended With longword operand Word PC 4 disp 2 EA Longword PC H FFFFFFFC 4 disp 4 EA PC relative disp 8 Effective address is PC 4 with 8 bit displacement disp added after being sign e...

Page 211: ... TST AND OR or XOR instruction is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operan...

Page 212: ... individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm XDm Rm_BANK nnn Register number DRm XDm Rn_BANK 000 DR0 XD0 R0_BANK 001 DR2 XD2 R1_BANK 111 DR14 XD14 R7_BANK mm Register number FVm nn Register number FVn 00 FV0 01 FV4 10 FV8 11 FV12 iiii Imm...

Page 213: ... W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001nnnndddd MOV L Rm disp Rn Rm disp 4 Rn 0001nnnnmmmmdddd MOV B disp Rm R0 di...

Page 214: ...sp 4 GBR 11000010dddddddd MOV B disp GBR R0 disp GBR sign extension R0 11000100dddddddd MOV W disp GBR R0 disp 2 GBR sign extension R0 11000101dddddddd MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R0 disp 4 PC H FFFFFFFC 4 R0 11000111dddddddd MOVT Rn T Rn 0000nnnn00101001 SWAP B Rm Rn Rm swap lower 2 bytes Rn 0110nnnnmmmm1000 SWAP W Rm Rn Rm swap upper lower words Rn 0110nnnnmmmm1...

Page 215: ...HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010101 Comparison result CMP STR Rm Rn When any bytes are equal 1 T Otherwise 0 T 0010nnnnmmmm1100 Comparison res...

Page 216: ...Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1110 NEG Rm Rn 0 Rm Rn 0110nnnnmmmm1011 NEGC Rm Rn 0 Rm T Rn borrow T 0110nnnnmmmm1010 Borro...

Page 217: ...mm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result 0 1 T Otherwise 0 T 11001100iiiiiiii T...

Page 218: ...hen Rn 0 Rn Rm Rn When Rn 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rn 0 Rn Rm Rn When Rn 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 SHLR8 Rn Rn 8 Rn 0100nnnn0...

Page 219: ...isp 2 PC 4 PC When T 0 nop 10001001dddddddd BT S label Delayed branch when T 1 disp 2 PC 4 PC When T 0 nop 10001101dddddddd BRA label Delayed branch disp 2 PC 4 PC 1010dddddddddddd BRAF Rn Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn PC 0100nnnn00101011 JSR Rn Delayed...

Page 220: ...L Rm SSR Rm SSR Rm 4 Rm 0100mmmm00110111 Privileged LDC L Rm SPC Rm SPC Rm 4 Rm 0100mmmm01000111 Privileged LDC L Rm DBR Rm DBR Rm 4 Rm 0100mmmm11110110 Privileged LDC L Rm Rn_BANK Rm Rn_BANK Rm 4 Rm 0100mmmm1nnn0111 Privileged LDS Rm MACH Rm MACH 0100mmmm00001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm00101010 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 LDS L Rm MACL Rm M...

Page 221: ...m0010 Privileged STC L SR Rn Rn 4 Rn SR Rn 0100nnnn00000011 Privileged STC L GBR Rn Rn 4 Rn GBR Rn 0100nnnn00010011 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 Privileged STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn Rn 4 Rn DBR Rn 0100nnnn11110010 Privileged STC ...

Page 222: ... Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 T Otherwise 0 T 1111nnnnmmmm0100 Compar...

Page 223: ... FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 7 11 Floating Point Control Instructions Instruction Operation Instruction Code Privileged T Bit LDS...

Page 224: ...mm11100 FMOV Rm XDn Rm XDn 1111nnn1mmmm1000 FMOV Rm XDn Rm XDn Rm 8 Rm 1111nnn1mmmm1001 FMOV R0 Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm10111 FIPR FVm FVn inner_product FVm FVn FR n 3 1111nnmm11101101 FTRV XMTRX FVn transform_vector XMTRX FVn FVn 1111nn0111111101 FRCHG FPSCR FR SPFCR FR 11...

Page 225: ...Rev 3 0 04 02 page 186 of 1064 ...

Page 226: ... the implementation of a processor Definitions in this section may not be applicable to SH 4 Series models other than the SH7751 Series 8 1 Pipelines Figure 8 1 shows the basic pipelines Normally a pipeline consists of five or six stages instruction fetch I decode and register read D execution EX SX F0 F1 F2 F3 data access NA MA and write back S FS An instruction is executed as a combination of ba...

Page 227: ...e Register read Non memory data access Write back I D SX Operation NA S 4 Special Load Store Pipeline Instruction fetch Instruction decode Issue Register read Memory data access Write back I D SX Address calculation MA S 5 Floating Point Pipeline Instruction fetch Instruction decode Issue Register read Computation 2 Computation 3 Write back I D F1 Computation 1 F2 FS 6 Floating Point Extended Pipe...

Page 228: ...S L to FPUL LDTLB PREF STS L from FPUL FPSCR I D EX MA S 3 GBR based load store 1 issue cycle MOV BWL d GBR I D SX MA S 4 JMP RTS BRAF 2 issue cycles I D EX NA S D EX NA S 5 TST B 3 issue cycles I D SX MA S D SX NA S D SX NA S 6 AND B OR B XOR B 4 issue cycles I D SX MA S D SX NA S D SX NA S D SX MA S 7 TAS B 5 issue cycles I D EX MA S D EX MA S D EX NA S D EX NA S D EX MA S 8 RTE 5 issue cycles I...

Page 229: ...NA S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S D EX NA S 14 LDC to DBR Rp_BANK SSR SPC VBR BSR 1 issue cycle I D EX NA S SX SX 15 LDC to GBR 3 issue cycles I D EX NA S D D SX SX 16 LDC to SR 4 issue cycles I D EX NA S D D D SX SX SX I D EX MA S 17 LDC L to DBR Rp_BANK SSR SPC VBR 1 issue cycle SX SX 18 LDC L to GBR 3 issue cycles I D EX MA S D D SX SX Figure 8 2 Instruction Execution Patte...

Page 230: ...A S D SX MA S 23 STC L from SGR 3 issue cycles I D SX NA S D SX NA S D SX MA S 24 LDS to PR JSR BSRF 2 issue cycles I D EX NA S D SX SX 25 LDS L to PR 2 issue cycles I D EX MA S D SX SX 26 STS from PR 2 issue cycles I D SX NA S D SX NA S 27 STS L from PR 2 issue cycles I D SX NA S D SX MA S 28 CLRMAC LDS to MACH L 1 issue cycle I D EX NA S F1 F1 F2 FS 29 LDS L to MACH L 1 issue cycle I D EX MA S F...

Page 231: ...X MA S CPU D EX MA S f1 FPU f1 f1 f1 F2 FS 36 Single precision floating point computation 1 issue cycle FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG I D F1 F2 FS 37 Single precision FDIV SQRT 1 issue cycle I D F1 F2 FS F3 F1 F2 FS 38 Double precision floating point computation 1 1 issue cycle FCNVDS FCNVSD FLOAT FTRC I D F1 F2 FS d F1 F2 FS 39 Double precision floating point computat...

Page 232: ... F1 F2 FS F1 F2 FS 42 FIPR 1 issue cycle I D F0 F1 F2 FS 43 FTRV 1 issue cycle F1 F2 FS D F0 I F1 F2 FS d F0 F1 F2 FS d F0 F1 F2 FS d F0 Notes Locks D stage Register read only Locks but no operation is executed Can overlap another f1 but not another F1 d D f1 Cannot overlap a stage of the same kind except when two instructions are executed in parallel Figure 8 2 Instruction Execution Patterns cont...

Page 233: ...MP EQ Rm Rn CMP PL Rn SETT CMP GE Rm Rn CMP PZ Rn TST imm R0 CMP GT Rm Rn CMP STR Rm Rn TST Rm Rn 2 EX Group ADD imm Rn MOVT Rn SHLL2 Rn ADD Rm Rn NEG Rm Rn SHLL8 Rn ADDC Rm Rn NEGC Rm Rn SHLR Rn ADDV Rm Rn NOT Rm Rn SHLR16 Rn AND imm R0 OR imm R0 SHLR2 Rn AND Rm Rn OR Rm Rn SHLR8 Rn DIV0S Rm Rn ROTCL Rn SUB Rm Rn DIV0U ROTCR Rn SUBC Rm Rn DIV1 Rm Rn ROTL Rn SUBV Rm Rn DT Rn ROTR Rn SWAP B Rm Rn E...

Page 234: ...n MOV B disp GBR R0 MOV W R0 Rm Rn FMOV Rm DRn MOV B disp Rm R0 MOV W Rm Rn FMOV Rm XDn MOV B R0 Rm Rn MOV W Rm Rn FMOV DRm R0 Rn MOV B Rm Rn MOV W R0 disp GBR FMOV DRm Rn MOV B Rm Rn MOV W R0 disp Rn FMOV DRm Rn MOV B R0 disp GBR MOV W Rm R0 Rn FMOV DRm DRn MOV B R0 disp Rn MOV W Rm Rn FMOV DRm XDn MOV B Rm R0 Rn MOV W Rm Rn FMOV FRm FRn MOV B Rm Rn MOVCA L R0 Rn FMOV XDm R0 Rn MOV B Rm Rn OCBI R...

Page 235: ... FIPR FVm FVn FSQRT DRn FADD FRm FRn FLOAT FPUL DRn FSQRT FRn FCMP EQ FRm FRn FLOAT FPUL FRn FSUB DRm DRn FCMP GT FRm FRn FMAC FR0 FRm FRn FSUB FRm FRn FCNVDS DRm FPUL FMUL DRm DRn FTRC DRm FPUL FCNVSD FPUL DRn FMUL FRm FRn FTRC FRm FPUL FDIV DRm DRn FRCHG FTRV XMTRX FVn FDIV FRm FRn FSCHG ...

Page 236: ...T DRm DRn LDS L Rm PR STC L SR Rn JMP Rn LDTLB STC L SSR Rn JSR Rn MAC L Rm Rn STC L VBR Rn LDC Rm DBR MAC W Rm Rn STS FPSCR Rn LDC Rm GBR MUL L Rm Rn STS MACH Rn LDC Rm Rp_BANK MULS W Rm Rn STS MACL Rn LDC Rm SPC MULU W Rm Rn STS PR Rn LDC Rm SR OR B imm R0 GBR STS L FPSCR Rn LDC Rm SSR RTE STS L FPUL Rn LDC Rm VBR RTS STS L MACH Rn LDC L Rm DBR SETS STS L MACL Rn LDC L Rm GBR SLEEP STS L PR Rn L...

Page 237: ... three clocks are determined with the frequency control register FRQCR In this section machine cycles are based on the I clock unless otherwise specified For details of FRQCR see section 10 Clock Oscillation Circuits Instruction execution cycles are summarized in table 8 3 Penalty cycles due to a pipeline stall or freeze are not considered in this table Issue rate Interval between the issue of an ...

Page 238: ...MUL is the preceding instruction 2 cycles In the case of flow dependency latency may be exceptionally increased or decreased depending on the combination of sequential instructions figure 8 3 e When a floating point computation is followed by a floating point register store the latency of the floating point computation may be decreased by 1 cycle If there is a load of the shift amount immediately ...

Page 239: ...ve the 2 cycle stall of the ADD is eliminated by inserting three instructions without dependency Software performance can be improved by such instruction scheduling Other causes of a stall are as follows Instruction TLB miss Instruction access to external memory instruction cache miss etc Data access to external memory operand cache miss etc Data access to a memory mapped control register During t...

Page 240: ...E A S 4 stall cycles EX group SHAD and EX group ADD cannot be executed in parallel Therefore SHAD is issued first and the following ADD is recombined with the next instruction EX group ADD and LS group MOV L can be executed in parallel Overlapping of stages in the 2nd instruction is possible AND B and MOV are fetched simultaneously but MOV is stalled due to resource locking After the lock is relea...

Page 241: ...3 write FR2 write I D F1 F2 FS d F1 F2 FS I D EX MA S 3 cycle latency for upper lower FR FR1 write FR0 write FLDI1 FR3 FIPR FV0 FV4 FMOV R1 XD14 FTRV XMTRX FV0 I D EX NA S I D d F0 F1 F2 FS Zero cycle latency 3 cycle increase 3 stall cycles I D EX MA S I D d F0 F1 F2 FS d F0 F1 FS F2 d F0 F2 F1 FS d F1 F0 F2 FS 2 cycle latency 1 cycle increase 3 stall cycles The following instruction ADD is not st...

Page 242: ...F2 FS 11 cycle latency 10 stall cycles latency 11 1 The registers are written back in program order D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX NA S I D 7 cycle latency for lower FR 8 cycle latency for upper FR 6 stall cycles longest latency 8 2 FR2 write FR3 write D F1 F2 FS I d F1 F2 FS d F1 F2 FS d F1 F0 F0 F0 F0 F2 FS g Anti flow dependency EX MA S I D 5 stall cycles D...

Page 243: ...0 DR2 I D F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 F2 FS EX MA S f1 EX MA S D f1 f1 F2 FS f1 F2 FS I D 5 stall cycles MAC W R1 R2 I D EX MA S f1 f1 f1 F2 FS f1 F2 FS I f1 D EX MA S f1 D EX MA S f1 F2 FS f1 F2 FS F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS d F1 F2 FS F1 I D 3 stall cycles 1 stall cycle 2 stall cycles MAC W R1 R2 MAC W R1 R2 FADD DR4 DR6 f1 stage can overlap preceding f...

Page 244: ... Rm Rn LS 1 2 2 11 MOV W Rm Rn LS 1 2 2 12 MOV L Rm Rn LS 1 2 2 13 MOV B Rm Rn LS 1 1 2 2 14 MOV W Rm Rn LS 1 1 2 2 15 MOV L Rm Rn LS 1 1 2 2 16 MOV B disp Rm R0 LS 1 2 2 17 MOV W disp Rm R0 LS 1 2 2 18 MOV L disp Rm Rn LS 1 2 2 19 MOV B R0 Rm Rn LS 1 2 2 20 MOV W R0 Rm Rn LS 1 2 2 21 MOV L R0 Rm Rn LS 1 2 2 22 MOV B disp GBR R0 LS 1 2 3 23 MOV W disp GBR R0 LS 1 2 3 24 MOV L disp GBR R0 LS 1 2 3 ...

Page 245: ... 1 3 7 12 MA 4 3 7 41 MOVT Rn EX 1 1 1 42 OCBI Rn LS 1 1 2 10 MA 4 1 2 43 OCBP Rn LS 1 1 5 11 MA 4 1 5 44 OCBWB Rn LS 1 1 5 11 MA 4 1 5 45 PREF Rn LS 1 1 2 46 SWAP B Rm Rn EX 1 1 1 47 SWAP W Rm Rn EX 1 1 1 Data transfer instructions 48 XTRCT Rm Rn EX 1 1 1 49 ADD Rm Rn EX 1 1 1 50 ADD imm Rn EX 1 1 1 51 ADDC Rm Rn EX 1 1 1 52 ADDV Rm Rn EX 1 1 1 53 CMP EQ imm R0 MT 1 1 1 54 CMP EQ Rm Rn MT 1 1 1 5...

Page 246: ... Rn CO 2 4 4 34 F1 4 2 71 MULS W Rm Rn CO 2 4 4 34 F1 4 2 72 MULU W Rm Rn CO 2 4 4 34 F1 4 2 73 NEG Rm Rn EX 1 1 1 74 NEGC Rm Rn EX 1 1 1 75 SUB Rm Rn EX 1 1 1 76 SUBC Rm Rn EX 1 1 1 Fixed point arithmetic instructions 77 SUBV Rm Rn EX 1 1 1 78 AND Rm Rn EX 1 1 1 79 AND imm R0 EX 1 1 1 80 AND B imm R0 GBR CO 4 4 6 81 NOT Rm Rn EX 1 1 1 82 OR Rm Rn EX 1 1 1 83 OR imm R0 EX 1 1 1 84 OR B imm R0 GBR ...

Page 247: ... 1 1 1 99 SHLD Rm Rn EX 1 1 1 100 SHLL Rn EX 1 1 1 101 SHLL2 Rn EX 1 1 1 102 SHLL8 Rn EX 1 1 1 103 SHLL16 Rn EX 1 1 1 104 SHLR Rn EX 1 1 1 105 SHLR2 Rn EX 1 1 1 106 SHLR8 Rn EX 1 1 1 Shift instructions 107 SHLR16 Rn EX 1 1 1 108 BF disp BR 1 2 or 1 1 109 BF S disp BR 1 2 or 1 1 110 BT disp BR 1 2 or 1 1 111 BT S disp BR 1 2 or 1 1 112 BRA disp BR 1 2 1 113 BRAF Rn CO 2 3 4 114 BSR disp BR 1 2 14 S...

Page 248: ...X 3 2 132 LDC Rm SR CO 4 4 16 SX 3 2 133 LDC Rm SSR CO 1 3 14 SX 3 2 134 LDC Rm SPC CO 1 3 14 SX 3 2 135 LDC Rm VBR CO 1 3 14 SX 3 2 136 LDC L Rm DBR CO 1 1 3 17 SX 3 2 137 LDC L Rm GBR CO 3 3 3 18 SX 3 2 138 LDC L Rm Rp_BANK CO 1 1 3 17 SX 3 2 139 LDC L Rm SR CO 4 4 4 19 SX 3 2 140 LDC L Rm SSR CO 1 1 3 17 SX 3 2 141 LDC L Rm SPC CO 1 1 3 17 SX 3 2 142 LDC L Rm VBR CO 1 1 3 17 SX 3 2 143 LDS Rm M...

Page 249: ...2 161 STC L SR Rn CO 2 2 2 22 162 STC L SSR Rn CO 2 2 2 22 163 STC L SPC Rn CO 2 2 2 22 164 STC L VBR Rn CO 2 2 2 22 165 STS MACH Rn CO 1 3 30 166 STS MACL Rn CO 1 3 30 167 STS PR Rn CO 2 2 26 168 STS L MACH Rn CO 1 1 1 31 169 STS L MACL Rn CO 1 1 1 31 System control instructions 170 STS L PR Rn CO 2 2 2 27 171 FLDI0 FRn LS 1 0 1 172 FLDI1 FRn LS 1 0 1 173 FMOV FRm FRn LS 1 0 1 174 FMOV S Rm FRn L...

Page 250: ...1 10 1 192 FSUB FRm FRn FE 1 3 4 36 193 FTRC FRm FPUL FE 1 3 4 36 194 FMOV DRm DRn LS 1 0 1 195 FMOV Rm DRn LS 1 2 2 196 FMOV Rm DRn LS 1 1 2 2 197 FMOV R0 Rm DRn LS 1 2 2 198 FMOV DRm Rn LS 1 1 2 199 FMOV DRm Rn LS 1 1 1 2 Single precision floating point instructions 200 FMOV DRm R0 Rn LS 1 1 2 201 FABS DRn LS 1 0 1 202 FADD DRm DRn FE 1 7 8 9 39 F1 2 6 203 FCMP EQ DRm DRn CO 2 3 5 40 F1 2 2 204 ...

Page 251: ... CO 1 1 1 2 222 FMOV DRm XDn LS 1 0 1 223 FMOV XDm DRn LS 1 0 1 224 FMOV XDm XDn LS 1 0 1 225 FMOV Rm XDn LS 1 2 2 226 FMOV Rm XDn LS 1 1 2 2 227 FMOV R0 Rm XDn LS 1 2 2 228 FMOV XDm Rn LS 1 1 2 229 FMOV XDm Rm LS 1 1 1 2 230 FMOV XDm R0 Rn LS 1 1 2 231 FIPR FVm FVn FE 1 4 5 42 F1 3 1 232 FRCHG FE 1 1 4 36 233 FSCHG FE 1 1 4 36 F0 2 4 Graphics acceleration instructions 234 FTRV XMTRX FVn FE 1 5 5 ...

Page 252: ...e following SHAD SHLD the latency of the load is increased by 1 cycle 3 When an LS group instruction with a latency of less than 3 cycles is followed by a double precision floating point instruction FIPR or FTRV the latency of the first instruction is increased to 3 cycles Example In the case of FMOV FR4 FR0 and FIPR FV0 FV4 FIPR is stalled for 2 cycles 4 When MAC W MAC L MUL L MULS W MULU W DMULS...

Page 253: ...Rev 3 0 04 02 page 214 of 1064 ...

Page 254: ... 1 1 Types of Power Down Modes The following power down modes and functions are provided Sleep mode Deep sleep mode Standby mode Hardware standby mode Module standby function TMU RTC SCI SCIF and DMAC on chip peripheral modules Table 9 1 shows the conditions for entering these modes from the program execution state the status of the CPU and peripheral modules in each mode and the method of exiting...

Page 255: ...n STBCR and DSLP bit is 1 in STBCR2 Operating Halted registers held Held Operating DMA halted Held Self refresh ing Interrupt Reset Standby SLEEP instruction executed while STBY bit is 1 in STBCR Halted Halted registers held Held Halted Held Self refresh ing Interrupt Reset Hard ware standby Setting CA pin to low level Halted Halted Unde fined Halted High imped ance state Unde fined Power on reset...

Page 256: ...stop clear register CLKSTPCLR00 W H 00000000 H FE0A0008 H 1E0A0008 32 9 1 3 Pin Configuration Table 9 3 shows the pins used for power down mode control Table 9 3 Power Down Mode Pins Pin Name Abbreviation I O Function Processor status 1 Processor status 0 STATUS1 STATUS0 Output Indicate the processor s operating status STATUS1 STATUS0 HH Reset HL Sleep mode LH Standby mode LL Normal operation Slee...

Page 257: ...e Control PHZ Controls the state of peripheral module related pins in standby mode When the PHZ bit is set to 1 peripheral module related pins go to the high impedance state in standby mode For the relevant pins see section 9 2 2 Peripheral Module Pin High Impedance Control Bit 6 PHZ Description 0 Peripheral module related pins are in normal state Initial value 1 Peripheral module related pins go ...

Page 258: ... SCIF clock supply is stopped Bit 2 Module Stop 2 MSTP2 Specifies stopping of the clock supply to the timer unit channel 0 to 2 TMU among the on chip peripheral modules The clock supply to the TMU is stopped when the MSTP2 bit is set to 1 Bit 2 MSTP2 Description 0 TMU channel 0 to 2 operates Initial value 1 TMU channel 0 to 2 clock supply is stopped Bit 1 Module Stop 1 MSTP1 Specifies stopping of ...

Page 259: ...D1 TXD2 MD7 MD8 DMA related pins DACK0 DRAK0 DACK1 DRAK1 Other Information The setting in this register is invalid when the above pins are used as port output pins For details of pin states see Appendix D Pin Functions 9 2 3 Peripheral Module Pin Pull Up Control When bit 5 in the standby control register STBCR is cleared to 0 peripheral module related pins are pulled up when in the input or high i...

Page 260: ...leep mode on execution of SLEEP instruction Note When the STBY bit in the STBCR register is 0 Bit 6 STATUS Pin High Impedance Control STHZ This bit selects whether the STATUS0 and 1 pins are set to high impedance when in hardware standby mode Bit 6 STHZ Description 0 Sets STATUS0 1 pins to high impedance when in hardware standby mode Initial value 1 Drives STATUS0 1 pins to LH when in hardware sta...

Page 261: ... by writing 1 to the corresponding bit in the CLKSTPCLR00 register Writing 0 to CLKSTP00 will not change the bit value CLKSTP00 is initialized to H 00000000 by a reset It is not initialized in standby mode Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 CSTP2 CSTP1 CSTP0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bits 31 to 3 Reserved These bit...

Page 262: ...al value 1 INTC does not detect PCIC and TMU channel 3 and 4 interrupts 9 2 6 Clock Stop Clear Register 00 CLKSTPCLR00 Clock stop clear register 00 CLKSTPCLR00 is a 32 bit write only register that is used to clear corresponding bits in the CLKSTP00 register Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W W W W W W W W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W W W W W W W W W Bit...

Page 263: ... code corresponding to the interrupt source is set in the INTEVT register Exit by Reset Sleep mode is exited by means of a power on or manual reset via the pin or a power on or manual reset executed when the watchdog timer overflows 9 4 Deep Sleep Mode 9 4 1 Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is set...

Page 264: ...751 Series to return to the normal state The pin sleep mode is also canceled when the conditions specified in section 9 3 2 Exit From Sleep Mode are satisfied In a power on reset the pin should be fixed high 9 6 Standby Mode 9 6 1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1 the chip switches from the program execution state to standby mode I...

Page 265: ... clock to be used for the up count in bits CKS2 CKS0 in the WTCSR register 2 Set the STBY bit in the STBCR register to 1 then execute a SLEEP instruction 3 When standby mode is entered and the chip s internal clock stops a low level signal is output at the STATUS1 pin and a high level signal at the STATUS0 pin 9 6 2 Exit from Standby Mode Standby mode is exited by means of an interrupt NMI IRL or ...

Page 266: ...a low level signal is output at the STATUS1 pin and a high level signal at the STATUS0 pin 3 The input clock is stopped or its frequency changed after the STATUS1 pin goes low and the STATUS0 pin high 4 When the frequency is changed input an NMI or IRL interrupt after the change When the clock is stopped input an NMI or IRL interrupt after applying the clock 5 After the time set in the WDT clock s...

Page 267: ...pped Notes 1 The register initialized is the same as in standby mode but initialization is not performed if the RTC clock is not in use see section 12 Timer Unit TMU 2 The counter operates when the START bit in RCR2 is 1 see section 11 Realtime Clock RTC 3 For details see section 20 6 User Break Controller Stop Function 4 Terminate DMA transfers prior to making the transition to module standby mod...

Page 268: ...when in the standby mode depends on the CPG status as follows 1 In standby mode The clock remains stopped and a transition is made to the hardware standby state Interrupts and manual resets are disabled but the output pins remain in the same state as in standby mode 2 When WDT is operating when standby mode is exited by interrupt Standby mode is momentarily exited the CPU restarts and then a trans...

Page 269: ...ng is shown below The meaning of the STATUS pin settings is as follows Reset HH STATUS1 high STATUS0 high Sleep HL STATUS1 high STATUS0 low Standby LH STATUS1 low STATUS0 high Normal LL STATUS1 low STATUS0 low The meaning of the clock units is as follows Bcyc Bus clock cycle Pcyc Peripheral clock cycle 9 9 1 In Reset Power On Reset CKIO STATUS Normal Reset Normal 0 5 Bcyc 0 30 Bcyc PLL stabilizati...

Page 270: ...s set and an internal reset started after waiting until the end of the currently executing bus cycle Figure 9 2 STATUS Output in Manual Reset 9 9 2 In Exit from Standby Mode Standby Interrupt CKIO STATUS Normal Standby Normal WDT count Oscillation stops Interrupt request WDT overflow Figure 9 3 STATUS Output in Standby Interrupt Sequence ...

Page 271: ...l Reset Normal 0 10 Bcyc Standby Oscillation stops 2 0 30 Bcyc Notes 1 When standby mode is exited by means of a power on reset a WDT count is not performed Hold low for the PLL oscillation stabilization time 2 Undefined Figure 9 4 STATUS Output in Standby Power On Reset Sequence ...

Page 272: ...e is exited by means of a manual reset a WDT count is not performed Hold low for the PLL oscillation stabilization time Reset Oscillation stops Figure 9 5 STATUS Output in Standby Manual Reset Sequence 9 9 3 In Exit from Sleep Mode Sleep Interrupt CKIO STATUS Normal Sleep Normal Interrupt request Figure 9 6 STATUS Output in Sleep Interrupt Sequence ...

Page 273: ...et Reset CKIO STATUS Normal Reset Sleep Normal 0 10 Bcyc 0 30 Bcyc 1 2 Notes 1 When sleep mode is exited by means of a power on reset hold low for the oscillation stabilization time 2 Undefined Figure 9 7 STATUS Output in Sleep Power On Reset Sequence ...

Page 274: ... 3 0 04 02 page 235 of 1064 Sleep Manual Reset Reset STATUS Normal Reset Sleep Normal CKIO High 0 30 Bcyc 0 30 Bcyc Note Hold low until STATUS reset Figure 9 8 STATUS Output in Sleep Manual Reset Sequence ...

Page 275: ... 9 STATUS Output in Deep Sleep Interrupt Sequence Deep Sleep Power On Reset Reset CKIO STATUS Normal Sleep Reset Normal 0 10 Bcyc 0 30 Bcyc RESET 1 2 Notes 1 When deep sleep mode is exited by means of a power on reset hold RESET low for the oscillation stabilization time 2 Undefined Figure 9 10 STATUS Output in Deep Sleep Power On Reset Sequence ...

Page 276: ...04 02 page 237 of 1064 Deep Sleep Manual Reset Reset STATUS Normal Sleep Reset Normal CKIO High 0 30 Bcyc 0 30 Bcyc Note Hold low until STATUS reset Figure 9 11 STATUS Output in Deep Sleep Manual Reset Sequence ...

Page 277: ...ust be kept low while in hardware standby mode After setting the pin level low the clock starts when the CA pin level is switched to high CKIO CA STATUS Reset 0 10 Bcyc 0 10 Bcyc Standby 2 Waiting for end of bus cycle Undefined Notes 1 Same at sleep and reset 2 High impedance when STBCR2 STHZ 0 Normal 1 Figure 9 12 Hardware Standby Mode Timing When CA Low in Normal Operation ...

Page 278: ... Standby WDT count WDT overflow Interrupt request Note High impedance when STBCR2 STHZ 0 Figure 9 13 Hardware Standby Mode Timing When CA Low in WDT Operation VDDQ VDD CA Min 0s Min 0s Max 50 µs Note VDDQ VDD CPG VDD min Figure 9 14 Timing When Power Other than VDD RTC is Off ...

Page 279: ...Rev 3 0 04 02 page 240 of 1064 CA VDD RTC VDD VDDQ Min 0s Note VDD VDD PLL1 2 VDDQ VDD CPG Power on oscillation settling time Figure 9 15 Timing When VDD RTC Power is Off On ...

Page 280: ...ck P used by the peripheral modules and the bus clock CKIO used by the external bus interface Six clock modes Any of six clock operating modes can be selected with different combinations of CPU clock bus clock and peripheral module clock division ratios after a power on reset Frequency change function PLL phase locked loop circuits and a frequency divider in the CPG enable the CPU clock bus clock ...

Page 281: ... Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow Power on reset or manual reset can be selected Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow Selection of eight counter input clocks Any of eight clocks can be selected scaled from the 1 clock of frequency divider 2 shown in figure 10 1 The ...

Page 282: ...andby control register 2 Oscillator circuit PLL circuit 1 Frequency divider 2 Crystal oscillator Frequency divider 1 PLL circuit 2 CPU clock Iø cycle Icyc Peripheral module clock Pø cycle Pcyc Bus clock Bø cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD0 FRQCR STBCR2 1 1 2 1 3 1 4 1 6 1 8 6 1 2 1 STBCR Fi...

Page 283: ... Frequency divider 2 Crystal oscillator CPU clock Iø cycle Icyc Peripheral module clock Pø cycle Pcyc Bus clock Bø cycle Bcyc CPG control unit Clock frequency control circuit Standby control circuit Bus interface Internal bus XTAL EXTAL MD8 CKIO MD2 MD1 MD0 FRQCR STBCR2 1 1 2 1 3 1 4 1 6 1 8 6 12 PLL circuit 2 1 STBCR Figure 10 1 2 Block Diagram of CPG SH7751R ...

Page 284: ...ut from the EXTAL pin is supplied internally without using PLL circuit 1 Frequency Divider 2 Frequency divider 2 generates the CPU clock I bus clock B and peripheral module clock P The division ratio is set in the frequency control register Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency by means of the MD pins and frequency control register Standby...

Page 285: ...t from EXTAL When MD8 1 crystal resonator is connected directly to EXTAL and XTAL Clock output pin CKIO Output Used as external clock output pin Level can also be fixed CKIO enable pin CKE Output 0 when CKIO output clock is unstable and in case of synchronous DRAM self refreshing Note Set to 1 in a power on reset For details of synchronous DRAM self refreshing see section 13 3 5 Synchronous DRAM I...

Page 286: ...rating mode is the only factor to determine whether to turn the 1 2 frequency divider on or off 2 For the frequency range of the input clock see the EXTAL clock input frequency fEX and CKIO clock output fOP in section 23 3 1 Clock and Control Signal Timing Table 10 3 2 Clock Operating Modes SH7751R External Pin Combination Frequency vs Input Clock Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Clo...

Page 287: ...2 9 h00a 1 4 9 h00c 1 2 1 8 9 h011 1 3 9 h013 1 3 1 6 9 h01a 1 4 9 h01c 1 4 1 8 9 h023 1 6 1 6 9 h02c 1 1 8 1 8 9 h048 1 2 9 h04a 1 4 9 h04c 1 2 1 8 9 h05a 1 4 9 h05c 1 4 1 8 9 h063 1 6 1 6 9 h06c 1 2 1 8 1 8 9 h091 1 3 9 h093 1 3 1 6 9 h0a3 1 3 1 6 1 6 9 h0da 1 4 9 h0dc 1 4 9 h0ec 1 4 1 8 1 8 9 h123 1 6 1 6 1 6 9 h16c 1 8 1 8 1 8 Note Do not set values other than those shown in the table for the ...

Page 288: ... 1 0 IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 Initial value R W R W R W R W R W R W R W R W R W Bits 15 to 12 Reserved These bits are always read as 0 and should only be written with 0 Bit 11 Clock Output Enable CKOEN Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high impedance state When the CKIO pin goes to the high impedance state operation continues at t...

Page 289: ...1 1 1 2 1 0 1 3 1 1 4 1 0 0 1 6 1 1 8 Other than the above Setting prohibited Do not set Bits 5 to 3 Bus Clock Frequency Division Ratio BFC These bits specify the bus clock frequency division ratio with respect to the input clock 1 2 frequency divider or PLL circuit 1 output frequency Bit 5 BFC2 Bit 4 BFC1 Bit 3 BFC0 Description 0 0 0 1 1 1 2 1 0 1 3 1 1 4 1 0 0 1 6 1 1 8 Other than the above Sett...

Page 290: ...d The oscillation stabilization time count is performed by the on chip WDT 1 Set a value in WDT to provide the specified oscillation stabilization time and stop the WDT The following settings are necessary WTCSR register TME bit 0 WDT stopped WTCSR register CKS2 CKS0 bits WDT count clock division ratio WTCNT counter Initial counter value 2 Set the PLL1EN bit to 1 3 Internal processor operation sto...

Page 291: ...llation stabilization time is required 1 Make WDT settings as in 10 5 1 2 Set the BFC2 BFC0 bits to the desired value 3 Internal processor operation stops temporarily and the WDT starts counting up The internal clock stops and an unstable clock is output to the CKIO pin 4 After the WDT count overflows clock supply begins within the chip and the processor resumes operation The WDT stops after overf...

Page 292: ...up 10 7 Overview of Watchdog Timer 10 7 1 Block Diagram Figure 10 2 shows a block diagram of the WDT Standby release Internal reset request Interrupt request Standby control Reset control Interrupt control WTCSR WTCNT Bus interface Clock selection Overflow Frequency divider Clock selector Clock WDT WTCSR Watchdog timer control status register WTCNT Watchdog timer counter Standby mode Frequency div...

Page 293: ... write with the upper byte set to H 5A or H A5 respectively Byte and longword size writes cannot be used Use byte access when reading 10 8 WDT Register Descriptions 10 8 1 Watchdog Timer Counter WTCNT The watchdog timer counter WTCNT is an 8 bit readable writable counter that counts up on the selected clock When WTCNT overflows a reset is generated in watchdog timer mode or an interrupt in interva...

Page 294: ... WT RSTS WOVF IOVF CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 Timer Enable TME Specifies starting and stopping of timer operation Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency Bit 7 TME Description 0 Up count stopped WTCNT value retained Initial value 1 Up count started Bit 6 Timer Mode Select WT Specifies whether ...

Page 295: ... 2 to 0 CKS2 CKS0 These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock The overflow periods shown in the following table are for use of a 33 MHz input clock with frequency divider 1 off and PLL circuit 1 on 6 Note When PLL1 is switched on or off the clock following the switch is used Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 ...

Page 296: ...written to with a byte or longword transfer instruction When writing to WTCNT perform the transfer with the upper byte set to H 5A and the lower byte containing the write data When writing to WTCSR perform the transfer with the upper byte set to H A5 and the lower byte containing the write data This transfer procedure writes the lower byte data to WTCNT or WTCSR The write formats are shown in figu...

Page 297: ...s not set at this time 6 The counter stops at a value of H 00 H 01 The value at which the counter stops depends on the clock ratio 10 9 2 Frequency Changing Procedure The WDT is used in a frequency change using the PLL It is not used when the frequency is changed simply by making a frequency divider switch 1 Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change I...

Page 298: ...ster to 1 and generates a reset of the type specified by the RSTS bit The counter then continues counting 10 9 4 Using Interval Timer Mode When the WDT is operating in interval timer mode an interval timer interrupt is generated each time the counter overflows This enables interrupts to be generated at fixed intervals 1 Clear the WT bit in the WTCSR register to 0 select the count clock with bits C...

Page 299: ...t no other signal lines cross the signal lines for these pins EXTAL XTAL SH7751 Series CL1 CL2 R Avoid crossing signal lines Recommended values CL1 CL2 0 33 pF R 0Ω Note The values for CL1 CL2 and the damping resistance should be determined after consultation with the crystal resonator manufacturer Figure 10 4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXT...

Page 300: ...power supply source and insert resistors RCB and RB and decoupling capacitors CPB and CB close to the pins VDD PLL1 CPB1 CPB2 CB RCB1 Recommended values RCB1 RCB2 10 Ω CPB1 CPB2 10 µF RB 10 Ω CB 10 µF RCB2 RB 1 8 V 3 3 V VSS PLL1 VDD PLL2 SH7751 Series VSS PLL2 VDD CPG VSS CPG Figure 10 5 Points for Attention when Using PLL Oscillator Circuit ...

Page 301: ...Rev 3 0 04 02 page 262 of 1064 ...

Page 302: ...Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider Start stop function 30 second adjustment function Alarm interrupts Comparison with second minute hour day of week day month or year SH7751R only can be selected as the alarm interrupt condition Periodic interrupts An interrupt period of 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second or 2 se...

Page 303: ...I PRI CUI RCR1 RCR2 RCR3 RYRCNT RYRAR RMONCNT RWKCNT RDAYCNT RHRCNT RMINCNT RSECCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR Prescaler RTC crystal oscillator RTC operation control unit RESET STBY etc Counter unit Interrupt control unit To registers Bus interface Internal peripheral module bus Note SH7751R only Figure 11 1 Block Diagram of RTC ...

Page 304: ...he RTC power supply pins even when the RTC is not used 11 1 4 Register Configuration Table 11 2 summarizes the RTC registers Table 11 2 RTC Registers Initialization Name Abbrevia tion R W Power On Reset Manual Reset Standby Mode Initial Value P4 Address Area 7 Address Access Size 64 Hz counter R64CNT R Counts Counts Counts Undefined H FFC80000 H 1FC80000 8 Second counter RSECCNT R W Counts Counts ...

Page 305: ...k alarm register RWKAR R W Initialized 1 Held Held Undefined 1 H FFC8002C H 1FC8002C 8 Day alarm register RDAYAR R W Initialized 1 Held Held Undefined 1 H FFC80030 H 1FC80030 8 Month alarm register RMONAR R W Initialized 1 Held Held Undefined 1 H FFC80034 H 1FC80034 8 RTC control register 1 RCR1 R W Initialized Initialized Held H 00 3 H FFC80038 H 1FC80038 8 RTC control register 2 RCR2 R W Initial...

Page 306: ...not be modified Bit 7 6 5 4 3 2 1 0 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R R R R 11 2 2 Second Counter RSECCNT RSECCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded second value in the RTC It counts on the carry transition of the R69CNT 1Hz bit from 0...

Page 307: ...ts Initial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R W R W R W R W R W R W R W 11 2 4 Hour Counter RHRCNT RHRCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded hour value in the RTC It counts on the carry generated once per hour by the minute counter The setting range is decimal 00 to 23 The RTC will not o...

Page 308: ...ate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RWKCNT is not initialized by a power on or manual reset or in standby mode Bits 7 to 3 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 Day of week code Initial value 0 0 0 0 0 Unde...

Page 309: ...rmed according to whether or not the value is divisible by 400 100 and 4 Bits 7 and 6 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 10 day units 1 day units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R R R W R W R W R W R W R W 11 2 7 Month Counter RMONCNT RMONCNT is an 8 bit readable writable...

Page 310: ... 0000 to 9999 The RTC will not operate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RYRCNT is not initialized by a power on or manual reset or in standby mode Bit 15 14 13 12 11 10 9 8 1000 year units 100 year units Initial value Undefined Undefined Undefined Undefined Undefined Undefined Unde...

Page 311: ...tial value 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W R W R W R W R W R W R W 11 2 10 Minute Alarm Register RMINAR RMINAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded minute value counter RMINCNT When the ENB bit is set to 1 the RMINAR value is compared with the RMINCNT value Comparison between the counter and the...

Page 312: ...value should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 10 hour units 1 hour units Initial value 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R W R R W R W R W R W R W R W 11 2 12 Day of Week Alarm Register RWKAR RWKAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded day of week value counter RWKCNT When the ENB bit is set to 1 the RWKAR valu...

Page 313: ...AR RWKAR RDAYAR and RMONAR in which the ENB bit is set to 1 and the RCR1 alarm flag is set when the respective values all match The setting range is decimal 01 to 31 ENB bit The RTC will not operate normally if any other value is set The setting range for RDAYAR depends on the month and whether the year is a leap year so care is required when making the setting The ENB bit in RDAYAR is initialized...

Page 314: ...et The other fields in RMONAR are not initialized by a power on or manual reset or in standby mode Bits 6 and 5 are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 7 6 5 4 3 2 1 0 ENB 10 month unit 1 month units Initial value 0 0 0 Undefined Undefined Undefined Undefined Undefined R W R W R R R W R W R W R W R W 11 2 15 RTC Control Register 1 RCR1 RCR1 ...

Page 315: ...er is read Setting conditions Generation of a second counter carry or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF Bit 4 Carry Interrupt Enable Flag CIE Enables or disables interrupt generation when the carry flag CF is set to 1 Bit 4 CIE Description 0 Carry interrupt is not generated when CF flag is set to 1 Initial value 1 Carry interrupt is generated when CF flag...

Page 316: ...2 and 1 Reserved The initial value of these bits is undefined A write to these bits is invalid but the write value should always be 0 11 2 16 RTC Control Register 2 RCR2 RCR2 is an 8 bit readable writable register used for periodic interrupt control 30 second adjustment and frequency divider RESET and RTC count control RCR2 is basically initialized to H 09 by a power on reset except that the value...

Page 317: ...PES2 PES0 These bits specify the period for periodic interrupts Bit 6 PES2 Bit 5 PES1 Bit 4 PES0 Description 0 0 0 No periodic interrupt generation Initial value 1 Periodic interrupt generated at 1 256 second intervals 1 0 Periodic interrupt generated at 1 64 second intervals 1 Periodic interrupt generated at 1 16 second intervals 1 0 0 Periodic interrupt generated at 1 4 second intervals 1 Period...

Page 318: ...vider circuits are initialized by writing 1 to this bit When 1 is written to the RESET bit the frequency divider circuits RTC prescaler and R64CNT are reset and the RESET bit is automatically cleared to 0 i e does not need to be written with 0 Bit 1 RESET Description 0 Normal clock operation Initial value 1 Frequency divider circuits are reset Bit 0 Start Bit START Stops and restarts counter clock...

Page 319: ...999 and normal operation is not obtained if a value beyond this range is set here RCR3 is initialized by a power on reset but RYRAR will not be initialized by a power on or manual reset or by the device entering standby mode Bits 6 to 0 of RCR3 are always read as 0 A write to these bits is invalid If a value is written to these bits it should always be 0 RCR3 Bit 7 6 5 4 3 2 1 0 YENB Initial value...

Page 320: ...er Set RCR2 START to 1 a Setting time after stopping clock Clear carry flag Write to counter register Carry flag 1 No Yes Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Set RYRCNT first and RSECCNT last Read RCR1 register and check CF bit b Setting time while clock is running Figure 11 2 Examples of Time Setting Procedures The procedure for setting the time after stopping ...

Page 321: ...ata If a carry occurs during the write operation the write data is automatically updated and there will be an error in the set data The carry flag should therefore be used to check the write status If the carry flag RCR1 CF is set to 1 the write must be repeated The interrupt function can also be used to determine the carry flag status 11 3 2 Time Reading Procedures Figure 11 3 shows examples of t...

Page 322: ...t generated Yes Disable carry interrupts No b Reading time using interrupts Set RCR1 CIE to 1 Clear RCR1 CF to 0 Write 1 to RCR1 AF so that alarm flag is not cleared Clear RCR1 CIE to 0 Figure 11 3 Examples of Time Reading Procedures If a carry occurs while the time is being read the correct time will not be obtained and the read must be repeated The procedure for reading the time without using in...

Page 323: ... only value or a combination of these Write 1 to the ENB bit in the alarm registers involved in the alarm setting and set the alarm time in the lower bits Write 0 to the ENB bit in registers not involved in the alarm setting When the counter and the alarm time match RCR1 AF is set to 1 Alarm detection can be confirmed by reading this bit but normally an interrupt is used If 1 has been written to R...

Page 324: ...o set to 1 11 5 Usage Notes 11 5 1 Register Initialization After powering on and making the RCR1 register settings reset the frequency divider by setting RCR2 RESET to 1 and make initial settings for all the other registers 11 5 2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode from standby mode by a ...

Page 325: ...oard 4 The crystal oscillation stabilization time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins 6...

Page 326: ... Selection of seven counter input clocks for channels 0 to 2 External clock TCLK on chip RTC output clock five internal clocks P 4 P 16 P 64 P 256 P 1024 P is the peripheral module clock Selection of five internal clocks for channels 3 and 4 Channels 0 to 2 can also operate in module standby mode when the on chip RTC output clock is selected as the counter input clock that is timer operation conti...

Page 327: ...cy supplied to the on chip peripheral functions Counter unit Interrupt control unit Counter unit Interrupt control unit Counter unit Interrupt control unit Ch 0 1 Ch 2 Ch 3 4 TMU operation control unit Prescaler TCLK control unit To chan nels 0 to 4 To chan nels 0 to 2 Figure 12 1 Block Diagram of TMU 12 1 3 Pin Configuration Table 12 1 shows the TMU pins Table 12 1 TMU Pins Pin Name Abbreviation ...

Page 328: ...Timer counter 0 TCNT0 R W Ini tialized Ini tialized Held 2 H FFFFFFFF H FFD8000C H 1FD8000C 32 Timer control register 0 TCR0 R W Ini tialized Ini tialized Held H 0000 H FFD80010 H 1FD80010 16 1 Timer constant register 1 TCOR1 R W Ini tialized Ini tialized Held H FFFFFFFF H FFD80014 H 1FD80014 32 Timer counter 1 TCNT1 R W Ini tialized Ini tialized Held 2 H FFFFFFFF H FFD80018 H 1FD80018 32 Timer co...

Page 329: ...100018 32 Timer control register 4 TCR4 R W Ini tialized Held Held H 0000 H FE10001C H 1E10001C 16 Notes 1 Not initialized in module standby mode when the input clock is the on chip RTC output clock 2 Counts in module standby mode when the input clock is the on chip RTC output clock 12 2 Register Descriptions 12 2 1 Timer Output Control Register TOCR TOCR is an 8 bit readable writable register tha...

Page 330: ... that specifies whether the channel 0 2 timer counters TCNT are operated or stopped TSTR is initialized to H 00 by a power on or manual reset In module standby mode TSTR is not initialized when the input clock selected by each channel is the on chip RTC output clock RTCCLK and is initialized only when the input clock is the external clock TCLK or internal clock P Bit 7 6 5 4 3 2 1 0 STR2 STR1 STR0...

Page 331: ... channel 3 and 4 timer counters TCNT are operated or stopped TSTR2 is initialized to H 00 by a power on reset TSTR retain their contents in standby mode When standby mode is entered when the value of either STR3 or STR4 is 1 the count halts when the peripheral module clock stops and restarts when the clock supply is resumed Bit 7 6 5 4 3 2 1 0 STR4 STR3 Initial value 0 0 0 0 0 0 0 0 R W R R R R R ...

Page 332: ...rs in channels 3 and 4 are initialized to H FFFFFFFF by a power on reset but are not initialized and retain their contents by a manual reset or in standby mode Bit 31 30 29 2 1 0 Initial value 1 1 1 1 1 1 R W R W R W R W R W R W R W 12 2 5 Timer Counters TCNT The TCNT registers are 32 bit readable writable registers There are five TCNT registers one for each channel Each TCNT counts down on the in...

Page 333: ...gisters one for each channel Each TCR selects the count clock specifies the edge when an external clock is selected in channels 0 to 2 and controls interrupt generation when the flag indicating timer counter TCNT underflow is set to 1 TCR2 is also used for channel 2 input capture control and control of interrupt generation in the event of input capture The TCR registers in channels 0 to 2 are init...

Page 334: ... 0 UNIE TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R R R W R R R W R W R W Bits 15 to 9 7 and 6 Channels 0 and 1 Bits 15 to 10 Channel 2 Reserved These bits are always read as 0 A write to these bits is invalid but the write value should always be 0 Bit 9 Input Capture Interrupt Flag ICPF Channel 2 Only Status flag provided in channel 2 only that indicates the occurrence of input capture ...

Page 335: ...ge or falling edge of the TCLK signal is used to set the TCNT2 value in the input capture register TCPR2 The TCNT2 value is set in TCPR2 only when the TCR2 ICPF bit is 0 When the TCR2 ICPF bit is 1 TCPR2 is not set in the event of input capture When input capture occurs a DMAC transfer request is generated regardless of the value of the TCR2 ICPF bit However a new DMAC transfer request is not gene...

Page 336: ... on chip RTC output clock is selected as the count clock for a channel that channel can operate even in module standby mode When another clock is selected the channel does not operate in standby mode Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 Counts on P 4 Initial value 1 Counts on P 16 1 0 Counts on P 64 1 Counts on P 256 1 0 0 Counts on P 1024 1 Reserved Do not set 1 0 Counts on on ch...

Page 337: ... set to 1 at this time an interrupt request is sent to the CPU At the same time the value is copied from TCOR into TCNT and the count down continues auto reload function Example of Count Operation Setting Procedure Figure 12 2 shows an example of the count operation setting procedure 1 Select the count clock with bits TPSC2 TPSC0 in the timer control register TCR When an external clock in channels...

Page 338: ...r value Start count Note When an interrupt is generated clear the source flag in the interrupt handler If the interrupt enabled state is set without clearing the flag another interrupt will be generated Figure 12 2 Example of Count Operation Setting Procedure Auto Reload Count Operation Figure 12 3 shows the TCNT auto reload operation TCOR H 00000000 STR0 STR4 UNF TCNT value TCOR value set in TCNT...

Page 339: ...external clock In channels 0 to 2 external clock pin TCLK input can be selected as the timer clock by means of the TPSC2 TPSC0 bits in TCR The detected edge rising falling or both edges can be selected with the CKEG1 and CKEG0 bits in TCR Figure 12 5 shows the timing for both edge detection N 1 N 1 N Pφ External clock input pin TCNT Figure 12 5 Count Timing when Operating on External Clock Operati...

Page 340: ...ting clock 3 Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function and whether interrupts are to generated when this function is used 4 Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter TCNT value in the input capture register TCPR2 This function cannot be used in standby mode When input ca...

Page 341: ...ture function is used Underflow interrupts are generated on channels 0 to 4 and input capture interrupts on channel 2 only An underflow interrupt request is generated on an individual channel basis when TCR UNF 1 and the channel s interrupt enable bit is 1 When the input capture function is used and an input capture request is generated an interrupt is requested if the input capture input flag ICP...

Page 342: ...the timer control registers TRCR0 to TCR4 can be cleared while the count is in progress When the flags UNF and ICPF are cleared while the count is in progress make sure not to change the values of bits other than those being cleared 12 5 2 TCNT Register Reads When performing a TCNT register read processing for synchronization with the timer count operation is performed If a timer count operation a...

Page 343: ...Rev 3 0 04 02 page 304 of 1064 ...

Page 344: ...a 0 which uses an external pin setting Wait state insertion by pin Wait state insertion can be controlled by program Specification of types of memory connectable to each area Output the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas or a read access followed by a write access to the same...

Page 345: ...tion executing the number of transfers set in a register Connectable areas 0 5 6 Settable bus widths 32 16 8 MPX interface Address data multiplexing Connectable areas 0 to 6 Settable bus widths 32 Byte control SRAM interface SRAM interface with byte control Connectable areas 1 4 Settable bus widths 32 16 PCMCIA interface Wait state insertion can be controlled by program Bus sizing function for I O...

Page 346: ... unit Wait control unit Interrupt controller BSC Peripheral bus WCR Wait control register BCR Bus control register MCR Memory control register PCR PCMCIA control register Note SH7751R only WCR2 WCR3 BCR1 BCR2 BCR3 BCR4 PCR RFCR MCR Module bus RFCR Refresh count register RTCNT Refresh timer count register RTCOR Refresh time constant register RTCSR Refresh timer control status register Figure 13 1 B...

Page 347: ...nation signal Also used as the DRAM synchronous DRAM PCMCIA interface write designation signal Row address strobe O signal when setting DRAM synchronous DRAM interface Read column address strobe cycle frame O Strobe signal that indicates a read cycle When setting synchronous DRAM interface signal When setting MPX interface signal Data enable 0 O When setting PCMCIA interface signal When setting SR...

Page 348: ...24 Ready I Wait state request signal Area 0 MPX interface specification 16 bit I O MD6 I In power on reset Designates area 0 bus as MPX interface 1 SRAM 0 MPX When setting PCMCIA interface 16 bit I O designation signal Valid only in little endian mode Clock enable CKE O Synchronous DRAM clock enable control signal Bus release request I Bus release request signal bus acknowledge signal Bus use perm...

Page 349: ...l register 3 2 BCR3 R W H 0000 H FF80 0050 H 1F80 0050 16 Bus control register 4 2 BCR4 R W H 0000 0000 H FE0A 00F0 H 1E0A 00F0 32 Wait state control register 1 WCR1 R W H 7777 7777 H FF80 0008 H 1F80 0008 32 Wait state control register 2 WCR2 R W H FFFE EFFF H FF80 000C H 1F80 000C 32 Wait state control register 3 WCR3 R W H 0777 7777 H FF80 0010 H 1F80 0010 32 Memory control register MCR R W H 0...

Page 350: ...ected to area 2 or 3 signals such as RD and DQM are also asserted When the PCMCIA interface is selected for area 5 or 6 is asserted in addition to for the byte to be accessed H 0000 0000 H 8000 0000 H A000 0000 H C000 0000 H E000 0000 H FFFF FFFF H E400 0000 H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800 0000 H 1FFF FFFF H 1C00 0000 Area 0 Area 1 Area 2 Area 3 Area ...

Page 351: ...Byte control RAM 16 32 2 8 16 32 64 6 bits 32 bytes 5 64 Mbytes SRAM 8 16 32 2 MPX 32 2 Burst ROM 8 16 32 2 H 14000000 H 17FFFFFF PCMCIA 8 16 2 4 8 16 32 64 6 bits 32 bytes 6 64 Mbytes SRAM 8 16 32 2 MPX 32 2 Burst ROM 8 16 32 2 H 18000000 H 1BFFFFFF PCMCIA 8 16 2 4 8 16 32 64 6 bits 32 bytes 7 5 H 1C000000 H 1FFFFFFF 64 Mbytes Notes 1 Memory bus width specified by external pins 2 Memory bus width...

Page 352: ...xternal pins The relationship between the external pins MD4 and MD3 and the bus width in a power on reset is shown below MD4 MD3 Bus Width 0 0 Reserved 1 8 bits 1 0 16 bits 1 32 bits When SRAM interface or ROM is used in areas 1 to 6 a bus width of 8 16 or 32 bits can be selected with bus control register 2 BCR2 When burst ROM is used a bus width of 8 16 or 32 bits can be selected When byte contro...

Page 353: ...ry card interface and I O card interface stipulated in JEIDA specifications version 4 2 PCMCIA2 1 External memory space areas 5 and 6 support both the IC memory card interface and the I O card interface The PCMCIA interface is supported only in little endian mode Table 13 4 PCMCIA Interface Features Item Features Access Random access Data bus 8 16 bits Memory type Mask ROM OTPROM EPROM EEPROM flas...

Page 354: ...I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 I Write enable I Write enable 16 O Ready busy O Interrupt request Sensed on port 17 VCC Operating power supply VCC Operating power supply 18 VPP1 Programming power supply VPP1 Programming peripheral power supply 19 A16 I Address A16 I Address A16 20...

Page 355: ...I O Data D12 I O Data D12 39 D13 I O Data D13 I O Data D13 40 D14 I O Data D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 I Card enable I Card enable or 43 RFSH I Refresh request RFSH I Refresh request Output from port 44 RFU Reserved I I O read 45 RFU Reserved I I O write 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Addres...

Page 356: ...ort 59 O Wait request O Wait request 60 RFU Reserved O Input acknowledge 61 I Attribute memory space select I Attribute memory space select 62 BVD2 O Battery voltage detection O Digital speech signal Sensed on port 63 BVD1 O Battery voltage detection O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 O Card detection ...

Page 357: ...on is completed Bit 31 30 29 28 27 26 25 24 ENDIAN MASTER A0MPX DPUP IPUP OPUP Initial value 0 1 0 1 0 1 0 0 0 0 0 R W R R R R R R W R W R W Bit 23 22 21 20 19 18 17 16 A1MBC A4MBC BREQEN MEMMPX DMABST Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R W R R W R W Bit 15 14 13 12 11 10 9 8 HIZMEM HIZCNT A0BST2 A0BST1 A0BST0 A5BST2 A5BST1 A5BST0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R ...

Page 358: ...et the master slave setting external pin MD7 is low designating slave mode for the SH7751 Series Bit 29 Area 0 Memory Type A0MPX Samples the value of the area 0 memory type specification external pin MD6 in a power on reset by means of the pin The memory type of area 0 is determined by this bit A0MPX is a read only bit Bit 29 A0MPX Description 0 In a power on reset the external pin specifying the ...

Page 359: ...ialized by a power on reset Bit 24 OPUP Description 0 Pull up resistor is on for control output pins A 25 0 RD MD5 Initial value 1 Pull up resistor is off for control output pins A 25 0 RD MD5 Bit 21 Area 1 SRAM Byte Control Mode A1MBC MPX interface has priority when an MPX interface is set This bit is initialized by a power on reset Bit 21 A1MBC Description 0 Area 1 SRAM is set to normal mode Ini...

Page 360: ...selected when areas 1 to 6 are set as SRAM interface or burst ROM interface Initial value 1 MPX interface is selected when areas 1 to 6 are set as SRAM interface or burst ROM interface Bit 16 DMAC Burst Mode Transfer Priority Setting DMABST Specifies the priority of burst mode transfers by the DMAC When OFF the priority is as follows bus privilege released refresh DMAC CPU When ON the bus privileg...

Page 361: ...specify the number of accesses in a burst If area 0 is an MPX interface area these bits are ignored Bit 13 A0BST2 Bit 12 A0BST1 Bit 11 A0BST0 Description 0 0 0 Area 0 is accessed as SRAM interface Initial value 1 Area 0 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 0 is accessed as burst ROM interface 8 consecutive accesses Can be used...

Page 362: ...rface Initial value 1 Area 5 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 5 is accessed as burst ROM interface 8 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 Area 5 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not specify for 32 bit bus width 1 0 0 Area 5...

Page 363: ...ace Initial value 1 Area 6 is accessed as burst ROM interface 4 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 0 Area 6 is accessed as burst ROM interface 8 consecutive accesses Can be used with 8 16 or 32 bit bus width 1 Area 6 is accessed as burst ROM interface 16 consecutive accesses Can only be used with 8 or 16 bit bus width Do not specify for 32 bit bus width 1 0 0 Area 6 i...

Page 364: ...as 2 and 3 are accessed as synchronous DRAM interface 1 0 0 Area 2 is accessed as SRAM interface or MPX interface area 3 is DRAM interface 1 Reserved Cannot be set 1 0 Reserved Cannot be set 1 Reserved Cannot be set Note Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit Bit 0 Area 5 and 6 Bus Type A56PCM Specifies whether areas 5 and 6 are accessed as PCMC...

Page 365: ...ompleted Bit 15 14 13 12 11 10 9 8 A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 Initial value 0 1 0 1 1 1 1 1 1 1 R W R R R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 PORTEN Initial value 1 1 1 1 1 1 0 0 R W R W R W R W R W R W R W R W Note These bits sample the values of the external pins that specify the area 0 bus size Bits 15 and 14 Area 0 Bus Width A0SZ1 ...

Page 366: ...e PORTEN Specifies whether pins AD31 to AD0 are used as a 32 bit port However select PCI disable mode when using this function Bit 0 PORTEN Description 0 AD31 to AD0 are not used as a port Initial value 1 AD31 to AD0 are used as a port 13 2 3 Bus Control Register 3 BCR3 SH7751R Only Bus control register 3 BCR3 is a 16 bit readable writable register that specifies the selection of either the MPX in...

Page 367: ... selected by A1MPX and A4MPX Bits 14 13 MPX Interface Specification for Area 1 and 4 A1MPX A4MPX These bits specify the types of memory connected to areas 1 and 4 These settings are validated by MEMMODE Bit 14 A1MPX Description 0 SRAM byte control SRAM interface is selected for area 1 Initial value 1 MPX interface is selected for area 1 Bit 13 A4MPX Description 0 SRAM byte control SRAM interface i...

Page 368: ...NCn 0 see figure 13 4 The timings shown in this section and section 23 Electrical Characteristics are all for the case where synchronous input is set ASYNCn 0 Note With the synchronous input setting ensure that setup and hold times are observed Bit 31 30 29 28 27 26 25 24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R...

Page 369: ... 0 ASYNCn Description 0 Corresponding pin is synchronous input with respect to CKIO Initial value 1 Asynchronous input with respect to CKIO is enabled for corresponding pin Bit 4 3 2 1 0 T1 Tw Tw Twe T2 CKIO BCR4 ASYNC0 0 BCR4 ASYNC0 1 Figure 13 4 Example of Sampling Timing at which BCR4 is Set Two Wait Cycles are Inserted by WCR2 ...

Page 370: ...eset but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 DMAIW2 DMAIW1 DMAIW0 A6IW2 A6IW1 A6IW0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 23 22 21 20 19 18 17 16 A5IW2 A5IW1 A5IW0 A4IW2 A4IW1 A4IW0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 15 14 13 12 11 10 9 8 A3IW2 A3IW1 A3IW0 A2IW2 A2IW1 A2IW0 Initial value 0 1 ...

Page 371: ... Area n 6 to 0 Inter Cycle Idle Specification AnlW2 AnlW0 These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n n 6 to 0 to another space or from a read access to a write access in the same space DMAIW2 AnIW2 DMAIW1 AnIW1 DMAIW0 AnIW0 Inserted Idle Cycles 0 0 0 0 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 Initial value ...

Page 372: ...interface a WCR1 idle wait may be inserted before an access either read or write to the same area after a write access The specific conditions for idle wait insertion in accesses to the same area are shown below a Synchronous DRAM set to RAS down mode b Synchronous DRAM accessed by on chip DMAC Apart from use under above conditions a and b an idle wait is also inserted between an MPX interface wri...

Page 373: ...F by a power on reset but is not initialized by a manual reset or in standby mode Bit 31 30 29 28 27 26 25 24 A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 Initial value 1 1 1 1 1 1 1 0 R W R W R W R W R W R W R W R W R Bit 15 14 13 12 11 10 9 8 A3W2 A3W1 A3W0 A2W2 A2W1 A2W0 A...

Page 374: ...ed 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 28 to 26 Area 6 Burst Pitch A6B2 A6B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 28 A6B2 Bit 27 A6B1 Bit 26 A6B0 Wait States Inserted from Second Data ...

Page 375: ...ed 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 22 to 20 Area 5 Burst Pitch A5B2 A5B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 22 A5B2 Bit 21 A5B1 Bit 20 A5B0 Wait States Inserted from Second Data ...

Page 376: ... 12 Reserved These bits are always read as 0 and should only be written with 0 Bits 15 to 13 Area 3 Wait Control A3W2 A3W0 These bits specify the number of wait states to be inserted for area 3 External wait input is only enabled when the SRAM interface or MPX interface is used and is ignored when DRAM or synchronous DRAM is used For the case where an MPX interface setting is made see table 13 7 W...

Page 377: ...mode Bits 11 to 9 Area 2 Wait Control A2W2 A2W0 These bits specify the number of wait states to be inserted for area 2 External wait input is only enabled when the SRAM interface or MPX interface is used and is ignored when synchronous DRAM is used For the case where an MPX interface setting is made see table 13 7 When SRAM Interface is Set Description Bit 11 A2W2 Bit 10 A2W1 Bit 9 A2W0 Inserted W...

Page 378: ...ernal wait input is always ignored 2 Inhibited in RAS down mode Bits 8 to 6 Area 1 Wait Control A1W2 A1W0 These bits specify the number of wait states to be inserted for area 1 For the case where an MPX interface setting is made see table 13 7 Description Bit 8 A1W2 Bit 7 A1W1 Bit 6 A1W0 Inserted Wait States Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 ...

Page 379: ...led 1 3 Enabled 1 0 0 6 Enabled 1 9 Enabled 1 0 12 Enabled 1 15 Initial value Enabled Bits 2 to 0 Area 0 Burst Pitch A0B2 A0B0 These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer Description Burst Cycle Excluding First Cycle Bit 2 A0B2 Bit 1 A0B1 Bit 0 A0B0 Wait States Inserted from Second Data Acce...

Page 380: ... Interface is Set Areas 0 to 6 Description Inserted Wait States 1st Data AnW2 AnW1 AnW0 Read Write 2nd Data Onward Pin 0 0 0 1 0 0 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled 1 0 0 1 0 1 Enabled 1 1 Enabled 1 0 2 2 Enabled 1 3 3 Enabled n 6 to 0 ...

Page 381: ...29 28 27 26 25 24 A6S0 A6H1 A6H0 Initial value 0 0 0 0 0 1 1 1 R W R R R R R R W R W R W Bit 23 22 21 20 19 18 17 16 A5S0 A5H1 A5H0 A4RDH A4S0 A4H1 A4H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Bit name A3S0 A3H1 A3H0 A2S0 A2H1 A2H0 Initial value 0 1 1 1 0 1 1 1 R W R R W R W R W R R W R W R W Bit 7 6 5 4 3 2 1 0 A1RDH A1S0 A1H1 A0H0 A0S0 A0H1 A0H0 ...

Page 382: ...f cycles to be inserted in the hold time from the data sampling timing Valid only for SRAM interface byte control SRAM interface and burst ROM interface Bit 4n 1 AnH1 Bit 4n AnH0 Waits Inserted in Hold 0 0 0 1 1 1 0 2 1 3 Initial value n 6 to 0 Bits 4n 3 Area n 4 or 1 Read Strobe Negate Timing AnRDH Setting Only Possible in the SH7751R When reading these bits specify the timing for the negation of...

Page 383: ...wing a power on reset and should not be modified subsequently When writing to bits RFSH and RMODE the same values should be written to the other bits so that they remain unchanged When using DRAM or synchronous DRAM areas 2 and 3 should not be accessed until register initialization is completed Bit 31 30 29 28 27 26 25 24 RASD MRSET TRC2 TRC1 TRC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W ...

Page 384: ...ode register setting is used See Power On Sequence in section 13 3 5 Synchronous DRAM Interface Bit 30 MRSET Description 0 All bank precharge Initial value 1 Mode register setting Bits 26 to 24 22 and 18 Reserved These bits should only be written with 0 Bits 29 to 27 RAS Precharge Time at End of Refresh TRC2 TRC0 Synchronous DRAM auto and self refresh both enabled DRAM auto and self refresh both e...

Page 385: ...t these bits set the bank active read write command delay time Description Bit 17 RCD1 Bit 16 RCD0 DRAM Synchronous DRAM 0 0 2 cycles Reserved Setting prohibited 1 3 cycles 2 cycles 1 0 4 cycles 3 cycles 1 5 cycles 4 cycles Note Inhibited in RAS down mode Bits 15 to 13 Write Precharge Delay TRWL2 TRWL0 These bits set the synchronous DRAM write precharge delay time In auto precharge mode they speci...

Page 386: ...synchronous DRAM interface is set the bank active command is not issued for a period of TRC TRAS after an auto refresh command is issued Bit 12 TRAS2 Bit 11 TRAS1 Bit 10 TRAS0 DRAM Assertion Time Command Interval after Synchronous DRAM Refresh 0 0 0 2 4 TRC Initial value 1 3 5 TRC 1 0 4 6 TRC 1 5 7 TRC 1 0 0 6 8 TRC 1 7 9 TRC 1 0 8 10 TRC 1 9 11 TRC Note Bits 29 to 27 RAS precharge interval at end...

Page 387: ...eserved Setting prohibited Reserved Setting prohibited 1 0 16 bits Reserved Setting prohibited 1 32 bits 32 bits Bits 6 to 3 Address Multiplexing AMXEXT AMX2 AMX0 These bits specify address multiplexing for DRAM and synchronous DRAM The address shift value is different for the DRAM interface and the synchronous DRAM interface For DRAM Interface Description Bit 6 AMXEXT Bit 5 AMX2 Bit 4 AMX1 Bit 3 ...

Page 388: ...2 RFSH Description 0 Refreshing is not performed Initial value 1 Refreshing is performed Bit 1 Refresh Mode RMODE Specifies whether normal refreshing or self refreshing is performed when the RFSH bit is set to 1 When the RFSH bit is 1 and this bit is cleared to 0 CAS before RAS refreshing or auto refreshing is performed for DRAM and synchronous DRAM using the cycle set by refresh related registers...

Page 389: ...t 15 14 13 12 11 10 9 8 Bit name A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Bit name A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 and 14 PCMCIA Wait A5PCW1 A5PCW0 These bits specify the number of waits to be added to...

Page 390: ...WE Assertion Delay A6TED2 A6TED0 These bits set the delay time from address output to assertion on the connected PCMCIA interface The setting of these bits is selected when the PCMCIA interface access TC bit is 0 Bit 8 A6TED2 Bit 7 A6TED1 Bit 6 A6TED0 Waits Inserted 0 0 0 0 Initial value 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 Bits 5 to 3 OE WE Negation Address Delay A5TEH2 A5TEH0 These bits set the...

Page 391: ...ss hold delay time from the data sampling timing is set The setting of these bits is selected when the PCMCIA interface access TC bit is 0 Bit 2 A6TEH2 Bit 1 A6TEH1 Bit 0 A6TEH0 Waits Inserted 0 0 0 0 Initial value 1 1 1 0 2 1 3 1 0 0 6 1 9 1 0 12 1 15 13 2 10 Synchronous DRAM Mode Register SDMR The synchronous DRAM mode register SDMR is a write only virtual 16 bit register that is written to via ...

Page 392: ...ted 2 bits to the right For example to write H 0230 to the area 2 SDMR register arbitrary data is written to address H FF900000 address Y H 08C0 value X H FF9008C0 As a result H 0230 is written to the SDMR register The range of value X is H 0000 to H 0FFC Similarly to write H 0230 to the area 3 SDMR register arbitrary data is written to address H FF940000 address Y H 08C0 value X H FF9408C0 As a r...

Page 393: ...served 110 Reserved 110 Reserved 111 Reserved 111 Reserved Note SH7751R only 13 2 11 Refresh Timer Control Status Register RTCSR The refresh timer control status register RTCSR is a 16 bit readable writable register that specifies the refresh cycle and whether interrupts are to be generated RTSCR is initialized to H 0000 by a power on reset but is not initialized by a manual reset or in standby mo...

Page 394: ...etained Bit 6 Compare Match Interrupt Enable CMIE Controls generation or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR Do not set this bit to 1 when CAS before RAS refreshing or auto refreshing is used Bit 6 CMIE Description 0 Interrupt requests initiated by CMF are disabled Initial value 1 Interrupt requests initiated by CMF are enabled Bits 5 to 3 Clock Select Bits C...

Page 395: ...rrupt requests initiated by OVF are disabled Initial value 1 Interrupt requests initiated by OVF are enabled Bit 0 Refresh Count Overflow Limit Select LMTS Specifies the count limit to be compared with the refresh count indicated by the refresh count register RFCR If the RFCR register value exceeds the value specified by LMTS the OVF flag is set Bit 0 LMTS Description 0 Count limit is 1024 Initial...

Page 396: ...ts are constantly compared and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0 If the refresh bit RFSH has been set to 1 in the memory control register MCR and CAS before RAS has been selected as the refresh mode a memory refresh cycle is generated when the CMF bit is set RTCOR is initialized to H 0000 by a power on reset but is not initialized and re...

Page 397: ... 0 0 R W R W R W R W R W R W R W R W R W 13 2 15 Notes on Accessing Refresh Control Registers When the refresh timer control status register RTCSR refresh timer counter RTCNT refresh time constant register RTCOR and refresh count register RFCR are written to a special code is added to the data to prevent inadvertent rewriting in the event of program runaway etc The following procedures should be u...

Page 398: ...r the PCMCIA interface Data alignment is carried out according to the data bus width and endian mode of each device Accordingly when the data bus width is narrower than the access size multiple bus cycles are automatically generated to reach the access size In this case access is performed by automatically incrementing addresses to the bus width For example when a long word access is performed at ...

Page 399: ...s Strobe Signals Access Size Address No D31 D24 D23 D16 D15 D8 D7 D0 DQM3 DQM2 DQM1 DQM0 Byte 4n 1 Data 7 0 Asserted 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Quad word 8n 1 Data 63 56...

Page 400: ...QM1 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Asserted Asserted 4n 2 2 Data 15 8 Data 7 0 Asserted Asserted Quad word 8n 1 Data 63 56 Data 55 48 Asserted Asserted 8n 2 2 Data 47 40 Data 39 32 Asserted Asserted 8n 4 3 Data 31 24 Data 23 16 Asserted Asserted 8n 6 4 Data 15 8 Data 7 0 Asserted Asserted...

Page 401: ...te n 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Asserted 2n 1 2 Data 7 0 Asserted Long word 4n 1 Data 31 24 Asserted 4n 1 2 Data 23 16 Asserted 4n 2 3 Data 15 8 Asserted 4n 3 4 Data 7 0 Asserted Quad word 8n 1 Data 63 56 Asserted 8n 1 2 Data 55 48 Asserted 8n 2 3 Data 47 40 Asserted 8n 3 4 Data 39 32 Asserted 8n 4 5 Data 31 24 Asserted 8n 5 6 Data 23 16 Asserted 8n 6 7 Data 15 8 Asserted 8n 7 8 Data ...

Page 402: ...ed 4n 1 1 Data 7 0 Asserted 4n 2 1 Data 7 0 Asserted 4n 3 1 Data 7 0 Asserted Word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted Quad word 8n 1 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Asserted Asserted Asserted Asserted 8n 4 2 Data 63 56 Data 55 48 Data 47 40 Data 39...

Page 403: ... DQM1 DQM0 Byte 2n 1 Data 7 0 Asserted 2n 1 1 Data 7 0 Asserted Word 2n 1 Data 15 8 Data 7 0 Asserted Asserted Long word 4n 1 Data 15 8 Data 7 0 Asserted Asserted 4n 2 2 Data 31 24 Data 23 16 Asserted Asserted Quad word 8n 1 Data 15 8 Data 7 0 Asserted Asserted 8n 2 2 Data 31 24 Data 23 16 Asserted Asserted 8n 4 3 Data 47 40 Data 39 32 Asserted Asserted 8n 6 4 Data 63 56 Data 55 48 Asserted Assert...

Page 404: ...yte n 1 Data 7 0 Asserted Word 2n 1 Data 7 0 Asserted 2n 1 2 Data 15 8 Asserted Long word 4n 1 Data 7 0 Asserted 4n 1 2 Data 15 8 Asserted 4n 2 3 Data 23 16 Asserted 4n 3 4 Data 31 24 Asserted Quad word 8n 1 Data 7 0 Asserted 8n 1 2 Data 15 8 Asserted 8n 2 3 Data 23 16 Asserted 8n 3 4 Data 31 24 Asserted 8n 4 5 Data 39 32 Asserted 8n 5 6 Data 47 40 Asserted 8n 6 7 Data 55 48 Asserted 8n 7 8 Data 6...

Page 405: ...hold time can be set respectively to 0 or 1 and to 0 to 3 cycles using the A0S0 A0H1 and A0H0 bits in the WCR3 register Area 1 For area 1 external address bits A28 to A26 are 001 SRAM MPX and byte control SRAM can be set for this area A bus width of 8 16 or 32 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register When MPX interface is set a bus width of 32 bit should be selected with...

Page 406: ... and bits A2H1 and A2H0 in the WCR3 register When synchronous DRAM interface is set the and signals RD signal and byte control signals DQM0 to DQM3 are asserted and address multiplexing is performed and data timing control and address multiplexing control can be set using the MCR register Area 3 For area 3 external address bits A28 to A26 are 011 SRAM MPX DRAM and synchronous DRAM can be set to th...

Page 407: ... as and write control signals to are also asserted As regards the number of bus cycles from 0 to 15 waits can be selected with bits A4W2 to A4W0 in the WCR2 register In addition any number of waits can be inserted in each bus cycle by means of the external wait pin The read write strobe signal address and setup and hold times can be set within a range of 0 1 and 0 3 cycles respectively by means of...

Page 408: ... external address bits A28 to A26 are 110 SRAM MPX burst ROM and a PCMCIA interface can be set to this area When SRAM interface is set a bus width of 8 16 or 32 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register When burst ROM interface is set a bus width of 8 16 or 32 bits can be selected with bits A6SZ1 and A6SZ0 in BCR2 When MPX interface is set a bus width of 32 bit should be ...

Page 409: ...ormal space accesses A no wait normal access is completed in two cycles The signal is asserted for one cycle to indicate the start of a bus cycle The signal is asserted on the T1 rising edge and negated on the next T2 clock rising edge Therefore there is no negation period in case of access at minimum pitch There is no access size specification when reading The correct access address is output to ...

Page 410: ... 3 0 04 02 page 371 of 1064 T1 CKIO A25 A0 RD D31 D0 read D31 D0 write T2 DACKn SA IO memory DACKn SA IO memory DACKn DA SA DA Single address DMA Dual address DMA Figure 13 6 Basic Timing of SRAM Interface ...

Page 411: ... 9 show examples of connection to 32 16 and 8 bit data width SRAM A16 A0 I O7 I O0 A18 A2 D31 D24 D23 D16 D15 D8 D7 D0 SH7751 Series 128k 8 bit SRAM A16 A0 I O7 I O0 A16 A0 I O7 I O0 A16 A0 I O7 I O0 Figure 13 7 Example of 32 Bit Data Width SRAM Connection ...

Page 412: ...Rev 3 0 04 02 page 373 of 1064 A16 A0 I O7 I O0 A17 A1 D15 D8 D7 D0 SH7751 Series 128k 8 bit SRAM A16 A0 I O7 I O0 Figure 13 8 Example of 16 Bit Data Width SRAM Connection ...

Page 413: ...n the SRAM interface can be controlled by the WCR2 settings If the WCR2 wait specification bits corresponding to a particular area are not zero a software wait is inserted in accordance with that specification For details see section 13 2 5 Wait Control Register 2 WCR2 The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 13 10 ...

Page 414: ...T1 CKIO A25 A0 RD D31 D0 read D31 D0 write Tw T2 DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 10 SRAM Interface Wait Timing Software Wait Only ...

Page 415: ... transition from the Tw state to the T2 state therefore the signal has no effect if asserted in the T1 cycle or the first Tw cycle The signal is sampled on the rising edge of the clock T1 CKIO A25 A0 RD read D31 D0 read write D31 D0 write Tw Twe T2 DACKn SA IO memory DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 11 SRAM Interfac...

Page 416: ...A4RDH bits of the WCR3 register For information about this setting see the description of the WCR3 register When a byte control SRAM setting is made AnRDH should be cleared to 0 TS1 CKIO A25 A0 RD RD D31 D0 T1 Tw Tw Tw Tw T2 TH1 TH2 TS1 Setup wait WCR3 AnS 0 to 1 Tw Access wait WCR2 AnW 0 to 15 TH1 TH2 Hold wait WCR3 AnH 0 to 3 Note When AnRDH is set to 1 Figure 13 12 SRAM Interface Wait State Tim...

Page 417: ...e data width 2 CAS 16 bit DRAMs can be connected since is used to control byte access Signals used for connection are to and RD to are not used when the data width is 16 bits In addition to normal read and write access modes fast page mode is supported for burst access EDO mode which enables the DRAM access time to be increased is supported A10 A2 RD D31 D16 D15 D0 SH7751 Series 256k 16 bit DRAM A...

Page 418: ...ect to address multiplexing are A17 to A1 The address signals output by pins A25 to A18 are undefined Table 13 14 Relationship between AMXEXT and AMX2 0 Bits and Address Multiplexing Setting External Address Pins AMXEXT AMX2 AMX1 AMX0 Number of Column Address Bits Output Timing A1 A13 A14 A15 A16 A17 0 0 0 0 8 bits Column address A1 A13 A14 A15 A16 A17 Row address A9 A21 A22 A23 A24 A25 1 9 bits C...

Page 419: ... assert cycle and Tc2 the read data latch cycle Tr1 CKIO Address RD D31 D0 read D31 D0 write Tr2 Tc1 Tc2 Tpc Row Column DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer The DACK is in the high active setting For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 14 Basic DRAM Access Timing ...

Page 420: ...e can be inserted by means of the TPC bit in MCR giving from 1 to 7 cycles The number of cycles from assertion to assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR Also the number of cycles from assertion to the end of the access can be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2 Tr1 CKIO Address RD D31 D0 read D31 D0 write ...

Page 421: ...t in MCR The timing for burst access using fast page mode is shown in figure 13 16 If the access size exceeds the set bus width burst access is performed In a 32 byte transfer the first access comprises a longword that includes the data requiring access The remaining accesses are performed on 32 byte boundary data that includes the relevant data In burst transfer wraparound writing is performed fo...

Page 422: ...O mode bit EDOMODE in MCR enables either normal access burst access using fast page mode or EDO mode normal access burst access to be selected for DRAM When EDO mode is set BE must be set to 1 in MCR EDO mode normal access is shown in figure 13 17 and burst access in figure 13 18 CAS Negation Period The CAS negation period can be set to 1 or 2 by means of the TCAS bit in the MCR register Tr1 Tc1 T...

Page 423: ... bit RASD to 1 it is possible to select RAS down mode in which remains asserted after the end of an access When RAS down mode is used if the refresh cycle is longer than the maximum DRAM assert time the refresh cycle must be decreased to or below the maximum value of tRAS In RAS down mode in the event of an access to an address with a different row address an access to a different area a refresh r...

Page 424: ...Tc2 Tc2 Tc1 Tc2 CKIO Address RD D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory d8 d2 d1 d8 d2 d1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 1 DRAM Burst Bus Cycle RAS Down Mode Start Fast Page Mode RCD 0 AnW 0 ...

Page 425: ... RD D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory c1 c2 c8 d1 d1 d2 d8 d2 d8 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 2 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 0 AnW 0 ...

Page 426: ... Tc2 Tc2 Tr1 c1 c2 c8 Tc1 Tc1 Tce Tc2 CKIO Address RD D31 D0 read DACKn SA IO memory d8 d2 d1 Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 3 DRAM Burst Bus Cycle RAS Down Mode Start EDO Mode RCD 0 AnW 0 ...

Page 427: ...c1 c2 c8 Tc1 Tnop Tce CKIO Address RD D31 D0 read DACKn SA IO memory d8 d2 d1 End of RAS down mode Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 19 4 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 0 AnW 0 ...

Page 428: ...CKS2 CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and the pin goes high If the SH7751 Series external bus can be used CAS before RAS refreshing is performed At the same time RTCNT is cleared to zero and the count up is restarted Figure 13 20 shows the operation...

Page 429: ...a long refresh cycle time for example the HM51W4160AL L version has a refresh cycle of 1024 cycles 128 ms compared with 1024 cycles 16 ms for the normal version With these DRAMs however the same refresh cycle as for the normal version is requested only in the case of refreshing immediately following self refreshing To ensure efficient DRAM refreshing therefore processing is needed to generate an o...

Page 430: ...ontinue to be output can be controlled by the HIZCNT bit in BCR1 This enables the DRAM to be kept in the self refreshing state Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle execution of the refresh is deferred until the bus cycle is completed Refresh operations are deferred during multiple bus cycles generated because...

Page 431: ... requested that a wait time at least 100 s or 200 s during which no access can be performed be provided followed by at least the prescribed number usually 8 of dummy CAS before RAS refresh cycles As the bus state controller does not perform any special operations for a power on reset the necessary power on sequence must be carried out by the initialization program executed after a power on reset ...

Page 432: ... writes synchronous DRAM is accessed with an 8 burst length burst read write and therefore 32 bytes of data are read even in the case of a single read In the case of a single write 32 byte data transfer is performed but DQMn is not asserted in the case of an unnecessary data transfer For a description of the case where an 8 burst length setting is made see section 13 3 6 Burst ROM Interface For in...

Page 433: ...nous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2 AMX0 in MCR Table 13 15 shows the relationship between the address multiplex specification bits and the bits output at the address pins See Appendix E Synchronous DRAM Address Multiplexing Tables The address signals output at address pins A25 A18 A1 and A0 ...

Page 434: ... cycle Td1 to cycle Td8 The Tpc cycle is used to wait for completion of auto precharge based on the READA command inside the synchronous DRAM no new access command can be issued to the same bank during this cycle In the SH7751 Series the number of Tpc cycles is determined by the specification of bits TPC2 TPC0 in MCR and commands are not issued for the synchronous DRAM during this interval The exa...

Page 435: ... Bank Precharge sel Address RD D31 D0 read DQMn DACKn SA IO memory CKE H L c5 Td5 Td6 Td8 Td7 Tpc c1 c1 c2 c3 c4 c5 c6 Row Row Row c7 c8 H L Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 24 Basic Timing for Synchronous DRAM Burst Read ...

Page 436: ...1 Series as synchronous DRAM is set to burst read burst write mode read data output continues after the required data has been read To prevent data collisions after the required data is read in Td1 empty read cycles Td2 to Td4 are performed and the SH7751 Series waits for the end of the synchronous DRAM operation The signal is asserted only in Td1 There are 4 burst transfers in a read In cache thr...

Page 437: ...is issued In the write cycle the write data is output at the same time as the write command In the case of the write with auto precharge command precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command and therefore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc us...

Page 438: ...charge sel Address CSn DQMn RD WR RAS CASS D31 D0 write BS CKE DACKn SA IO memory c1 c2 c3 c4 c5 c6 c7 c8 Row Row Tc8 Trw1 Tpc Trw1 H L H L c5 Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 26 Basic Timing for Synchronous DRAM Burst Write ...

Page 439: ...mpletion of the write command and therefore no command can be issued for the synchronous DRAM until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for the same bank is postponed during this interval The number of Trw...

Page 440: ...rw H L c1 Trw1 CKIO Bank Precharge sel Address CSn DQMn RD WR RAS CASS D31 D0 write BS CKE DACKn SA IO memory c1 Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 27 Basic Timing for Synchronous DRAM Single Write ...

Page 441: ...address will be accessed within the period in which this value is maintained by program execution it is necessary to set auto refresh and set the refresh cycle to no more than the maximum value of tRAS In this way it is possible to observe the restrictions on the maximum active state time for each bank If auto refresh is not used measures must be taken in the program to ensure that the banks do no...

Page 442: ... c8 c5 Tc3 Tc4 Td1 Td2 Td4 Td5 Trw H L c1 H L c5 Td3 Td6 Td8 Td7 CKIO Bank Precharge sel Address DQMn RD D31 D0 read CKE DACKn SA IO memory Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 28 Burst Read Timing ...

Page 443: ...c6 c7 c8 Td2 Td3 Td4 Tc2 H L c1 H L c5 Td5 Td6 Td7 Td8 CKIO Bank Precharge sel Address DQMn RD D31 D0 read CKE DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 29 Burst Read Timing RAS Down Same Row Address ...

Page 444: ...d2 Tpc H L H L c1 c5 Tc4 Td1 Td3 Td4 Td5 Td6 Td7 Td8 CKIO Bank Precharge sel Address DQMn RD D31 D0 read CKE DACKn SA IO memory Row Row Row Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 30 Burst Read Timing RAS Down Different Row Addresses ...

Page 445: ...w H L H L c1 c5 Tc6 Tc7 Tc8 Trw1 Trw1 CKIO Bank Precharge sel Address DQMn RD D31 D0 read CKE c1 c2 c3 c4 c5 c6 c7 c8 Row Row Row DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 31 Burst Write Timing ...

Page 446: ...ory Note c8 c7 Normal write Single address DMA The Tnop cycle is inserted only for SA DMA The DACKn signal is output as indicated by the solid line In the case of a normal write the Tnop cycle is deleted and the DACKn signal is output as indicated by the dotted line For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 32 Burst Write Timing Same Row Address ...

Page 447: ...here CHCRn AL access level 0 for the DMAC Figure 13 33 Burst Write Timing Different Row Addresses Pipelined Access When the RASD bit is set to 1 in MCR pipelined access is performed between an access by the CPU and an access by the DMAC or in the case of consecutive accesses by the DMAC to provide faster access to synchronous DRAM As synchronous DRAM is internally divided into two or four banks af...

Page 448: ...s following a write access or a write access following a write access the PRE ACTV READ or WRIT command is issued during the data write cycle for the preceding access however in the case of different row addresses in the same bank a PRE command cannot be issued and so in this case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits in MCR after the end of the l...

Page 449: ...c1_A Tc1_B H L H L H L CKIO Bank Precharge sel Address DQMn RD D31 D0 read CKE a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 c1_A c5_A c1_B c5_B H L Figure 13 34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ...

Page 450: ...t time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and an auto refresh is performed At the same time RTCNT is cleared to zero and the count up is restarted Figure 13 36 shows the auto refresh cycle timing First an REF command is issued in the TRr cycle After the TRr cycle new command output cannot be performed for th...

Page 451: ... retention are performed correctly and auto refreshing is performed at the correct intervals When self refreshing is activated from the state in which auto refreshing is set or when exiting standby mode other than through a power on reset auto refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode...

Page 452: ... or write back and also between read and write cycles during execution of a TAS instruction and between read and write cycles when DMAC dual address transfer is executed If a refresh request occurs when the bus has been released by the bus arbiter refresh execution is deferred until the bus is acquired If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a ne...

Page 453: ... command or a mode register setting command is issued The timing for the precharge all banks command is shown in figure 13 38 1 and the timing for the mode register setting command in figure 13 38 2 Before mode register a 200 µs idle time depending on the memory manufacturer must be guaranteed after the power required for the synchronous DRAM is turned on If the reset signal pulse width is greater...

Page 454: ...ould be executed once only after power on reset and before synchronous DRAM access and no subsequent changes should be made CKIO Bank Precharge sel Address RD D31 D0 CKE TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High TMw5 Figure 13 38 1 Synchronous DRAM Mode Write Timing PALL ...

Page 455: ...e 13 39 is the timing chart for burst read operations For the example shown below we assume that two synchronous DRAMs of 512k 16 bits 2 banks are connected and are used with a 32 bit data width and a burst length of 8 Following the Tr cycle during which an ACTV command is output a READA command is issued during cycle Tc1 During the Td1 to Td8 cycles the read data are accepted on the rising edges ...

Page 456: ...d the Trw cycle which is for the issuing of NOP commands to the synchronous DRAM is inserted between the Tr and Tc cycles The number of cycles from cycle Tc1 on which the READA command is output until cycle Td1 in which the first part of the data to be read is received can be set by the bits A2W2 to A2W0 and A3W2 to A3W0 of WCR2 These independently select a number of cycles between 1 and 5 for are...

Page 457: ...be written is output along with the write command With a write command that includes an auto precharge precharging is of the relevant bank of the synchronous DRAM and takes place on completion of the write command so no new command that accesses the same bank can be issued until precharging has been completed For this reason the Trwl cycles are added as a period of waiting for precharging to start...

Page 458: ...2 A5BST0 or A6BST2 A6BST0 When 16 bit ROM is connected 4 8 or 16 can be set in the same way When 32 bit ROM is connected 4 or 8 can be set pin sampling is always performed when one or more wait states are set The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0 The timing in this case is shown in figure 13 42 In a burst R...

Page 459: ...ge 420 of 1064 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CKIO A25 A5 A4 A0 RD D31 D0 read DACKn SA IO memory Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 41 Burst ROM Basic Access Timing ...

Page 460: ...CKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 42 Burst ROM Wait Access Timing CKIO A25 A5 A4 A0 RD D31 D0 read DACKn SA IO memory TS1 TB2 TH1 TS1 TB1 TB2 TS1 T1 TH1 TB1 TH1 TS1 TB1 T2 TH1 TB2 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 43 Burst ROM Wait Access Timing ...

Page 461: ...ement Unit MMU for details of the setting method When the MMU is off the setting of bits SA2 to SA0 of PTEA is always used for access SA2 SA1 SA0 Description 0 0 0 Reserved Setting prohibited 1 Dynamic I O bus sizing 1 0 8 bit I O space 1 16 bit I O space 1 0 0 8 bit common memory 1 16 bit common memory 1 0 8 bit attribute memory 1 16 bit attribute memory When the MMU is on wait cycles in a bus ac...

Page 462: ... A5IW2 A5IW0 and A6IW2 A6IW0 in wait control register 1 WCR1 The inter cycle write cycles selected depend only on the area accessed area 5 or 6 when area 5 is accessed bits A5IW2 A5IW0 are selected and when area 6 is accessed bits A6IW2 A6IW0 are selected In 32 byte transfer a total of 32 bytes are transferred consecutively according to the set bus width The first access is performed on the data f...

Page 463: ...valid Upper read data Odd Don t care Write 8 Even Don t care 1 0 0 Invalid Write data Odd Don t care 1 0 1 Invalid Write data 16 Even Don t care First 1 0 0 Invalid Lower write data Even Don t care Second 1 0 1 Invalid Upper write data Odd Don t care 16 Read 8 Even Don t care 1 0 0 Invalid Read data Odd Don t care 0 1 1 Read data Invalid 16 Even Don t care 0 0 0 Upper read data Lower read data Odd...

Page 464: ...e data Odd 0 Read 8 Even 1 1 0 0 Invalid Read data Odd 1 First 0 1 1 Ignored Invalid Odd 1 Second 1 0 1 Invalid Read data 16 Even 1 First 0 0 0 Invalid Lower read data Even 1 Second 1 0 1 Invalid Upper read data Odd 1 Write 8 Even 1 1 0 0 Invalid Write data Odd 1 First 0 1 1 Invalid Write data Odd 1 Second 1 0 1 Invalid Write data 16 Even 1 First 0 0 0 Upper write data Lower write data Even 1 Seco...

Page 465: ...A0 D15 D0 CD1 CD2 A25 A0 D15 D0 CD1 CD2 A25 A0 SH7751 Series D15 D0 RD DIR D7 D0 D15 D8 DIR DIR DIR D7 D0 D15 D8 PC card memory I O PC card memory I O Card detection circuit Card detection circuit Figure 13 44 Example of PCMCIA Interface ...

Page 466: ...CMCIA memory card interface and figure 13 46 shows the wait timing for the PCMCIA memory card interface CKIO Tpcm1 Tpcm2 A25 A0 RD D15 D0 read D15 D0 write read write DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 45 Basic Timing for PCMCIA Memory Card Interface ...

Page 467: ...pcm0 A25 A0 RD REG read D15 D0 read D15 D0 write write DACKn DA Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 46 Wait Timing for PCMCIA Memory Card Interface ...

Page 468: ... 2 Access by CS6 wait controller Figure 13 47 PCMCIA Space Allocation I O Card Interface Timing Figures 13 48 and 13 49 show the timing for the PCMCIA I O card interface When an I O card interface access is made to a PCMCIA card dynamic sizing of the I O bus width is possible using the pin When a 16 bit bus width is set if the signal is high during a word size I O bus cycle the I O port is recogni...

Page 469: ...e 430 of 1064 CKIO Tpci1 Tpci2 A25 A0 RD read D15 D0 read write D15 D0 write DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 48 Basic Timing for PCMCIA I O Card Interface ...

Page 470: ...O A25 A0 RD read write DACKn DA D15 D0 read D15 D0 write Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 49 Wait Timing for PCMCIA I O Card Interface ...

Page 471: ...pci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CKIO A25 A1 A0 RD read write D15 D0 write D15 D0 read DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 50 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 472: ...cur in the case of minimum pitch access The signal is asserted at the rise of Tm1 and negated when the last data transfer cycle starts in the data phase Therefore an external device for the MPX interface must hold the address information and access size output in the address phase within itself and peripheral function data input output for the data phase For details of access sizes and data alignm...

Page 473: ...nection The MPX interface timing is shown below When the MPX interface is used for areas 1 to 6 a bus size of 32 bit should be specified in BCR2 For wait control waits specified by WCR2 and wait insertion by means of the pin can be used In a read one wait cycle is automatically inserted after address output even if WCR2 is cleared to 0 ...

Page 474: ...page 435 of 1064 Tm1 CKIO A RD D31 D0 Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 52 MPX Interface Timing 1 Single Read Cycle AnW 0 No External Wait ...

Page 475: ...436 of 1064 Tm1 CKIO A RD D31 D0 Tmd1w Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 53 MPX Interface Timing 2 Single Read AnW 0 One External Wait Inserted ...

Page 476: ...02 page 437 of 1064 Tm1 CKIO A RD D31 D0 Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 54 MPX Interface Timing 3 Single Write Cycle AnW 0 No External Wait ...

Page 477: ...438 of 1064 Tm1 CKIO A RD D31 D0 Tmd1w Tmd1w Tmd1 DACKn DA D0 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 55 MPX Interface Timing 4 Single Write AnW 1 One External Wait Inserted ...

Page 478: ...D D31 D0 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D2 D3 D4 D6 D7 D8 D5 A D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 56 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait ...

Page 479: ...O A RD D31 D0 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D7 D8 D2 D3 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 57 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control ...

Page 480: ... A RD D31 D0 Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D1 D2 D3 D4 D5 D6 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 58 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait ...

Page 481: ...m1 CKIO A RD D31 D0 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D1 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 59 MPX Interface Timing 8 Burst Write Cycle AnW 1 External Wait Control ...

Page 482: ...A RD D31 D0 Tmd1w Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 60 MPX Interface Timing 1 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 483: ... D0 Tmd1w Tmd1w Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 61 MPX Interface Timing 2 Burst Read Cycle AnW 0 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 484: ...IO A RD D31 D0 Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 62 MPX Interface Timing 3 Burst Write Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 485: ... D0 Tmd1w Tmd1w Tmd1 Tmd2 DACKn DA D0 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 63 MPX Interface Timing 4 Burst Write Cycle AnW 1 One External Wait Inserted Bus Width 32 Bits Transfer Data Size 64 Bits ...

Page 486: ...2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D2 D3 D4 D6 D7 D8 D5 A D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 64 MPX Interface Timing 5 Burst Read Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 487: ...1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D7 D8 D2 D3 D1 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 65 MPX Interface Timing 6 Burst Read Cycle AnW 0 External Wait Control Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 488: ...Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 DACKn DA D1 D2 D3 D4 D5 D6 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 66 MPX Interface Timing 7 Burst Write Cycle AnW 0 No External Wait Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 489: ...1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 DACKn DA D1 D7 D8 Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 67 MPX Interface Timing 8 Burst Write Cycle AnW 1 External Wait Control Bus Width 32 Bits Transfer Data Size 32 Bytes ...

Page 490: ...sserted Assertion is synchronized with the fall of the CKIO clock as for the signal while negation is synchronized with the rise of the CKIO clock using the same timing as the signal 32 byte transfer is performed consecutively for a total of 32 bytes according to the set bus width The first access is performed on the data for which there was an access request The remaining accesses are performed i...

Page 491: ...2 page 452 of 1064 T1 T2 CKIO A25 A0 RD D31 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 69 Byte Control SRAM Basic Read Cycle No Wait ...

Page 492: ...3 of 1064 T1 Tw T2 CKIO A25 A0 RD D31 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 70 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle ...

Page 493: ...4 T1 Tw Twe T2 CKIO A25 A0 RD D31 D0 read DACKn SA IO memory DACKn DA Note For DACKn an example is shown where CHCRn AL access level 0 for the DMAC Figure 13 71 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait ...

Page 494: ...ertion is not performed If there is originally space between accesses according to the setting of bits AnIW2 AnIW0 n 0 to 6 in WCR1 the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles When bus arbitration is performed the bus is released after waits are inserted between cycles In single address mode DMA transfer when data transfer is performed...

Page 495: ... 1064 T1 A25 A0 RD D31 D0 T2 Twait T1 T2 Twait T1 T2 Area m space read Area m inter access wait specification Area n inter access wait specification Area n space read Area n space write Figure 13 72 Waits between Access Cycles ...

Page 496: ...ests Instead of a slave mode chip In the following description an external device that issues bus requests is also referred to as a slave The SH7751 Series has three internal bus masters the CPU DMAC and PCIC When synchronous DRAM or DRAM is connected and refresh control is performed refresh requests constitute a fourth bus master In addition to these are bus requests from external devices in mast...

Page 497: ...s a cache fill or write back and also between read and write cycles during execution of a TAS instruction and between read and write cycles when DMAC dual address transfer is executed Refresh operations are also deferred in the bus released state If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued before a refresh cycle occurs or before the bus is released by b...

Page 498: ...25 A0 RD D31 D0 read HiZ HiZ HiZ HiZ HiZ HiZ Negated within 2 cycles Asserted for at least 2 cycles Slave mode device access Negated within 2 cycles HiZ HiZ HiZ HiZ HiZ Master access Master access Slave access Note For the SH7751 refer to the Usage Note in section 13 3 15 Figure 13 73 Arbitration Sequence ...

Page 499: ...us is released after precharging is completed The actual bus release sequence is as follows First the bus use permission signal is asserted in synchronization with the rising edge of the clock The address bus and data bus go to the high impedance state in synchronization after this assertion At the same time the bus control signals RD and go to the high impedance state These bus control signals ar...

Page 500: ...he access cycle is synchronized with the rising edge of the clock When the bus cycle ends the signal is negated and the release of the bus is reported to the master On the next rising edge of the clock the control signals are set to high impedance In order for the slave mode processor to begin access the signal must be asserted for at least two cycles For a slave access cycle in DRAM or synchronou...

Page 501: ...ystems performing bus arbitration make the transition to standby mode or deep sleep mode only after setting the bus privilege release enable bit BCR1 BREQEN to 0 for the processor in master mode If the bus privilege release enable bit remains set to 1 operation cannot be guaranteed when the transition is made to standby mode or deep sleep mode Simultaneous Use of Refresh and Bus Arbitration With t...

Page 502: ...hysical address space Choice of 8 bit 16 bit 32 bit 64 bit or 32 byte transfer data length Maximum of 16 M 16 777 216 transfers Choice of single or dual address mode Single address mode Either the transfer source or the transfer destination external device is accessed by a DACK signal while the other is accessed by address One data transfer is completed in one bus cycle Dual address mode Both the ...

Page 503: ...is generated automatically within the DMAC Channel functions Transfer modes that can be set are different for each channel 1 Normal DMA mode Channel 0 Single or dual address mode External requests are accepted Channel 1 Single or dual address mode External requests are accepted Channel 2 Dual address mode only Channel 3 Dual address mode only Channel 4 SH7751R only Dual address mode only Channel 5...

Page 504: ...between the external device and the DMAC Request queue clear for each channel SH7751R only Request queues can be cleared on a channel by channel basis in either of the following two ways Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR SZ 110 DTR ID 00 DTR MD 11 and DTR COUNT 7 4 1 8 Using software to clear the request queue The req...

Page 505: ...egister CHCRn DMAC channel control register n 0 to 3 On chip peripheral module Peripheral bus Internal bus DMAC module Count control Register control Activation control Request priority control Bus interface 32B data buffer Bus state controller CH0 CH1 CH2 CH3 Request controller DTR command buffer DDT module SAR0 DAR0 DMATCR0 CHCR0 only External bus ID 1 0 D 31 0 DDTMODE DBREQ BAVL dreq0 3 4 48 bi...

Page 506: ...ification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request Input DMA transfer request input from external device to channel 1 acceptance confirmation DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external device Notification to...

Page 507: ...ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as output ID 1 DRAK1 ID 0 DACK1 14 1 4 Register Configuration SH7751 Table 14 3 summarizes the DMAC registers The DMAC has a total of 17 registers four registers are allocated to each channel and an additional control register is shared by all four channels Table 14 3 DMAC Registers Chan nel Name Abbre viation...

Page 508: ... 32 DMA transfer count register 2 DMATCR2 R W Undefined H FFA00028 H 1FA00028 32 DMA channel control register 2 CHCR2 R W H 00000000 H FFA0002C H 1FA0002C 32 3 DMA source address register 3 SAR3 R W Undefined H FFA00030 H 1FA00030 32 DMA destination address register 3 DAR3 R W Undefined H FFA00034 H 1FA00034 32 DMA transfer count register 3 DMATCR3 R W Undefined H FFA00038 H 1FA00038 32 DMA channe...

Page 509: ...er feedback function and during a DMA transfer they indicate the next source address In single address mode the SAR value is ignored when a device with DACK has been specified as the transfer source Specify a 16 bit 32 bit 64 bit or 32 byte boundary address when performing a 16 bit 32 bit 64 bit or 32 byte data transfer respectively If a different address is specified an address error will be dete...

Page 510: ... a different address is specified an address error will be detected and the DMAC will halt The initial value of these registers after a power on or manual reset is undefined They retain their values in standby mode sleep mode and deep sleep mode Notes 1 When a 16 bit 32 bit 64 bit or 32 byte boundary address is specified take care with the setting of bit 0 bits 1 0 bits 2 0 or bits 4 0 respectivel...

Page 511: ... DMATCR0 DMATCR3 are 32 bit readable writable registers that specify the transfer count for the corresponding channel byte count word count longword count quadword count or 32 byte count Specifying H 000001 gives a transfer count of 1 while H 000000 gives the maximum setting 16 777 216 16M transfers During DMAC operation the remaining number of transfers is shown Bits 31 24 of these registers are ...

Page 512: ...nt depending on the channel DMA channel control registers 0 3 CHCR0 CHCR3 are 32 bit readable writable registers that specify the operating mode transfer method etc for each channel Bits 31 28 and 27 24 indicate the source address and destination address respectively these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA ...

Page 513: ... 1 16 bit attribute memory space Bit 28 Source Address Wait Control Select STC Specifies CS5 or CS6 space wait control for PCMCIA interface area access Bit 28 STC Description 0 CS5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PCW0 A5TED2 A5TED0 and A5TEH2 A5TEH0 in the PCMCIA control register PCR are selected 1 CS6 space wait...

Page 514: ...or CS6 space wait cycle control for PCMCIA interface area access This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control Bit 24 DTC Description 0 CS5 space wait cycle selection Initial value Settings of bits A5W2 A5W0 in wait control register 2 WCR2 and bits A5PCW1 A5PCW0 A5TED2 A5TED0 and A5TEH2 A5TEH0 in the PCMCIA control register PCR are selected 1 C...

Page 515: ... bit is valid only in CHCR0 and CHCR1 It is invalid in DDT mode Bit 18 RL Description 0 DRAK is an active high output Initial value 1 DRAK is an active low output Bit 17 Acknowledge Mode AM In dual address mode selects whether DACK is output in the data read cycle or write cycle In single address mode DACK is always output regardless of the setting of this bit In normal DMA mode this bit is valid ...

Page 516: ... 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer 8 in 64 bit transfer 32 in 32 byte burst transfer 1 Setting prohibited Bits 13 and 12 Source Address Mode 1 and 0 SM1 SM0 These bits specify incrementing decrementing of the DMA transfer source address The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode Bit 13...

Page 517: ... 1 0 0 0 SCI transmit data empty interrupt transfer request external address space SCTDR1 2 1 SCI receive data full interrupt transfer request SCRDR1 external address space 2 1 0 SCIF transmit data empty interrupt transfer request external address space SCFTDR2 2 1 SCIF receive data full interrupt transfer request SCFRDR2 external address space 2 1 0 0 TMU channel 2 input capture interrupt externa...

Page 518: ...TS1 Bit 4 TS0 Description 0 0 0 Quadword size 64 bit specification Initial value 1 Byte size 8 bit specification 1 0 Word size 16 bit specification 1 Longword size 32 bit specification 1 0 0 32 byte block transfer specification Bit 3 Reserved This bit is always read as 0 and should only be written with 0 Bit 2 Interrupt Enable IE When this bit is set to 1 an interrupt request DMTE is generated aft...

Page 519: ... When 0 is written to TE after reading TE 1 In a power on or manual reset and in standby mode 1 Number of transfers specified in DMATCR completed Bit 0 DMAC Enable DE Enables operation of the corresponding channel Bit 0 DE Description 0 Operation of corresponding channel is disabled Initial value 1 Operation of corresponding channel is enabled When auto request is specified with RS3 RS0 transfer i...

Page 520: ...h 0 after being read as 1 to clear the flags DMAOR is a 32 bit readable writable register that specifies the DMAC transfer mode DMAOR is initialized to H 00000000 by a power on or manual reset They retain their values in standby mode and deep sleep mode Bits 31 to 16 Reserved These bits are always read as 0 and should only be written with 0 Bit 15 On Demand Data Transfer DDT Specifies on demand da...

Page 521: ... and an interrupt request DMAE is generated The CPU cannot write 1 to AE This bit can only be cleared by writing 0 after reading 1 Bit 2 AE Description 0 No address error DMA transfer enabled Initial value Clearing condition When 0 is written to AE after reading AE 1 1 Address error DMA transfer disabled Setting condition When an address error is caused by the DMAC Bit 1 NMI Flag NMIF Indicates th...

Page 522: ...e After the desired transfer conditions have been set in the DMA source address register SAR DMA destination address register DAR DMA transfer count register DMATCR DMA channel control register CHCR and DMA operation register DMAOR the DMAC transfers data according to the following procedure 1 The DMAC checks to see if transfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 2 When a transfer request is is...

Page 523: ... of 1064 Note If a transfer request is issued while transfer is disabled the transfer enable wait state transfer suspended state is entered Transfer is started when subsequently enabled by setting DE 1 DME 1 TE 0 NMIF 0 AE 0 ...

Page 524: ... AE 1 or DE 0 or DME 0 Bus mode transfer request mode detection method Transfer suspended 4 2 3 No No Yes Yes Yes No No No Yes Yes No Yes Notes 1 In auto request mode transfer begins when the NMIF AE and TE bits are all 0 and the DE and DME bits are set to 1 2 level detection external request in burst mode or cycle steal mode 3 edge detection external request in burst mode or auto request mode in ...

Page 525: ...request signal internally When the DE bit in CHCR0 CHCR3 and the DME bit in the DMA operation register DMAOR are set to 1 the transfer begins so long as the TE bit in CHCR0 CHCR3 and the NMIF and AE bits in DMAOR are all 0 External Request Mode In this mode a transfer is performed in response to a transfer request signal from an external device One of the modes shown in table 14 4 should be chosen...

Page 526: ...is started after it is enabled DME 1 DE 1 DMAOR NMIF 0 DMAOR AE 0 CHCR TE 0 2 When DMA transfer is enabled DME 1 DE 1 DMAOR NMIF 0 DMAOR AE 0 CHCR TE 0 if an external request is input DMA transfer is started 3 An external request will be ignored if input when CHCR TE 1 DMAOR NMIF 1 DMAOR AE 1 during a power on reset or manual reset in deep sleep mode standby mode or while the DMAC is in the module...

Page 527: ...ial communication interfaces SCI SCIF If DMA transfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 transfer starts when a transfer request signal is input The source of the transfer request does not have to be the data transfer source or destination However when the transfer request is set to RXI transfer request by SCI SCIF receive data full interrupt the transfer source must be the SCI SCIF s receive ...

Page 528: ...eal mode TMU Timer unit SCI Serial communication interface SCIF Serial communication interface with FIFO Notes External memory or memory mapped external device 1 SCI SCIF burst transfer setting is prohibited 2 If input capture interrupt acceptance is set for multiple channels and DE 1 for each channel processing will be executed on the highest priority channel in response to a single input capture...

Page 529: ...g priority orders are available in fixed mode CH0 CH1 CH2 CH3 CH0 CH2 CH3 CH1 CH2 CH0 CH1 CH3 The priority order is selected with bits PR1 and PR0 in DMAOR Round Robin Mode In round robin mode each time the transfer of one transfer unit byte word longword quadword or 32 bytes ends on a given channel that channel is assigned the lowest priority level This is illustrated in figure 14 3 The order of ...

Page 530: ...is a transfer request for channel 1 only immediately afterward channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down Transfer on channel 3 Initial priority order Priority order after transfer No change in priority order CH0 CH1 CH2 CH3 CH3 CH0 CH1 CH2 CH2 CH3 CH0 CH1 CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH2 CH3 CH0 CH1 When channel 1 is given the ...

Page 531: ... transfer standby 6 At the end of the channel 1 transfer channel 1 shifts to the lowest priority level 7 The channel 3 transfer is started 8 At the end of the channel 3 transfer the channel 3 and channel 2 priority levels are lowered giving channel 3 the lowest priority 3 1 3 3 Transfer request Channel waiting DMAC operation Channel priority order 1 Issued for channels 0 and 3 3 Issued for channel...

Page 532: ...he bus mode which can be either burst mode or cycle steal mode Table 14 6 Supported DMA Transfers Transfer Destination Transfer Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Single address mode Single address mode Not available External memory Single address mode Dual address mode Dual address mode D...

Page 533: ... with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle DMAC DACK External memory External device with DACK SH7751 Series External address bus Data flow External data bus Figure 14 5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode 1 transfer between an external device with DACK...

Page 534: ...e Address output to external memory space Data output from external memory space RD signal to external memory space DACK signal to external device with DACK a From external device with DACK to external memory space b From external memory space to external device with DACK CKIO A28 A0 CSn D63 D0 DACK WE CKIO A28 A0 CSn D63 D0 RD DACK Figure 14 6 DMA Transfer Timing in Single Address Mode ...

Page 535: ... such as that shown in figure 14 7 data is read from external memory into the BSC s data buffer in the read cycle then written to the other external memory in the write cycle Figure 14 8 shows the timing for this operation Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR...

Page 536: ...C releases the bus to the CPU at the end of each transfer unit 8 bit 16 bit 32 bit 64 bit or 32 byte transfer When the next transfer request is issued the DMAC reacquires the bus from the CPU and carries out another transfer unit transfer At the end of this transfer the bus is again given to the CPU This is repeated until the transfer end condition is satisfied Cycle steal mode can be used with al...

Page 537: ...ister 1 BCRL DMABST With low level detection in external request mode however when is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted even if the transfer end condition has not been satisfied Figure 14 10 shows an example of DMA transfer timing in burst mode The transfer conditions in this example are single address mode an...

Page 538: ... 0 1 2 3 5 6 Memory mapped external device and on chip peripheral module Internal 2 B C 3 8 16 32 64 4 0 1 2 3 5 6 32B 32 byte burst transfer B Burst C Cycle steal External External request Internal Auto request on chip peripheral module request Notes 1 External request auto request or on chip peripheral module request TMU input capture interrupt request possible In the case of an on chip peripher...

Page 539: ...e with DACK Single 0 1 2 External device with DACK Synchronous DRAM Single 0 1 3 SRAM type DRAM External device with DACK Single 0 1 4 External device with DACK SRAM type DRAM Single 0 1 5 Synchronous DRAM SRAM type MPX PCMCIA Dual 0 1 6 SRAM type MPX PCMCIA Synchronous DRAM Dual 0 1 7 SRAM type DRAM PCMCIA MPX SRAM type MPX PCMCIA Dual 0 1 8 SRAM type MPX PCMCIA SRAM type DRAM PCMCIA MPX Dual 0 1...

Page 540: ...byte control SRAM or burst ROM setting Notes 1 The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM 2 When performing dual address mode transfer make the DACK output setting for the SRAM byte control SRAM burst ROM PCMCIA or MPX interface Bus Mode and Channel Priority Order When for example channel 1 is transferring data in burst mode and a tr...

Page 541: ...he bus cycle when the DMAC is the bus master is controlled by the bus state controller BSC just as it is when the CPU is the bus master See section 13 Bus State Controller BSC for details DREQ Pin Sampling Timing In external request mode the pin is sampled at the rising edge of CKIO clock pulses When input is detected a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles a...

Page 542: ...f the first DMAC transfer bus cycle Figure 14 19 shows the case of cycle steal mode single address mode and edge detection In this case transfer is started at the earliest five CKIO cycles after the first sampling operation The second sampling begins one cycle after the first assertion of DRAK In single address mode the DACK signal is output every DMAC transfer cycle 2 Burst Mode Dual Address Mode...

Page 543: ...ignal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR 5 Burst Mode Single Address Mode Edge Detection In burst mode using single address mode and edge detection sampling is performed only in the first cycle For example in the case shown in figure 14 21 DMAC transfer begins at the earliest five cycles after the firs...

Page 544: ...urce address Destination address Bus locked Destination address CPU CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 12 Dual Address Mode Cycle Steal Mode External Bus External Bus Level Detection DACK Read Cycle ...

Page 545: ...locked Source address Source address Destination address Bus locked Destination address CPU DMAC CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 13 Dual Address Mode Cycle Steal Mode External Bus External Bus Edge Detection DACK Read Cycle ...

Page 546: ... Source address Destination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 14 Dual Address Mode Burst Mode External Bus External Bus Level Detection DACK Read Cycle ...

Page 547: ...Destination address Bus locked Destination address CPU DMAC 2 CPU DMAC 1 TE bit transfer end DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 15 Dual Address Mode Burst Mode External Bus External Bus Edge Detection DACK Read Cycle ...

Page 548: ...ource address On chip peripheral data bus Read Read Read D 31 0 Write Write Write Source address Source address A 25 0 Destination address Destination address Destination address CPU CPU DMAC CPU DMAC CPU DMAC Figure 14 16 Dual Address Mode Cycle Steal Mode On Chip SCI Level Detection External Bus ...

Page 549: ...ite Write Write Source address Source address A 25 0 Destination address Destination address Destination address CPU DMAC CPU DMAC CPU DMAC T1 T2 T1 T2 T1 T2 On chip peripheral address bus On chip peripheral data bus Figure 14 17 Dual Address Mode Cycle Steal Mode External Bus On Chip SCI Level Detection ...

Page 550: ...e address 2nd acceptance Source address 3rd acceptance Source address 4th acceptance Source address DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 18 Single Address Mode Cycle Steal Mode External Bus External Bus Level Detection ...

Page 551: ...ce 2nd acceptance Source address Source address CPU CPU DMAC CPU DMAC CPU DMAC DRAK0 DREQ1 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 19 Single Address Mode Cycle Steal Mode External Bus External Bus Edge Detection ...

Page 552: ...ance 2nd acceptance Source address Source address Source address CPU DMAC 4 DMAC 2 DMAC 3 CPU DMAC 1 DREQ sampling and determination of channel priority DRAK0 DREQ1 DREQ0 level detection DACK0 Bus cycle A 25 0 CKIO D 31 0 Figure 14 20 Single Address Mode Burst Mode External Bus External Bus Level Detection ...

Page 553: ... acceptance Source address Source address Source address CPU DMAC 2 DMAC 4 DMAC 3 CPU DMAC 1 DRAK0 DREQ0 edge detection DACK0 Bus cycle A 25 0 CKIO D 31 0 DREQ sampling and determination of channel priority Figure 14 21 Single Address Mode Burst Mode External Bus External Bus Edge Detection ...

Page 554: ...es before start of bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle 2nd acceptance 3rd acceptance DMAC 1 DMAC 2 DMAC 3 Destination address Destination address Destination address D1 D6 D8 D1 D6 D7 D8 D7 D7 Figure 14 22 Single Address Mode Burst Mode External Bus External Bus Level Detection 32 Byte Block Transfer Bus Width 32 Bits SDRAM Row Hit Writ...

Page 555: ...tivates the DMAC but the timing of stop request DE 0 in CHCR DME 0 in DMAOR sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14 3 5 Therefore a transfer request is regarded as having been issued until a stop request is detected and the corresponding processing is executed before the DMAC stops 3 Burst Mode Level Detection External Request The...

Page 556: ...ously when either of the following conditions is satisfied The address error bit AE or NMI flag NMIF in the DMA operation register DMAOR is set The DMA master enable bit DME in DMAOR is cleared to 0 1 End of transfer when AE 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error DMA transfer is suspended on all channels in accordance with the conditions in 1 2 3 and 4 in section 14 ...

Page 557: ...tance of external requests is suspended while NMIF is set to 1 so a DMA transfer request must be reissued when resuming transfer Acceptance of internal requests is also suspended so when resuming transfer the DMA transfer request enable bit for the relevant on chip peripheral module must be cleared to 0 before the new setting is made 3 End of transfer when DME 0 in DMAOR If the DME bit in DMAOR is...

Page 558: ... Transfer between External Memory and an External Device with DACK and Corresponding Register Settings Transfer Conditions Register Set Value Transfer source external memory SAR1 H 0C000000 Transfer source external device with DACK DAR1 Accessed by DACK Number of transfers 32 DMATCR1 H 00000020 Transfer source address decremented CHCR1 H 000022A5 Transfer destination address setting invalid Transf...

Page 559: ...ta buffer bavl ID 1 0 ddtmode Data buffer Address bus ddtmode tdack id 1 0 Data bus Request controller FIFO or memory Figure 14 23 On Demand Transfer Mode Block Diagram After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU a transfer request is output from an external device using the DTR ID 1 0 and DTR MD 1 0 signals handshake protocol using the data bus A tra...

Page 560: ...andshake protocol using the data bus valid for channel 0 only This mode is only valid for channel 0 After the initial settings have been made in the DMAC channel 0 control register the DDT module asserts a data transfer request for the DMAC by setting the DTR command ID 00 MD 00 and SZ 101 110 and driving the DTR command 4 Handshake protocol without use of the data bus The DDT module includes a fu...

Page 561: ...ng When is accepted the BSC asserts Data bus D31 D0 release signal Assertion of means that the data bus will be released two cycles later Transfer request signal Assertion of has the following different meanings In normal data transfer mode except channel 0 is asserted and at the same time the DTR format is output two cycles after is asserted In the case of the handshake protocol without use of th...

Page 562: ...e data transfer request format DTR format consists of 32 bits In the case of normal data transfer mode channel 0 except channel 0 and the handshake protocol using the data bus channel number and transfer request mode are specified Connection is made to D31 through D0 Bits 31 to 29 Transmit Size SZ2 SZ0 000 Handshake protocol data bus used 001 Setting prohibited 010 Setting prohibited 011 Setting p...

Page 563: ...the DTR format Use the MOV instruction to make settings in the DMAC s SAR0 DAR0 CHCR0 and DMATCR0 registers Either single address mode or dual address mode can be used as the transfer mode Select one of the following settings CHCR0 RS3 RS0 0000 0010 0011 Operation is not guaranteed if the DTR format data settings are DTR ID 00 DTR MD 00 and DTR SZ 101 110 Usable SZ ID and MD Combination in DDT Mod...

Page 564: ... 10 or 11 after making DMAC control register settings in the same way as in normal DMA mode Each of channels 1 to 3 has a request queue that can accept up to four transfer requests When a request queue is full the fifth and subsequent transfer requests will be ignored and so transfer requests must not be output When CHCR TE 1 when a transfer request remains in the request queue and a transfer is c...

Page 565: ...tCSD Row Row Row tAD c1 H L tRASD tDQMD tCASD2 tCASD2 tRDS tBSD tBSD c1 c2 c4 c3 tDQMD tRDH DMAC Channel tIDD tTDAD tTDAD tIDD tTRS tTRH tBAVD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tDTRS tDTRH tDBQH tBAVD tRASD Figure 14 26 Single Address Mode Synchronous DRAM External Device Longword Transfer SDRAM Auto Precharge Read Bus Cycle Burst RCD 1 CAS latency 3 TPC 3 ...

Page 566: ...WDD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tBSD tWDD tRWD tCSD Row Row tRASD Row tAD H L c1 tAD tRASD tCASD2 tCASD2 tRWD tDQMD c4 c3 c2 tDTRS tDTRH tDBQS tDBQH tBAVD tBAVD tTRS tTRH tTDAD DMAC Channel tIDD tIDD tTDAD Figure 14 27 Single Address Mode External Device Synchronous DRAM Longword Transfer SDRAM Auto Precharge Write Bus Cycle Burst RCD 1 TRWL 2 TPC 1 ...

Page 567: ...1 ID0 D31 D0 READ RD tAD tCSD tAD tCSD Row Row Row tAD c1 H L tRASD tDQMD tCASD2 tCASD2 tRDS tBSD tBSD c1 c2 c4 c3 tDQMD tRDH DMAC Channel tTDAD tTRS tTRH tBAVD 2CKIO cycles tDTRS 18ns 100MHz DTR 1CKIO cycle 10ns 100MHz tDTRS tDTRH tDBQH tBAVD tRASD tTDAD DMAC Channel Figure 14 28 Dual Address Mode Synchronous DRAM SRAM Longword Transfer ...

Page 568: ...ngle Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer RA CA WT BA D0 D1 D2 D3 D4 D5 DTR CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ Figure 14 30 Single Address Mode Burst Mode External Device External Bus 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 569: ...064 RA CA CA CA D1 D0 DTR BA RD RD RD 00 00 CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ DQMn Figure 14 31 Single Address Mode Burst Mode External Bus External Device 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 570: ...1 of 1064 RA CA CA D1 D0 DTR BA WT WT CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ DQMn Figure 14 32 Single Address Mode Burst Mode External Device External Bus 32 Bit Transfer Channel 0 On Demand Data Transfer ...

Page 571: ...64 CA CA D0 D1 DTR MD 00 D0 D1 D2 D3 WT WT DTR MD 00 Start of data transfer Next transfer request CKIO ID1 ID0 TDACK D31 D0 A25 A0 TR BAVL DBREQ CMD Figure 14 33 Handshake Protocol Using Data Bus Channel 0 On Demand Data Transfer ...

Page 572: ... CA CA D0 D1 D2 D3 D0 D1 D2 D3 WT WT MD 00 Start of data transfer Next transfer request CKIO ID1 ID0 TDACK DTR D31 D0 A25 A0 TR BAVL DBREQ CMD Figure 14 34 Handshake Protocol without Use of Data Bus Channel 0 On Demand Data Transfer ...

Page 573: ... RAS CAS WE D0 RA CA D1 D2 D3 BA RD Figure 14 35 Read from Synchronous DRAM Precharge Bank CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA RD Transfer requests can be accepted Figure 14 36 Read from Synchronous DRAM Non Precharge Bank Row Miss ...

Page 574: ... CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE CA RD D0 D1 D2 D3 Figure 14 37 Read from Synchronous DRAM Row Hit CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE RA CA BA WT D0 D1 D2 D3 Figure 14 38 Write to Synchronous DRAM Precharge Bank ...

Page 575: ...0 D31 D0 RAS CAS WE RA CA D0 D1 D2 D3 PCH BA WT Transfer requests can be accepted Figure 14 39 Write to Synchronous DRAM Non Precharge Bank Row Miss CKIO DBREQ BAVL TR A25 A0 D31 D0 RAS CAS WE D0 CA D1 D2 D3 WT Figure 14 40 Write to Synchronous DRAM Row Hit ...

Page 576: ... of 1064 00 D0 D1 D2 RA CA RD BA DTR CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ Figure 14 41 Single Address Mode Burst Mode External Bus External Device 32 Byte Block Transfer Channel 0 On Demand Data Transfer ...

Page 577: ...A mode 1 On demand data transfer mode Figure 14 42 DDT Mode Setting DTR CA CA D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT WT CKIO ID1 ID0 TDACK CMD D31 D0 A25 A0 TR BAVL DBREQ Start of data transfer No DMA request sampling Figure 14 43 Single Address Mode Burst Mode Edge Detection External Device External Bus Data Transfer ...

Page 578: ...AVL DBREQ Figure 14 44 Single Address Mode Burst Mode Level Detection External Bus External Device Data Transfer CA CA CA RD RD RD DTR D0 D3 D2 CKIO ID1 ID0 TDACK DQMn D31 D0 A25 A0 TR BAVL DBREQ CMD Idle cycle Idle cycle Idle cycle Figure 14 45 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Bus External Device Data Transfer ...

Page 579: ... WT DTR D0 D3 D1 CKIO ID1 ID0 TDACK DQMn D31 D0 A25 A0 TR BAVL DBREQ CMD Idle cycle Idle cycle Idle cycle WT WT Figure 14 46 Single Address Mode Burst Mode Edge Detection Byte Word Longword Quadword External Device External Bus Data Transfer ...

Page 580: ... DTR ID 1 2 or 3 RA CA BA RD D0 D1 D2 D3 CKIO ID1 ID0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ 01 or 10 or 11 Figure 14 47 Single Address Mode Burst Mode 32 Byte Block Transfer DMA Transfer Request to Channels 1 3 Using Data Bus ...

Page 581: ...0 TDACK RAS CAS WE D31 D0 A25 A0 TR BAVL DBREQ No DTR cycle so requests can be made at any time Figure 14 48 Single Address Mode Burst Mode 32 Byte Block Transfer External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 without Using Data Bus ...

Page 582: ...WE D0 D1 D2 D3 D0 D1 D2 3rd 4th 1st 2nd 5th Four requests can be queued Handshaking is necessary to send additional requests No more requests Must be ignored no request transmitted Figure 14 49 Single Address Mode Burst Mode External Bus External Device Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 583: ...CAS WE D0 D1 D2 D3 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted D0 D1 D2 D3 WT Four requests can be queued 1st 2nd Figure 14 50 Single Address Mode Burst Mode External Device External Bus Data Transfer Direct Data Transfer Request to Channel 2 ...

Page 584: ...0 D1 D2 D3 D0 D1 D2 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted Four requests can be queued 1st 2nd Figure 14 51 Single Address Mode Burst Mode External Bus External Device Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 ...

Page 585: ... D3 3rd 4th 5th Handshaking is necessary to send additional requests Must be ignored no request transmitted D0 D1 D2 D3 WT Four requests can be queued 1st 2nd Figure 14 52 Single Address Mode Burst Mode External Device External Bus Data Transfer Active Bank Address Direct Data Transfer Request to Channel 2 ...

Page 586: ... transfer request the TE flag must be cleared by writing CHCR0 TE 0 after reading CHCR0 TE 1 4 Handshake protocol without use of the data bus a With the handshake protocol without use of the data bus a DMA transfer request can be input to the DMAC again for the channel for which transfer was requested immediately before by asserting only b When using the handshake protocol without use of the data ...

Page 587: ...ution set CHCR0 DE 1 with an MOV instruction 9 Request queue clearance a When settings of DTR ID 00 DTR MD 10 and SZ 110 are accepted by the DDT in normal data transfer mode DDT channel 0 requests and channel 1 to 3 request queues are all cleared All external requests held on the DMAC side are also cleared b In case 3 c the DMAC freeze state can be cleared c When settings of DMAOR DDT 1 DTR ID 00 ...

Page 588: ...reeze This also applies when switching from normal DMA mode DMAOR DDT 0 to DDT mode 12 Confirming DMA transfer requests and number of transfers executed The channel associated with a DMA bus cycle being executed in response to a DMA transfer request can be confirmed by determining the level of external pins ID1 and ID0 at the rising edge of the CKIO clock while is asserted ID 00 channel 0 ID 01 ch...

Page 589: ...ck id 2 0 ID 1 0 D 31 0 DBREQ SAR0 7 DAR0 7 DMATCR0 7 CHCR0 7 DMAOR Bus interface Peripheral bus Internal bus DMAC module Count control Registr control Activation control Request priority control 32B data buffer Bus state controller On chip peripheral module External address on chip peripheral module address TMU SCI SCIF DACK0 DACK1 DRAK0 DRAK1 DMAOR SAR DAR DMATCR CHCR DMAC operation register DMA...

Page 590: ...l device Notification to external device of start of execution DMA transfer end notification DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device 1 DMA transfer request Input DMA transfer request input from external device to channel 1 DREQ acceptance confirmation DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external devic...

Page 591: ...irect request to channel 2 DMAC strobe DACK0 Output Reply strobe signal for external device from DMAC Channel number notification ID 1 0 DRAK1 DACK1 Output Notification of channel number to external device at same time as output ID 1 DRAK1 ID 0 DACK1 Requests for DMA transfer from external devices are normally accepted only on channel 0 and channel 1 In DDT mode the pin functions as both the data ...

Page 592: ...unt register 1 DMATCR1 R W Undefined H FFA00018 H 1FA00018 32 1 DMA channel control register 1 CHCR1 R W H 00000000 H FFA0001C H 1FA0001C 32 DMA source address register 2 SAR2 R W Undefined H FFA00020 H 1FA00020 32 DMA destination address register 2 DAR2 R W Undefined H FFA00024 H 1FA00024 32 DMA transfer count register 2 DMATCR2 R W Undefined H FFA00028 H 1FA00028 32 2 DMA channel control registe...

Page 593: ... CHCR5 R W H 00000000 H FFA0006C H 1FA0006C 32 DMA source address register 6 SAR6 R W Undefined H FFA00070 H 1FA00070 32 DMA destination address register 6 DAR6 R W Undefined H FFA00074 H 1FA00074 32 DMA transfer count register 6 DMATCR6 R W Undefined H FFA00078 H 1FA00078 32 6 DMA channel control register 6 CHCR6 R W H 00000000 H FFA0007C H 1FA0007C 32 DMA source address register 7 SAR7 R W Undef...

Page 594: ... registers are the same as on the SH7751 For more information see section 14 2 1 DMA Source Address Registers 0 3 SAR0 SAR3 14 7 2 DMA Destination Address Registers 0 7 DAR0 DAR7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W...

Page 595: ...1DSA0 DTC DS RL AM AL Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 QCL IE TE DE Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W DMA channel control registers 0 7 CHCR0 CHCR7 are 32 bit...

Page 596: ...sters 0 3 CHCR0 CHCR3 Bit 24 Destination Address Wait Control Select DTC Specifies CS5 or CS6 space wait cycle control for PCMCIA access This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control For details of the settings see the description of the DTC bit in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bits 23 to 20 Reserved These bits ar...

Page 597: ...and 0 SM1 SM0 These bits specify incrementing decrementing of the DMA transfer source address The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode For details of the settings see the description of the SM1 and SM0 bits in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bits 11 to 8 Resource Select 3 to 0 ...

Page 598: ...before TE is set to 1 for example due to an NMI interrupt address error or clearing of the DE bit or the DME bit in DMAOR the TE bit is not set to 1 When this bit is 1 the transfer enabled state is not entered even if the DE bit is set to 1 For details of the settings see the description of the TE bit in section 14 2 4 DMA Channel Control Registers 0 3 CHCR0 CHCR3 Bit 0 DMAC Enable DE Enables oper...

Page 599: ...ts in DDT mode Bit 14 DBL Description 0 Four DDT mode channels Initial value 1 Eight DDT mode channels Note When DMAOR DBL 0 channels 4 to 7 do not accept external requests When DMAOR DBL 1 one channel can be selected from among channels 0 7 by the combination of DTR SZ and DTR ID in the DTR format see figure 14 54 Table 14 15 shows the channel selection by DTR format in the DDT mode Table 14 15 C...

Page 600: ...ting 0 after reading 1 For details of the settings see the description of the AE bit in section 14 2 5 DMA Operation Register DMAOR Bit 1 NMI Flag NMIF Indicates that NMI has been input This bit is set regardless of whether or not the DMAC is operating If this bit is set during data transfer transfers on all channels are suspended The CPU cannot write 1 to NMIF This bit can only be cleared by writ...

Page 601: ...de DMA Transfer For DMA transfer in DDT mode the DMAOR DBL setting selects either four or eight channels External requests are accepted on channels 0 3 when DMAOR DBL 0 and on channels 0 7 when DMAOR DBL 1 For further information on these settings see the entry on the DBL bit in section 14 7 5 DMA Operation Register DMAOR 14 8 3 Transfer Channel Notification in DDT Mode When the DMAC is set up for...

Page 602: ...e 14 17 Function of Function of High Bus available data bus enabled Low Notification of channel number 14 8 4 Clearing Request Queues by DTR Format In DDT mode the request queues of any channel can be cleared by using DTR ID DTR MD DTR SZ and DTR COUNT 7 4 in a DTR format This function is only available when DMAOR DBL 1 Table 14 18 shows the DTR format settings for clearing request queues ...

Page 603: ... Clear the CH2 request queues 0100 Clear the CH3 request queues 0101 Clear the CH4 request queues 0110 Clear the CH5 request queues 0111 Clear the CH6 request queues 1 00 11 110 1000 Clear the CH7 request queues Note SH7751R DTR SZ DTR 31 29 DTR ID DTR 27 26 DTR MD DTR 25 24 DTR COUNT 7 4 DTR 23 20 14 8 5 Interrupt Request Codes When the number of transfers specified in DMATCR has been finished an...

Page 604: ...es Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer end interrupt H 640 High DMTE1 CH1 transfer end interrupt H 660 DMTE2 CH2 transfer end interrupt H 680 DMTE3 CH3 transfer end interrupt H 6A0 DMTE4 CH4 transfer end interrupt H 780 DMTE5 CH5 transfer end interrupt H 7A0 DMTE6 CH6 transfer end interrupt H 7C0 DMTE7 CH7 transfer end interrupt H 7E0 DMAE Address error inte...

Page 605: ...e 566 of 1064 CKIO RA DTR CA D1 D2 RD BA 00 ID1 ID0 RAS CAS WE D63 D0 A25 A0 D0 Figure 14 56 Single Address Mode Cycle Steal Mode External Bus External Device 32 Byte Block Transfer On Demand Data Transfer on Channel 4 ...

Page 606: ...TE 1 in the SH7751 s CHCR0 CHCR3 or in the SH7751R s CHCR0 CHCR7 or clear DME to 0 in DMAOR to terminate DMA transfer When DME is cleared to 0 in DMAOR transfer halts at the end of the currently executing DMA bus cycle Note therefore that transfer may not end immediately depending on the transfer data size DMA operation is not guaranteed if the module standby state standby mode or deep sleep mode ...

Page 607: ...Rev 3 0 04 02 page 568 of 1064 ...

Page 608: ... asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiproc...

Page 609: ... and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources transmit data empty transmit end receive data full and receive error that can issue requests independently The transmit data empty interrup...

Page 610: ...ption control Baud rate generator Clock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TEI TXI RXI ERI SCI Bus interface Internal data bus SCSPTR1 SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register SCBRR1 Bit rate register SCSPTR1 Serial port register Fi...

Page 611: ...rform transmitter receiver control With the exception of the serial port register the SCI registers are initialized in standby mode and in the module standby state as well as after a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 15 2 SCI Registers Name Abbreviation R W Initial Value P4 Address Area 7 Address Acces...

Page 612: ...PU 15 2 2 Receive Data Register SCRDR1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R SCRDR1 is the register that stores received serial data When the SCI has received one byte of serial data it transfers the received data from SCRSR1 to SCRDR1 where it is stored and completes the receive operation SCRSR1 is then enabled for reception Since SCRSR1 and SCRDR1 function as a do...

Page 613: ...erial status register SCSSR1 is set to 1 SCTSR1 cannot be directly read or written to by the CPU 15 2 4 Transmit Data Register SCTDR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W SCTDR1 is an 8 bit register that stores data for serial transmission When the SCI detects that SCTSR1 is empty it transfers the transmit data written in SCTDR1 to SCTSR1 and starts...

Page 614: ...lects 7 or 8 bits as the data length in asynchronous mode In synchronous mode a fixed data length of 8 bits is used regardless of the CHR setting Bit 6 CHR Description 0 8 bit data Initial value 1 7 bit data Note When 7 bit data is selected the MSB bit 7 of SCTDR1 is not transmitted Bit 5 Parity Enable PE In asynchronous mode selects whether or not parity bit addition is performed in transmission ...

Page 615: ...on is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd Bit 3 Stop Bit Length STOP Selects 1 or 2 bits as the stop bit length in asynchronous mode The STOP bit setting is only valid in asynchronous mode If synchro...

Page 616: ...om P P 4 P 16 and P 64 according to the setting of bits CKS1 and CKS0 For the relation between the clock source the bit rate register setting and the baud rate see section 15 2 9 Bit Rate Register SCBRR1 Bit 1 CKS1 Bit 0 CKS0 Description 0 0 P clock Initial value 1 P 4 clock 1 0 P 16 clock 1 P 64 clock Note P Peripheral clock 15 2 6 Serial Control Register SCSCR1 Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE ...

Page 617: ...ed from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1 Bit 6 RIE Description 0 Receive data full interrupt RXI request and receive error interrupt ERI request disabled Initial value 1 Receive data full interrupt RXI request and receive error interrupt ERI request enabled Note RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag or the FER PER or ORER flag then cl...

Page 618: ...de or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts disabled normal reception performed Initial value Clearing conditions When the MPIE bit is cleared to 0 When data with MPB 1 is received 1 Multiprocessor interrupts enabled Note When receive data including MPB 1 is received the MPIE bit is cleared to 0 automatically and generation of RXI and ERI interrupts whe...

Page 619: ...ls of clock source selection see table 15 9 in section 15 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as input pin input signal ignored 1 Synchronous mode Internal clock SCK pin functions as serial clock output 1 1 Asynchronous mode Internal clock SCK pin functions as clock output 2 Synchronous mode Internal clock SCK pin functions as serial...

Page 620: ...ag and MPB flag are read only flags and cannot be modified SCSSR1 is initialized to H 84 by a power on reset or manual reset in standby mode and in the module standby state Bit 7 Transmit Data Register Empty TDRE Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1 Bit 7 TDRE Description 0 Valid transmit data has been written to ...

Page 621: ... completed while the RDRF flag is still set to 1 an overrun error will occur and the receive data will be lost Bit 5 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 5 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset manual reset standby mode or module standby Whe...

Page 622: ...rs the receive data is transferred to SCRDR1 but the RDRF flag is not set Serial reception cannot be continued while the FER flag is set to 1 Bit 3 Parity Error PER Indicates that a parity error occurred during reception with parity addition in asynchronous mode causing abnormal termination Bit 3 PER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing condi...

Page 623: ...tten to The read value is undefined Note This bit is prepared for storing a multi processor bit in the received data when the receipt is carried out with a multi processor format in asynchronous mode however this does not function correctly in this LSI Do not use the read value from this bit Bit 0 Multiprocessor Bit Transfer MPBT When transmission is performed using a multiprocessor format in asyn...

Page 624: ...ialized in the module standby state or standby mode Bit 7 Error Interrupt Only EIO When the EIO bit is 1 an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1 When the DMAC is used this setting means that only ERI interrupts are handled by the CPU The DMAC transfers read data to memory or another peripheral module This bit specifies enabling or disabling of the RXI interr...

Page 625: ... When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin Initial value 1 SPB0DT bit value is output to the TxD pin Bit 0 Serial Port Break Data SPB0DT Specifies the serial port RxD pin input data and TxD pin output data The TxD pin output co...

Page 626: ...O C R Q D SPB1DT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SCK SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C bit in SCSMR1 Figure 15 2 SCK Pin ...

Page 627: ...ernal data bus SPTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C TxD Transmit enable signal Serial transmit data SPTRW Write to SPTR Figure 15 3 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data SPTRR Read SPTR Figure 15 4 RxD Pin ...

Page 628: ...U at all times SCBRR1 is initialized to H FF by a power on reset or manual reset in standby mode and in the module standby state The SCBRR1 setting is found from the following equations Asynchronous mode N 106 1 64 22n 1 B φ P Synchronous mode N 106 1 8 22n 1 B φ P Where B Bit rate bits s N SCBRR1 setting for baud rate generator 0 N 255 P Peripheral module operating frequency MHz n Baud rate gener...

Page 629: ...e bit rate error in asynchronous mode is found from the following equation Error 100 P 106 N 1 B 64 22n 1 φ 1 Table 15 3 shows sample SCBRR1 settings in asynchronous mode and table 15 4 shows sample SCBRR1 settings in synchronous mode ...

Page 630: ...00 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 P MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1 64 0 16 1200 0 95 0 00 0 ...

Page 631: ... 00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 P MHz 9 8304 10 12 12 288 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 129 0 16...

Page 632: ... 0 63 0 00 0 64 0 16 19200 0 23 0 00 0 25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 P MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 0 ...

Page 633: ... 5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 0 29 500k 0 1 0 3 0 7 0 14 1M 0 0 0 1 0 3 2M 0 0 0 1 Note As far as possible the setting should be made so that the error is within 1 Blank No setting is available A setting is available but error o...

Page 634: ...mum Bit Rate for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings P MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 0 30 937500...

Page 635: ... 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 Table 15 7 Maximum Bit Rate with External Clock Input Synchronous Mode P MHz External Input Clock MHz Maximum Bit Rate bits s 8 1 3333 1333333 3 16 2 6667 2666666 7 24...

Page 636: ... these parameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When internal clock is selected The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected A clock with a fre...

Page 637: ...0 1 bit 0 1 1 1 Asynchronous mode multiprocessor format 7 bit data Yes 2 bits 1 Synchronous mode 8 bit data No No None Note An asterisk in the table means Don t care Table 15 9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting SCI Transmit Receive Clock Bit 7 C Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Internal SCI does not use SCK pin 1 Outputs c...

Page 638: ...on line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by data in LSB first order a parity bit high or low level and finally one or two stop bits high level In asynchronous mode the SCI performs synchronization at the falling edge of the start bit in reception The SCI...

Page 639: ... data STOP STOP 0 1 0 0 S 8 bit data P STOP 0 1 0 1 S 8 bit data P STOP STOP 1 0 0 0 S 7 bit data STOP 1 0 0 1 S 7 bit data STOP STOP 1 1 0 0 S 7 bit data P STOP 1 1 0 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 0 1 1 S 8 bit data MPB STOP STOP 1 1 0 S 7 bit data MPB STOP 1 1 1 S 7 bit data MPB STOP STOP Note An asterisk in the table means Don t care S Start bit STOP Stop bit P Parity b...

Page 640: ...igure 15 6 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 One frame 0 Figure 15 6 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations SCI Initialization Asynchronous Mode Before transmitting and receiving data it is necessary to clear the TE and RE bits in SCSCR1 to 0 then initialize the SCI as described below When the operating mode transfer format etc is changed the...

Page 641: ...ttings are made 2 Set the data transfer format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also set the RIE TIE TEIE and MPIE bits Setting the TE and RE bits enables the TxD and RxD pins to be used When transmitting the SCI will go to the mark state when ...

Page 642: ...DR1 and clear the TDRE flag to 0 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the direct memory access controller DMAC is activated by a transmit data empty interrupt TXI request and data i...

Page 643: ...ity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is ...

Page 644: ...ten to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request TXI interrupt request Figure 15 9 Example of Transmit Operation in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit Serial Data Reception Asynchronous Mode Figure 15 10 shows a sample flowchart for serial reception Use the following procedure for serial data reception after enabling the S...

Page 645: ...e ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the RxD pin 2 SCI status check and receive data read Read SCSSR1 and check that RDRF 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 3 Serial reception continuation procedure To continue seria...

Page 646: ... ORER 1 FER 1 Break PER 1 End Yes Yes No Yes No No No Yes Clear ORER PER and FER flags in SCSSR1 to 0 Parity error handling Framing error handling Clear RE bit in SCSCR1 to 0 Overrun error handling Figure 15 10 Sample Serial Reception Flowchart 2 ...

Page 647: ...on is as shown in table 15 11 Note No further receive operations can be performed when a receive error has occurred Also note that the RDRF flag is not set to 1 in reception and so the error flags must be cleared to 0 4 If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated If the RIE bi...

Page 648: ...unique ID code The serial communication cycle consists of two cycles an ID transmission cycle which specifies the receiving station and a data transmission cycle The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as ...

Page 649: ...ry data is achieved by collaborative operation with the exception handling routine Transmitting station Receiving station A Receiving station B Receiving station C Receiving station D ID 01 ID 02 ID 03 ID 04 Serial transmission line MPB 1 MPB 0 H 01 H AA MPB Multiprocessor bit Serial data ID transmission cycle Receiving station specification Data transmission cycle Data transmission to receiving s...

Page 650: ...ation is invalid For details see table 15 10 Clock See the description under Clock in section 15 3 2 Data Transfer Operations Multiprocessor Serial Data Transmission Figure 15 13 shows a sample flowchart for multiprocessor serial data transmission Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission ...

Page 651: ...and write ID data to SCTDR1 Finally clear the TDRE flag to 0 2 Preparation for data transfer Read SCSSR1 and check that the TEND flag is set to 1 then set the MPBT bit in SCSSR1 to 1 3 Serial data transmission Write the first transmit data to SCTDR1 then clear the TDRE flag to 0 To continue data transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data t...

Page 652: ...t starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is set to 1 the TEND flag in SCSSR1 is set to 1 the stop bit is sent and then the line goes to the mark state in which 1 is output If the TEIE bit in SCSCR1 is set to 1 at this time a transmit end interrupt TEI request is generated 4 The SCI monitors the TDRE flag When TDRE...

Page 653: ...1 1 1 Multi proces sor bit Multi proces sor bit Multi proces sor bit Stop bit Start bit Stop bit Stop bit Start bit Data Data Data Start bit TDRE TEND One frame Idle state mark state Figure 15 14 Example of SCI Transmit Operation Example with 8 Bit Data Multiprocessor Bit One Stop Bit Multiprocessor Serial Data Reception Figure 15 15 shows a sample flowchart for multiprocessor serial reception Use...

Page 654: ... MPIE bit is set to 0 then read the receive data in SCRDR1 and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 3 SCI status check and data reception Read SCSSR1 and check that the RDRF flag is set to 1 then read the data in SCRDR1 4 Receive error handling and br...

Page 655: ...ER 1 FER 1 Error handling Overrun error handling Break Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Yes No No Yes Yes No Figure 15 15 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 656: ...0 by RXI interrupt handler As data is not this station s ID MPIE bit is set to 1 again RXI interrupt request MPB Serial data Start bit Data ID2 Stop bit Start bit Data Data2 Stop bit Idle state mark state a Data does not match station s ID SCRDR1 value RXI interrupt request multiprocessor interrupt MPIE 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this sta...

Page 657: ...RSR1 is transferred to SCRDR1 and if the stop bit is 0 RDRF is set to 1 15 3 4 Operation in Synchronous Mode In synchronous mode data is transmitted or received in synchronization with clock pulses making it suitable for high speed serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also hav...

Page 658: ...SCI clock source selection see table 15 9 When the SCI is operated on an internal clock the serial clock is output from the SCK pin Eight serial clock pulses are output in the transfer of one character and when no transfer is performed the clock is fixed high In reception only if an on chip clock source is selected clock pulses are output while RE 1 When the last data is received RE should be clea...

Page 659: ...s in SCSCR1 to 0 Initialization 1 Set the clock selection in SCSCR1 Be sure to clear bits RIE TIE TEIE and MPIE TE and RE to 0 2 Set the data transfer format in SCSMR1 3 Write a value corresponding to the bit rate into SCBRR1 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR1 to 1 Also set the RIE TIE TEIE and MPIE bits Setting the T...

Page 660: ...a to SCTDR1 and clear TDRE flag in SCSSR1 to 0 1 SCI status check and transmit data write Read SCSSR1 and check that the TDRE flag is set to 1 then write transmit data to SCTDR1 and clear the TDRE flag to 0 2 To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to SCTDR1 and then clear the TDRE flag to 0 Checking and clearing of t...

Page 661: ...the LSB bit 0 and ending with the MSB bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from SCTDR1 to SCTSR1 and serial transmission of the next frame is started If the TDRE flag is set to 1 the TEND flag in SCSSR1 is set to 1 the MSB bit 7 is sent and the TxD pin maintains its state If the TEIE bit in SCSCR1 is set t...

Page 662: ... Yes No No Error handling 1 Receive error handling If a receive error occurs read the ORER flag in SCSSR1 and after performing the appropriate error handling clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 2 SCI status check and receive data read Read SCSSR1 and check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 T...

Page 663: ...o SCRDR1 If this check is passed the RDRF flag is set to 1 and the receive data is stored in SCRDR1 If a receive error is detected in the error check the operation is as shown in table 15 11 Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check Also as the RDRF flag is not set to 1 when receiving the flag must be cleared to 0 3...

Page 664: ...ne frame RXI interrupt request ERI interrupt request due to overrun error Figure 15 22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception Synchronous Mode Figure 15 23 shows a sample flowchart for simultaneous serial transmit and receive operations Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for t...

Page 665: ... check that the RDRF flag is set to 1 then read the receive data in SCRDR1 and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 4 Serial transmission reception continuation procedure To continue serial transmission reception finish reading the RDRF flag reading SCRDR1 and clearing the RDRF flag to 0 before the MSB bit 7 of the current fram...

Page 666: ...ransfer The RDRF flag is cleared to 0 automatically when a receive data register SCRDR1 read is performed by the DMAC When the ORER FER or PER flag in SCSSR1 is set to 1 an ERI interrupt request is generated The DMAC cannot be activated by an ERI interrupt request When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to...

Page 667: ...shown in table 15 13 If there is an overrun error data is not transferred from SCRSR1 to SCRDR1 and the receive data is lost Table 15 13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors RDRF ORER FER PER Receive Data Transfer SCRSR1 SCRDR1 Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error framing error 1 1 1 0 X Overrun error pa...

Page 668: ...ssion When the TE bit is cleared to 0 the transmitter is initialized regardless of its current state and the TxD pin becomes an output port outputting the value 0 Receive Error Flags and Transmit Operations Synchronous Mode Only Transmission cannot be started when a receive error flag ORER PER or FER is set to 1 even if the TDRE flag is set to 1 Be sure to clear the receive error flags to 0 before...

Page 669: ...onous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N 1 M Receive margin N Ratio of clock frequency to bit rate N 16 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 When D 0 5 and F 0 M ...

Page 670: ...ipheral operating clock cycles after external clock SCK has changed from 0 to 1 Only set both TE and RE to 1 when external clock SCK is 1 In reception note that if RE is cleared to 0 from 2 5 to 3 5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input RDRF will be set to 1 but copying to SCRDR1 will not be possible When Using Synchronous Internal Clock Mode In recept...

Page 671: ...Rev 3 0 04 02 page 632 of 1064 ...

Page 672: ...r UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun errors Break detection If the receive data following that in which a framing error occurred is also at the space 0 level and there is a frame error a break is detec...

Page 673: ...er by issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be stopped by halting its clock supply to reduce power consumption Modem control functions and are provided The amount of data in the transmit receive FIFO registers and the number of receive errors in the receive data in the receive FIFO register can be ...

Page 674: ...ock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI BRI SCIF Bus interface Internal data bus SCSCR2 SCSPTR2 SCRSR2 Receive shift register SCFRDR2 Receive FIFO data register SCTSR2 Transmit shift register SCFTDR2 Transmit FIFO data register SCSMR2 Serial mode register SCSCR2 Serial control register SCFSR2 Serial status register SCBRR2 Bit rate register SCSPTR2 Serial port register SCFCR2 FIFO contro...

Page 675: ...a format and bit rate and to perform transmitter receiver control Table 16 2 SCIF Registers Name Abbrevia tion R W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR2 R W H 0000 H FFE80000 H IFE80000 16 Bit rate register SCBRR2 R W H FF H FFE80004 H IFE80004 8 Serial control register SCSCR2 R W H 0000 H FFE80008 H IFE80008 16 Transmit FIFO data register SCFTDR2 W Undefi...

Page 676: ... R W R R R R R R R R SCFRDR2 is a 16 stage FIFO register that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR2 to SCFRDR2 where it is stored and completes the receive operation SCRSR2 is then enabled for reception and consecutive receive operations can be performed until the receive FIFO register is full 16 data bytes SCFRDR2...

Page 677: ...ally SCTSR2 cannot be directly read or written to by the CPU 16 2 4 Transmit FIFO Data Register SCFTDR2 Bit 7 6 5 4 3 2 1 0 R W W W W W W W W W SCFTDR2 is a 16 stage FIFO register that stores data for serial transmission If SCTSR2 is empty when transmit data has been written to SCFTDR2 the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission SCFTDR2 is a wri...

Page 678: ...asynchronous mode data length Bit 6 CHR Description 0 8 bit data Initial value 1 7 bit data Note When 7 bit data is selected the MSB bit 7 of SCFTDR2 is not transmitted Bit 5 Parity Enable PE Selects whether or not parity bit addition is performed in transmission and parity bit checking in reception Bit 5 PE Description 0 Parity bit addition and checking disabled Initial value 1 Parity bit additio...

Page 679: ...e 1 2 stop bits 2 Notes 1 In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sent 2 In transmission two 1 bits stop bits are added to the end of a transmit character before it is sent In reception only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit if it is 0 it is treated as the...

Page 680: ...data empty interrupt TXI request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2 the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number and the TDFE flag in the serial status register SCFSR2 is set to 1 Bit 7 TIE Description 0 Transmit FIFO data empty interrupt TXI request disabled Initial value 1 Transmit FIFO data empty...

Page 681: ...by the SCIF Bit 5 TE Description 0 Transmission disabled Initial value 1 Transmission enabled Note Serial transmission is started when transmit data is written to SCFTDR2 in this state Serial mode register SCSMR2 and FIFO control register SCFCR2 settings must be made the transmission format decided and the transmit FIFO reset before the TE bit is set to 1 Bit 4 Receive Enable RE Enables or disable...

Page 682: ...nterrupt controller is to be notified of ERI and BRI interrupt requests Bits 1 and 0 Clock Enable 1 and 0 CKE1 and CKE0 These bits select the SCIF clock source and enable disable clock output from the SCK2 pin The combination of CKE1 and CKE0 determine whether the SCK2 pin functions as serial clock output pin or the serial clock input pin Note however that the setting of the CKE0 bit is valid only...

Page 683: ...ad only flags and cannot be modified SCFSR2 is initialized to H 0060 by a power on reset or manual reset It is not initialized in standby mode or in the module standby state Bits 15 to 12 Number of Parity Errors PER3 PER0 These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2 After the ER bit in SCFSR2 is set the value indicated by bits ...

Page 684: ...it 7 ER Description 0 No framing error or parity error occurred during reception Initial value Clearing conditions Power on reset or manual reset When 0 is written to ER after reading ER 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 When in rece...

Page 685: ...Transmission is in progress Clearing conditions When transmit data is written to SCFTDR2 and 0 is written to TEND after reading TEND 1 When data is written to SCFTDR2 by the DMAC 1 Transmission has been ended Initial value Setting conditions Power on reset or manual reset When the TE bit in SCSCR2 is 0 When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1 byte serial tra...

Page 686: ...er on reset or manual reset When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation Note As SCFTDR2 is a 16 byte FIFO register the maximum number of bytes that can be written when TDFE 1 is 16 transmit trigger set number Data written in excess of this will be ignored The number of data bytes in SCFTDR2 is indicated by t...

Page 687: ...o be read from SCFRDR2 Setting condition When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2 Parity Error PER Indicates whether or not a parity error has been found in the data that is to be read from the receive FIFO data register SCFRDR2 Bit 2 PER Description 0 There is no parity error in the receive data that is to be read from SCFRDR2 Initial value Clearing con...

Page 688: ...a bytes in SCFRDR2 falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number 1 The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number Setting condition When SCFRDR2 contains at least the receive tr...

Page 689: ...ata has arrived Setting condition When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes and no further data has arrived for at least 15 etu after the stop bit of the last data received Note Equivalent to 1 5 frames with an 8 bit 1 stop bit format etu Elementary time unit time for transfer of 1 bit 16 2 8 Bit Rate Register SCBRR2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1...

Page 690: ... 0 3 P 64 1 1 The bit rate error in asynchronous mode is found from the following equation Error 1 100 P 106 N 1 B 64 22n 1 φ 16 2 9 FIFO Control Register SCFCR2 Bit 15 14 13 12 11 10 9 8 RSTRG2 RSTRG1 RSTRG0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bit 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W SCFC...

Page 691: ...data register SCFRDR2 exceeds the trigger number as shown in the table below Bit 10 RSTRG2 Bit 9 RSTRG1 Bit 8 RSTRG0 Output Active Trigger 0 0 0 15 Initial value 1 1 1 0 4 1 6 1 0 0 8 1 10 1 0 12 1 14 Bits 7 and 6 Receive FIFO Data Number Trigger RTRG1 RTRG0 These bits are used to set the number of receive data bytes that sets the receive data full RDF flag in the serial status register SCFSR2 The...

Page 692: ...nd modem control signals Bit 3 MCE Description 0 Modem signals disabled Initial value 1 Modem signals enabled Note is fixed at active 0 regardless of the input value and output is also fixed at 0 Bit 2 Transmit FIFO Data Register Reset TFRST Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state Bit 2 TFRST Description 0 Reset operation disabled Initial v...

Page 693: ...DR2 and the lower 8 bits show the number of receive data bytes in SCFRDR2 SCFDR2 can be read by the CPU at all times Bit 15 14 13 12 11 10 9 8 T4 T3 T2 T1 T0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2 A value of H 00 indicates that there is no transmit data and a value of H 10 indicates that SCFTDR2 is full of transmit data B...

Page 694: ... written to by the CPU at all times All SCSPTR2 bits except bits 6 4 2 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 6 4 2 and 0 is undefined SCSPTR2 is not initialized in standby mode or in the module standby state Bits 15 to 8 Reserved These bits are always read as 0 and should only be written with 0 Bit 7 Serial Port RTS Port I O RTSIO Specifies the serial por...

Page 695: ...t The initial value of this bit after a power on reset or manual reset is undefined Bit 4 CTSDT Description 0 Input output data is low level 1 Input output data is high level Bit 3 Serial Port Clock Port I O SCKIO Sets the I O for the SCK2 pin serial port To actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit set the CKE1 and CKE0 bits of the SCSCR2 register ...

Page 696: ... value 1 SPB2DT bit value is output to the TxD2 pin Bit 0 Serial Port Break Data SPB2DT Specifies the serial port RxD2 pin input data and TxD2 pin output data The TxD2 pin output condition is specified by the SPB2IO bit see the description of bit 1 SPB2IO for details When the TxD2 pin is designated as an output the value of the SPB2DT bit is output to the TxD2 pin The RxD2 pin value is read from t...

Page 697: ...et Internal data bus SPTRW D7 D6 SCIF R Q D RTSIO C Reset Mode setting register SPTRR SPTRW R Q D RTSDT C MD8 RTS2 SPTRW Write to SPTR SPTRR Read SPTR Note The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2 Modem control enable signal RTS2 signal Figure 16 2 MD8 RTS2 Pin ...

Page 698: ...4 SCIF R Q D CTSIO C Reset SPTRR Mode setting register SPTRW R Q D CTSDT C MD7 CTS2 SPTRW Write to SPTR SPTRR Read SPTR Note The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2 Modem control enable signal CTS2 signal Figure 16 3 MD7 CTS2 Pin ...

Page 699: ...ster SCIF R Q D D1 D0 SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 16 4 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR D0 Serial receive data SPTRR Read SPTR Figure 16 5 MD2 RxD2 Pin ...

Page 700: ...t enable signal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK2 Mode setting register SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2 Figure 16 6 MD0 SCK2 Pin ...

Page 701: ...abnormal termination Bit 0 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 2 Setting condition When the next serial reception is completed while the receive FIFO is full Notes 1 The ORER flag is not affected and reta...

Page 702: ...on of these parameters determines the transfer format and character length Detection of framing errors parity errors receive FIFO data full state overrun errors receive data ready state and breaks during reception Indication of the number of data bytes stored in the transmit and receive FIFO registers Choice of internal or external clock as SCIF clock source When internal clock is selected The SCI...

Page 703: ...K2 Pin Function 0 SCIF does not use SCK2 pin 0 1 Internal Output clock with frequency of 16 times the bit rate 0 1 1 Asynchronous mode External Inputs clock with frequency of 16 times the bit rate 16 3 2 Serial Operation Data Transfer Format Table 16 5 shows the data transfer formats that can be used Any of 8 transfer formats can be selected according to the SCSMR2 settings ...

Page 704: ...data P STOP STOP S Start bit STOP Stop bit P Parity bit Clock Either an internal clock generated by the on chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF s serial clock according to the setting of the CKE1 bit in SCSCR2 For details of SCIF clock source selection see table 16 4 When an external clock is input at the SCK2 pin the clock frequency shoul...

Page 705: ...nd RE bits to 0 does not change the contents of SCFSR2 SCFTDR2 or SCFRDR2 The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set TEND can also be cleared to 0 during transmission but the data being transmitted will go to the mark state after the clearance Before setting TE again to start transmission the TFRST bit in SCFCR2 should first be ...

Page 706: ...ts End Wait No Yes 1 Set the clock selection in SCSCR2 Be sure to clear bits RIE and TIE and bits TE and RE to 0 2 Set the data transfer format in SCSMR2 3 Write a value corresponding to the bit rate into SCBRR2 Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR2 to 1 Also set the RIE REIE and TIE bits Setting the TE and RE bits enabl...

Page 707: ... that the TDFE flag is set to 1 then write transmit data to SCFTDR2 read 1 from the TDFE and TEND flags then clear these flags to 0 The number of transmit data bytes that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR2 and then clear...

Page 708: ...this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD2 pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selected d Stop bit s One or two 1 bits sto...

Page 709: ... 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the input value When is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When is set to 0 the next transmit data is output starting from the start bit Figure 16 10 shows an example of the operation when modem control is ...

Page 710: ...o identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the RxD2 pin 2 SCIF status check and receive data read Read SCFSR2 and check that RDF 1 then read the receive data in SCFRDR2 read 1 from the RDF flag and then clear the RDF flag to 0 The transition of the RDF f...

Page 711: ...g ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2 2 When a break signal is received receive data is not transferred to SCFRDR2 while the BRK flag is set However note that the last data in SCFRDR2 is H 00 the break data in which a framing error occurred is stored Figure 16 11 Samp...

Page 712: ...ft register SCRSR2 to SCFRDR2 c Overrun error check The SCIF checks that the ORER flag is 0 indicating that no overrun error has occurred d Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If all the b c and d checks are passed the receive data is stored in SCFRDR2 Note Reception continues when parity error framing error occurs 4 If the RIE bit in SCSCR...

Page 713: ... Parity One Stop Bit 5 When modem control is enabled the signal is output when SCFRDR2 is empty When is 0 reception is possible When is 1 this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the output active trigger set number The output active trigger value is specified by bits 10 to 8 in the FIFO control register SCFCR2 described in section 16 2 9 RTS2 also goes ...

Page 714: ...rupt request A transmit FIFO data empty request can activate the DMAC to perform data transfer When the RDF flag or DR flag in SCFSR2 is set to 1 a receive FIFO data full request is generated separately from the interrupt request A receive FIFO data full request can activate the DMAC to perform data transfer When using the DMAC for transmission reception set and enable the DMAC before making the S...

Page 715: ...ster SCFSR2 is set when the number of receive data bytes in the receive FIFO data register SCFRDR2 has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register SCFCR2 After RDF is set receive data equivalent to the trigger number can be read from SCFRDR2 allowing efficient continuous reception However if the number of data bytes in SCFRDR2...

Page 716: ...IF operates on a base clock with a frequency of 16 times the bit rate In reception the SCIF synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the eighth base clock pulse The timing is shown in figure 16 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 D0 D1 16 clocks 8 cl...

Page 717: ... 30 When Using the DMAC When using the DMAC for transmission reception inhibit output of RXI and TXI interrupt requests to the interrupt controller If interrupt request output is enabled interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler Serial Ports Note that when the SCIF pin value is read using a serial port the value read will be ...

Page 718: ...re listed below Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported On chip baud rate generator allows any bit rate to be selected Three interrupt sources There are three interrupt sources tra...

Page 719: ...d rate generator Clock External clock Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI SCI Bus interface Internal data bus SCSMR1 SCSCMR1 Smart card mode register SCRSR1 Receive shift register SCRDR1 Receive data register SCTSR1 Transmit shift register SCTDR1 Transmit data register SCSMR1 Serial mode register SCSCR1 Serial control register SCSSR1 Serial status register SCBRR1 Bit rate register SCSPTR1 Serial port ...

Page 720: ...itialized in standby mode and in the module standby state as well as by a power on reset or manual reset When recovering from standby mode or the module standby state the registers must be set again Table 17 2 Smart Card Interface Registers Name Abbreviation R W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R W H 00 H FFE00000 H 1FE00000 8 Bit rate register SCBRR1...

Page 721: ...er Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 SCTDR1 contents are transmitted LSB first Initial value Receive data is stored in SCRDR1 LSB first 1 SCTDR1 contents are transmitted MSB first Receive data is stored in SCRDR1 MSB first Bit 2 Smart Card Data Invert SINV Specifies inversion of the data logic level This function is used together with the bit 3 f...

Page 722: ...cates completion of transmission and the type of clock output used The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register SCSCR1 In GSM mode the pulse width is guaranteed when SCK start stop specifications are made by CKE1 and CKE0 Bit 7 GM Description 0 Normal smart card interface mode operation Initial value The TEND flag is...

Page 723: ...ock Enable 1 and 0 CKE1 CKE0 These bits specify the function of the SCK pin In smart card interface mode an internal clock is always used as the clock source In smart card interface mode it is possible to specify a fixed high level or fixed low level for the clock output in addition to the usual switching between enabling and disabling of the clock output GM CKE1 CKE0 SCK Pin Function 0 0 0 Port I...

Page 724: ...it 4 indicates the status of the error signal sent back from the receiving side during transmission Framing errors are not detected in smart card interface mode Bit 4 ERS Description 0 Normal reception no error signal Initial value Clearing conditions Power on reset manual reset standby mode or module standby When 0 is written to ERS after reading ERS 1 1 An error signal has been sent from the rec...

Page 725: ...tu after transmission of a 1 byte serial character etu Elementary time unit time for transfer of 1 bit Bits 1 and 0 Not used with the smart card interface 17 3 Operation 17 3 1 Overview The main functions of the smart card interface are as follows One frame consists of 8 bit data plus a parity bit In transmission a guard time of at least 2 etu elementary time unit the time for transfer of one bit ...

Page 726: ...hen the clock generated on the smart card interface is used by an IC card the SCK pin output is input to the CLK pin of the IC card No connection is needed if the IC card uses an internal clock Chip port output is used as the reset signal Other pins must normally be connected to the power supply or ground Note If an IC card is not connected and both TE and RE are set to 1 closed transmission recep...

Page 727: ...Transmitting station output Transmitting station output Receiving station output Figure 17 3 Smart Card Interface Data Format The operation sequence is as follows 1 When the data line is not in use it is in the high impedance state and is fixed high with a pull up resistor 2 The transmitting station starts transmission of one frame of data The data frame starts with a start bit Ds low level follow...

Page 728: ...setting of other bits is described below Table 17 3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER ERS PER TEND 0 0 SCRDR1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0...

Page 729: ...nverse convention type The SMIF bit is set to 1 when the smart card interface is used Figure 17 5 shows examples of register settings and the waveform of the start character for the two types of IC card direct convention and inverse convention With the direct convention type the logic 1 level corresponds to state Z and the logic 0 level to state A and transfer is performed in LSB first order The s...

Page 730: ...rt card interface The bit rate is set with the bit rate register SCBRR1 and the CKS1 and CKS0 bits in the serial mode register SCSMR1 The equation for calculating the bit rate is shown below Table 17 5 shows some sample bit rates If clock output is selected with CKE0 set to 1 a clock with a frequency of 372 times the bit rate is output from the SCK pin B 106 1488 22n 1 N 1 φ P Where N Value set in...

Page 731: ...eripheral module operating frequency and bit rate is shown below Here N is an integer in the range 0 N 255 and the smaller error is specified N 106 1 1488 22n 1 B φ P Table 17 6 Examples of SCBRR1 Settings for Bit Rate B bits s When n 0 P MHz 7 1424 10 00 10 7136 14 2848 25 00 33 00 50 00 Bits s N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 00 1 25 00 1 8 99 3 14 27 4 8 ...

Page 732: ...PTR1 1 0 0 1 SCK serial clock output state 2 2 1 1 0 0 Low output Low level output state 1 1 0 1 SCK serial clock output state 3 2 1 1 1 0 High output High level output state 1 1 1 1 SCK serial clock output state Notes 1 The SCK output state changes as soon as the CKE0 bit setting is changed Clear the CKE1 bit to 0 2 Stopping and starting the clock by changing the CKE0 bit setting does not affect ...

Page 733: ...t O and baud rate generator select bits CKS1 and CKS0 in the serial mode register SCSMR1 Clear the CHR and MP bits to 0 and set the STOP and PE bits to 1 4 Set the SMIF SDIR and SINV bits in the smart card mode register SCSCMR1 When the SMIF bit is set to 1 the TxD pin and RxD pin both go to the high impedance state 5 Set the value corresponding to the bit rate in the bit rate register SCBRR1 6 Se...

Page 734: ...set parity in O bit clock in CKS1 and CKS0 bits and set GM Set SMIF SDIR and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1 set clock in CKE1 and CKE0 bits and clear TIE RIE TE RE MPIE and TEIE bits to 0 1 bit interval elapsed Set TIE RIE TE and RE bits in SCSCR1 End Wait No Yes 1 2 3 4 5 6 7 Figure 17 7 Sample Initialization Flowchart ...

Page 735: ...CSSR1 is set to 1 4 Write the transmit data to SCTDR1 clear the TDRE flag to 0 and perform the transmit operation The TEND flag is cleared to 0 5 To continue transmitting data go back to step 2 6 To end transmission clear the TE bit to 0 With the above processing interrupt handling is possible If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests a...

Page 736: ...mit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 FER ERS 0 TEND 1 All data transmitted FER ERS 0 TEND 1 Clear TE bit in SCSCR1 to 0 End of transmission Error handling Error handling No Yes Yes Yes Yes No Yes No No No 1 2 3 4 5 6 Figure 17 8 Sample Transmission Processing Flowchart ...

Page 737: ... set to 1 4 Read the receive data from SCRDR1 5 To continue receiving data clear the RDRF flag to 0 and go back to step 2 6 To end reception clear the RE bit to 0 With the above processing interrupt handling is possible If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled a receive data full interrupt RXI request will be generated If an e...

Page 738: ... When switching from receive mode to transmit mode first confirm that the receive operation has been completed then start from initialization clearing RE to 0 and setting TE to 1 The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed When switching from transmit mode to receive mode first confirm that the transmit operation has been completed the...

Page 739: ...the TXI request and transfer of the transmit data will be carried out The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC In the event of an error the SCI retransmits the same data automatically The TEND flag remains cleared to 0 during this time and the DMAC is not activated Thus the number of bytes specified by the SCI and DMAC are transmitted automatically in...

Page 740: ...eceive data is latched at the rising edge of the 186th base clock pulse The timing is shown in figure 17 10 0 185 371 0 185 371 0 Base clock 372 clocks 186 clocks Start bit D0 D1 Receive data RxD Synchronization sampling timing Data sampling timing Figure 17 10 Receive Data Sampling Timing in Smart Card Mode The receive margin in smart card mode can therefore be expressed as shown in the following...

Page 741: ... SCSSR1 should be cleared to 0 before the next parity bit is sampled 2 The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred 3 If an error is found when the received parity bit is checked the PER bit in SCSSR1 is not set to 1 4 If no error is found when the received parity bit is checked the receive operation is judged to have been completed normally and the RDRF bit in SCSS...

Page 742: ...ich an error signal indicating an error is received 3 If an error signal is not sent back from the receiving side the FER ERS bit in SCSSR1 is not set 4 If an error signal is not sent back from the receiving side transmission of one frame including a retransfer is judged to have been completed and the TEND bit in SCSSR1 is set to 1 If the TIE bit in SCSCR1 is enabled at this time a TXI interrupt r...

Page 743: ... Write 0 to the CKE0 bit in SCSCR1 to stop the clock 4 Wait for one serial clock cycle During this period the duty cycle is preserved and clock output is fixed at the specified level 5 Write H 00 to the serial mode register SCSMR1 and smart card mode register SCSMR1 6 Make the transition to the standby state Returning from Standby Mode to Smart Card Interface Mode 7 Clear the standby state 8 Set t...

Page 744: ...al state is port input and high impedance Use pull up or pull down resistors to fix the potential 2 Fix at the output specified by the CKE1 bit in the serial control register SCSCR1 3 Set the serial mode register SCSMR1 and smart card mode register SCSCMR1 and switch to smart card mode operation 4 Set the CKE0 bit in SCSCR1 to 1 to start clock output ...

Page 745: ...Rev 3 0 04 02 page 706 of 1064 ...

Page 746: ... when in PCI enabled mode The features of the SCI I O port are as follows Data can be output when the I O port is designated for output and SCI enabling has not been set This allows break function transmission The RxD pin value can be read at all times allowing break state detection SCK pin control is possible when the I O port is designated for output and SCI enabling has not been set The SCK pin...

Page 747: ... Data input strobe D Q C 0 1 0 1 MPX MPX MPX PTIRENn BCK C Q D Pull up resistor Port 15 input output AD15 to Port 0 input output AD0 ADn output data Internal bus Interrupt controller PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output PTIRENn 0 Interrupt input disabled 1 Interrupt input enabled Figure 18 1 16 Bit Port A ...

Page 748: ...PUP PORTEN ADnDIR PBnIO 0 1 PDTRW BCK D Q C 0 1 0 1 BCK C Q D MPX MPX MPX Data input strobe Pull up resistor Port 31 input output AD31 to Port 16 input output AD16 ADn output data Internal bus PORTEN 0 Port not available 1 Port available PBnPuP 0 Pull up 1 Pull up off DnDIR 0 Input 1 Output PBnIO 0 Input 1 Output Figure 18 2 16 Bit Port B ...

Page 749: ...O C R Q D SPB1DT C SPTRR Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SCK SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C bit in SCSMR1 Figure 18 3 SCK Pin ...

Page 750: ...ernal data bus SPTRW SCI R Q D SPB0IO C Reset SPTRW R Q D SPB0DT C TxD Transmit enable signal Serial transmit data SPTRW Write to SPTR Figure 18 4 TxD Pin Internal data bus SCI RxD SPTRR Serial receive data SPTRR Read SPTR Figure 18 5 RxD Pin ...

Page 751: ...rnal data bus SPTRW Mode setting register SCIF R Q D SPB2IO C Reset SPTRW R Q D SPB2DT C MD1 TxD2 SPTRW Write to SPTR Transmit enable signal Serial transmit data Figure 18 6 MD1 TxD2 Pin Internal data bus Mode setting register SCIF MD2 RxD2 SPTRR Serial receive data SPTRR Read SPTR Figure 18 7 MD2 RxD2 Pin ...

Page 752: ...t enable signal Serial clock output signal Serial clock input signal Clock input enable signal MD0 SCK2 Mode setting register SPTRW Write to SPTR SPTRR Read SPTR Note Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2 Figure 18 8 MD0 SCK2 Pin ...

Page 753: ...IF R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C MD7 CTS2 Mode setting register SPTRW Write to SPTR SPTRR Read SPTR Note MCE bit in SCFCR2 signal that designates modem control as the CTS2 pin function Modem control enable signal CTS2 signal Figure 18 9 MD7 CTS2 Pin ...

Page 754: ...ignal Figure 18 10 MD8 RTS2 Pin 18 1 3 Pin Configuration Table 18 1 shows the 32 bit general purpose I O port pin configuration Table 18 1 32 Bit General Purpose I O Port Pins Pin Name Signal I O Function Port 31 pin AD31 PORT31 I O I O port Port 30 pin AD30 PORT30 I O I O port Port 29 pin AD29 PORT29 I O I O port Port 28 pin AD28 PORT28 I O I O port Port 27 pin AD27 PORT27 I O I O port Port 26 pi...

Page 755: ...12 pin AD12 PORT12 I O I O port GPIO interrupt Port 11 pin AD11 PORT11 I O I O port GPIO interrupt Port 10 pin AD10 PORT10 I O I O port GPIO interrupt Port 9 pin AD9 PORT9 I O I O port GPIO interrupt Port 8 pin AD8 PORT8 I O I O port GPIO interrupt Port 7 pin AD7 PORT7 I O I O port GPIO interrupt Port 6 pin AD6 PORT6 I O I O port GPIO interrupt Port 5 pin AD5 PORT5 I O I O port GPIO interrupt Port...

Page 756: ...e SCI s SCSPTR1 register Table 18 3 shows the SCIF I O port pin configuration Table 18 3 SCIF I O Port Pins Pin Name Abbreviation I O Function Serial clock pin MD0 SCK2 I O Clock input output Receive data pin MD2 RxD2 Input Receive data input Transmit data pin MD1 TxD2 Output Transmit data output Modem control pin MD7 I O Transmission enabled Modem control pin MD8 I O Transmission request Note The...

Page 757: ...A PCTRA R W H 00000000 H FF80002C H 1F80002C 32 Port data register A PDTRA R W Undefined H FF800030 H 1F800030 16 Port control register B PCTRB R W H 00000000 H FF800040 H 1F800040 32 Port data register B PDTRB R W Undefined H FF800044 H 1F800044 16 GPIO interrupt control register GPIOIC R W H 00000000 H FF800048 H 1F800048 16 Serial port register SCSPTR1 R W Undefined H FFE0001C H 1FE0001C 8 Seri...

Page 758: ...IO PB12PUP PB12IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 PB7PUP PB7IO PB6PUP PB6IO PB5PUP PB5IO PB4PUP PB4IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PB...

Page 759: ...itten to the PDTRA register is read PDTR is not initialized by a power on or manual reset or in standby mode and retains its contents Bit 15 14 13 12 11 10 9 8 PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT PB8DT Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value R W R W R W R W R W R W R W R W R W 18 2 3 Port Contro...

Page 760: ...8IO PB17PUP PB17IO PB16PUP PB16IO Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 2n 1 n 0 15 Port Pull Up Control PBnPUP Specifies whether each bit in the 16 bit port B is to be pulled up with a built in resistor Pull up is automatically turned off for a port pin set to output by bit PBnIO Bit 2n 1 PBnPUP Description 0 Bit m m 16 31 of 16 bit port B is pulled up Initial valu...

Page 761: ...Bit 15 14 13 12 11 10 9 8 PB31DT PB30DT PB29DT PB28DT PB27DT PB26DT PB25DT PB24DT Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PB23DT PB22DT PB21DT PB20DT PB19DT PB18DT PB17DT PB16DT Initial value R W R W R W R W R W R W R W R W R W 18 2 5 GPIO Interrupt Control Register GPIOIC The GPIO interrupt control register GPIOIC is a 16 bit readable writable register that performs ...

Page 762: ...PB1IO SPB1DT SPB0IO SPB0DT Initial value 0 0 0 0 0 0 R W R W R W R W R W R W The serial port register SCSPTR1 is an 8 bit readable writable register that controls input output and data for the port pins multiplexed with the serial communication interface SCI pins Input data can be read from the RxD pin output data written to the TxD pin and breaks in serial transmission reception controlled by mea...

Page 763: ...reset is undefined Bit 2 SPB1DT Description 0 Input output data is low level 1 Input output data is high level Bit 1 Serial Port Break I O SPB0IO Specifies the serial port TxD pin output condition When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit the TE bit in SCSCR1 should be cleared to 0 Bit 1 SPB0IO Description 0 SPB0DT bit value is not output to ...

Page 764: ...erformed by means of bits 3 and 2 pin data reading and output data writing can be performed by means of bits 5 and 4 and pin data reading and output data writing by means of bits 7 and 6 SCSPTR2 can be read or written to by the CPU at all times All SCSPTR2 bits except bits 6 4 2 and 0 are initialized to 0 by a power on reset or manual reset the value of bits 6 4 2 and 0 is undefined SCSPTR2 is not...

Page 765: ...e serial port pin input output data Input or output is specified by the CTSIO pin see the description of bit 5 CTSIO for details When the pin is designated as an output the value of the CTSDT bit is output to the pin The pin value is read from the CTSDT bit regardless of the value of the CTSIO bit The initial value of this bit after a power on reset or manual reset is undefined Bit 4 CTSDT Descrip...

Page 766: ...Description 0 SPB2DT bit value is not output to the TxD2 pin Initial value 1 SPB2DT bit value is output to the TxD2 pin Bit 0 Serial Port Break Data SPB2DT Specifies the serial port RxD2 pin input data and TxD2 pin output data The TxD2 pin output condition is specified by the SPB2IO bit see the description of bit 1 SPB2IO for details When the TxD2 pin is designated as an output the value of the SP...

Page 767: ...Rev 3 0 04 02 page 728 of 1064 ...

Page 768: ...rupt priority levels can be set By setting the five interrupt priority registers the priorities of on chip peripheral module interrupts can be selected from 15 levels for different request sources NMI noise canceler function The NMI input level bit indicates the NMI pin state The pin state can be checked by reading this bit in the interrupt exception handler enabling it to be used as a noise cance...

Page 769: ...ICR Interrupt control register IPRA IPRD Interrupt priority registers A D INTPRI00 Interrupt priority register 00 SR Status register NMI Input control IRL3 IRL0 TMU RTC SCI SCIF WDT REF DMAC H UDI Priority identifier 4 4 Interrupt request Com parator Bus interface Internal bus ICR IPRA IPRD INTPRI00 Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt...

Page 770: ... R W 2 H FFD00000 H 1FD00000 16 Interrupt priority register A IPRA R W H 0000 H FFD00004 H 1FD00004 16 Interrupt priority register B IPRB R W H 0000 H FFD00008 H 1FD00008 16 Interrupt priority register C IPRC R W H 0000 H FFD0000C H 1FD0000C 16 Interrupt priority register D IPRD R W H DA74 H FFD00010 H 1FD00010 16 Interrupt priority register 00 INTPRI00 R W H 00000000 H FE080000 H 1E080000 32 Inte...

Page 771: ...in the status register in the CPU is set to 1 In sleep or standby mode the interrupt is accepted even if the BL bit is set to 1 A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1 Input from the NMI pin is edge detected The NMI edge select bit NMIE in the interrupt control register ICR is used to select either rising or falling edge When the NMIE bit in the...

Page 772: ...evel is the level indicated by pins An value of 0 0000 indicates the highest level interrupt request interrupt priority level 15 A value of 15 1111 indicates no interrupt request interrupt priority level 0 Interrupt requests Priority encoder to 4 SH7751 Series to Figure 19 2 Example of IRL Interrupt Connection ...

Page 773: ...lation feature is built in and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles so that no transient level on the pin change is detected In standby mode as the bus clock is stopped noise cancellation is performed using the 32 768 kHz clock for the RTC instead When the RTC is not used therefore interruption by means o...

Page 774: ... SR are not affected by on chip peripheral module interrupt handling On chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register SR is set to 1 To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated first read the on chip peripheral register containing the releva...

Page 775: ...ified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D IPRA IPRD and interrupt priority register 00 INTPRI00 The order of priority of the on chip peripheral modules is set to 0 by a reset When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously they are handled according to the default pri...

Page 776: ...220 14 2 H 240 13 3 H 260 12 4 H 280 11 5 H 2A0 10 6 H 2C0 9 7 H 2E0 8 8 H 300 7 9 H 320 6 A H 340 5 B H 360 4 C H 380 3 D H 3A0 2 E H 3C0 1 IRL0 H 240 15 0 13 IPRD 15 12 IRL1 H 2A0 15 0 10 IPRD 11 8 IRL2 H 300 15 0 7 IPRD 7 4 IRL3 H 360 15 0 4 IPRD 3 0 H UDI H UDI H 600 15 0 0 IPRC 3 0 GPIO GPIOI H 620 15 0 0 IPRC 15 12 DMAC DMTE0 H 640 15 0 0 IPRC 11 8 High DMTE1 H 660 DMTE2 H 680 DMTE3 H 6A0 DM...

Page 777: ...INTPRI00 7 4 Low TMU3 TUNI3 H B00 15 0 0 INTPRI00 11 8 TMU4 TUNI4 H B80 15 0 0 INTPRI00 15 12 TMU0 TUNI0 H 400 15 0 0 IPRA 15 12 TMU1 TUNI1 H 420 15 0 0 IPRA 11 8 TMU2 TUNI2 H 440 15 0 0 IPRA 7 4 High TICPI2 H 460 Low RTC ATI H 480 15 0 0 IPRA 3 0 PRI H 4A0 CUI H 4C0 High Low SCI ERI H 4E0 15 0 0 IPRB 7 4 High RXI H 500 TXI H 520 TEI H 540 Low SCIF ERI H 700 15 0 0 IPRC 7 4 High RXI H 720 BRI H 74...

Page 778: ...CIERR PCIC error interrupt PCIPWDWN PCIC power down request interrupt PCIPWON PCIC power ON request interrupt PCIDMA0 to 3 PCIC DMA transfer end interrupts 19 3 Register Descriptions 19 3 1 Interrupt Priority Registers A to D IPRA IPRD Interrupt priority registers A to D IPRA IPRD are 16 bit readable writable registers that set priority levels from 0 to 15 for on chip peripheral module interrupts ...

Page 779: ...h unit in the bus state controller BSC See section 13 Bus State Controller BSC for details 2 Reserved bits These bits are always read as 0 and should always be written with 0 As shown in table 19 5 four on chip peripheral modules are assigned to each register Interrupt priority levels are established by setting a value from H F 1111 to H 0 0000 in each of the four bit groups 15 12 11 8 7 4 and 3 0...

Page 780: ...espective of the CPU s SR BL bit Bit 14 MAI Description 0 Interrupts enabled even while NMI pin is low Initial value 1 Interrupts disabled while NMI pin is low Note NMI interrupts are accepted in normal operation and in sleep mode In standby mode all interrupts are masked and standby is not cleared while the NMI pin is low Bit 9 NMI Block Mode NMIB Specifies whether an NMI request is to be held pe...

Page 781: ... independent interrupt requests level sense IRQ mode Bits 13 to 10 and 6 to 0 Reserved These bits are always read as 0 and should only be written with 0 19 3 3 Interrupt Priority Level Settting Register 00 INTPRI00 The interrupt priority level setting register INTPRI00 sets the order of priority levels 15 to 0 of the internal peripheral module interrupts The INTPRI00 register is a 32 bit read writ...

Page 782: ...ed These bits are always read as 0 and should only be written with 0 19 3 4 Interrupt Factor Register 00 INTREQ00 The interrupt factor register 00 INTREQ00 shows which interrupt have been requested of the INTC Even when the interrupts are masked with INTPRI00 and INTMSK00 the bits in this register are not affected INTREQ00 is a 32 bit read only register Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0...

Page 783: ...INTMSKCLR00 register The values in INTMSK00 do not change if you write 0 to it Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 1 1 R W R R R R R R W R W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Interrupt Masks These bits indicate the existence of an interrupt request corresponding to each bit For the correspondence between bits and interrupt...

Page 784: ...0 29 11 10 9 8 Initial value R W W W W W W W W Bit 7 6 5 4 3 2 1 0 Initial value R W W W W W W W W W Bits 31 to 0 Interrupt Mask Clear These bits indicate the existence of an interrupt request corresponding to each bit For the correspondence between bits and interrupt sources see section 19 3 7 INTREQ00 INTMSK00 and INTMSKCLR00 Bit Allocation Bits 31 to 0 Description 0 Do not change corresponding ...

Page 785: ...ng shows the relationship between individual bits in the register and interrupt factors Table 19 7 Bit Allocation Bit No Module Interrupt 31 to 10 Reserved Reserved 9 TMU TUNI4 8 TMU TUNI3 7 PCI PCIERR 6 PCI PCIPWDWN 5 PCI PCIPWON 4 PCI PCIDMA0 3 PCI PCIDMA1 2 PCI PCIDMA2 1 PCI PCIDMA3 0 PCI PCISERR ...

Page 786: ... between instructions 5 The interrupt source code is set in the interrupt event register INTEVT 6 The status register SR and program counter PC are saved to SSR and SPC respectively 7 The block bit BL mode bit MD and register bank bit RB in SR are set to 1 8 The CPU jumps to the start address of the interrupt handler the sum of the value set in the vector base register VBR and H 00000600 The inter...

Page 787: ...e in INTEVT Set BL MD RB bits in SR to 1 Branch to exception handler Interrupt generated BL bit in SR 0 or sleep or standby mode NMI Level 14 interrupt Level 1 interrupt I3 I0 level 13 or lower I3 I0 level 0 Yes Level 15 interrupt I3 I0 level 14 or lower Note I3 I0 Interrupt mask bits in status register SR NMIB in ICR 1 and NMI Figure 19 3 Interrupt Operation Flowchart ...

Page 788: ... RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 This enables the interrupt response time to be shortened for urgent processing 19 4 3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register it is possible to mask interrupts while the NMI pin is low irrespective...

Page 789: ... SR mask bit comparison 1Icyc 4Bcyc 1Icyc 7Bcyc 1Icyc 2Bcyc Wait time until end of sequence being executed by CPU S 1 0 Icyc S 1 0 Icyc S 1 0 Icyc Time from interrupt exception handling save of SR and PC until fetch of first instruction of exception handler is started 4 Icyc 4 Icyc 4 Icyc Total 5Icyc 4Bcyc S 1 Icyc 5Icyc 7Bcyc S 1 Icyc 5Icyc 2Bcyc S 1 Icyc Minimum case 13Icyc 19Icyc 9Icyc When Icy...

Page 790: ...features Two break channels A and B User break interrupts can be generated on independent conditions for channels A and B or on sequential conditions sequential break setting channel A channel B The following can be set as break compare conditions Address selection of 32 bit virtual address and ASID for comparison Address All bits compared lower 10 bits masked lower 12 bits masked lower 16 bits ma...

Page 791: ...RA BBRB BARB BASRB BAMRB BDRB BDMRB BRCR Control User break trap request BBRA Break bus cycle register A BARA Break address register A BASRA Break ASID register A BAMRA Break address mask register A BBRB Break bus cycle register B BARB Break address register B BASRB Break ASID register B BAMRB Break address mask register B BDRB Break data register B BDMRB Break data mask register B BRCR Break cont...

Page 792: ... Undefined H FF000014 H 1F000014 8 Break address register B BARB R W Undefined H FF20000C H 1F20000C 32 Break address mask register B BAMRB R W Undefined H FF200010 H 1F200010 8 Break bus cycle register B BBRB R W H 0000 H FF200014 H 1F200014 16 Break ASID register B BASRB R W Undefined H FF000018 H 1F000018 8 Break data register B BDRB R W Undefined H FF200018 H 1F200018 32 Break data mask regist...

Page 793: ...on When a UBC register is updated use either of the following methods to make the updated value valid 1 Execute an RTE instruction after the memory store instruction that updated the register The updated value will be valid from the RTE instruction jump destination onward 2 Execute instructions requiring 5 states for execution after the memory store instruction that updated the register As the SH7...

Page 794: ...5 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Break address register A BARA is a 32 bit readable writable register that specifies the virtual address used in the channel A break conditions BARA is not initialized by a power on re...

Page 795: ...4 Break Address Mask Register A BAMRA Bit 7 6 5 4 3 2 1 0 BAMA2 BASMA BAMA1 BAMA0 Initial value 0 0 0 0 R W R R R R R W R W R W R W Note Undefined Break address mask register A BAMRA is an 8 bit readable writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA BAMRA is not initialized by a power on reset or manual reset Bits 7 to...

Page 796: ...ed in break conditions 1 Lower 20 bits of BARA are masked and not included in break conditions 1 Reserved cannot be set Note Don t care 20 2 5 Break Bus Cycle Register A BBRA Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Break bus cycle register A BBR...

Page 797: ... or write cycle is used as the bus cycle in the channel A break conditions Bit 3 RWA1 Bit 2 RWA0 Description 0 0 Condition comparison is not performed Initial value 1 Read cycle is used as break condition 1 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition Bits 6 1 and 0 Operand Size Select A SZA2 SZA0 These bits select the operand size of the bus cycl...

Page 798: ... 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BD...

Page 799: ...BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Break data mask register B BDMRB is a ...

Page 800: ...er BRCR Bit 15 14 13 12 11 10 9 8 CMFA CMFB PCBA Initial value 0 0 0 0 0 0 0 R W R W R W R R R R W R R Bit 7 6 5 4 3 2 1 0 DBEB PCBB SEQ UBDE Initial value 0 0 0 0 0 R W R W R W R R R W R R R W Note Undefined The break control register BRCR is a 16 bit readable writable register that specifies 1 whether channels A and B are to be used as two independent channels or in a sequential condition 2 whet...

Page 801: ...s read as 0 and should only be written with 0 Bit 10 Instruction Access Break Select A PCBA Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed This bit is not initialized by a power on reset or manual reset Bit 10 PCBA Description 0 Channel A PC break is effected before instruction execution 1 Channel A PC break is effected af...

Page 802: ...nd B comparisons are performed as sequential conditions channel A channel B Bits 2 and 1 Reserved These bits are always read as 0 and should only be written with 0 Bit 0 User Break Debug Enable UBDE Specifies whether the user break debug function see section 20 4 User Break Debug Support Function is to be used Bit 0 UBDE Description 0 User break debug function is not used Initial value 1 User brea...

Page 803: ... instruction s after as a measure of the distance between two instructions is defined as follows A branch is counted as an interval of two instructions Example of sequence of instructions with no branch 100 Instruction A 0 instructions after instruction A 102 Instruction B 1 instruction after instruction A 104 Instruction C 2 instructions after instruction A 106 Instruction D 3 instructions after ...

Page 804: ...egister or the break control register is in the initial state after a reset a break may be generated inadvertently 3 The operation when a break condition is satisfied depends on the BL bit in the CPU s SR register When the BL bit is 0 exception handling is started and the condition match flag CMFA CMFB for the respective channel is set for the matched condition When the BL bit is 1 the condition m...

Page 805: ...rried out first The instruction TLB exception handling is performed when the instruction is re executed see section 5 4 Exception Types and Priorities Also since a delayed branch instruction and the delay slot instruction are executed as a single instruction if a pre execution break is specified for a delay slot instruction the break will be effected before execution of the delayed branch instruct...

Page 806: ...In this case break data register B BDRB and break data mask register B BDMRB settings are necessary in addition to the address condition A user break interrupt is generated when all three conditions address ASID and data are matched When a quadword access occurs the 64 bit access data is divided into an upper 32 bits and lower 32 bits and interpreted as two 32 bit data units A break is generated i...

Page 807: ...uction access pre execution is set as a break condition the program counter PC value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred In this case a user break interrupt is generated and the fetched instruction is not executed 2 When instruction access post execution is set as a break condition the program counter PC value ...

Page 808: ...rrespective of the existence of exception 1 The program counter value saved is the address of the first instruction for which execution is suppressed Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register EXPEVT INTEVT is not guaranteed However if exception 2 is from a source not synchronized with an instruction external interr...

Page 809: ...execution instruction access break for the SLEEP instruction 2 Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction 3 The value of the BL bit referenced in a user break exception depends on the break setting as follows a Pre execution instruction access break The BL bit value before the executed instruction is referenced b Post execution instruction a...

Page 810: ...ak state is initialized by a channel B condition match For example A A B user break generated B no break generated 7 In the event of contention between a re execution type exception and a post execution break in a multistep instruction the re execution type exception is generated In this case the CMF bit may or may not be set to 1 when the break condition occurs 8 A post execution break is classif...

Page 811: ... VBR vector offset Exception handling routine Execute RTE instruction PC SPC SR SSR SGR R15 EXPEVT H 160 TRA TRAPA imm PC DBR Debug program R15 SGR STC instruction Reset exception BRCR UBDE 1 user break exception End of exception operations INTEVT interrupt code EXPEVT exception code Yes No No Yes Hardware operation Figure 20 2 User Break Debug Support Function Flowchart ...

Page 812: ...H 000083FE with ASID H 70 Register settings BASRA H 80 BARA H 00037226 BAMRA H 00 BBRA H 0016 BASRB H 70 BARB H 0003722E BAMRB H 00 BBRB H 0016 BDRB H 00000000 BDMRB H 00000000 BRCR H 0008 Conditions set Channel A channel B sequential mode Channel A ASID H 80 address H 00037226 address mask H 00 Bus cycle instruction access pre instruction execution read word Channel B ASID H 70 address H 0003722E...

Page 813: ...BASRB H 70 BARB H 000ABCDE BAMRB H 02 BBRB H 002A BDRB H 0000A512 BDMRB H 00000000 BRCR H 0080 Conditions set Independent channel A channel B mode Channel A ASID H 80 address H 00123456 address mask H 00 Bus cycle operand access read operand size not included in conditions Channel B ASID H 70 address H 000ABCDE address mask H 02 Data H 0000A512 data mask H 00000000 Bus cycle operand access write w...

Page 814: ...n exception or interrupt occurs while performing steps 1 to 5 you do not change the values of these registers in the exception handling routine Do not read or write the following registers while the user break controller clock is stopped BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB and BRCR If these registers are read or written the value cannot be guaranteed 20 6 2 Cancelling the User Break Control...

Page 815: ...R1 2 Initialize BRCR to 0 mov l BRCR R1 mov w R0 R1 3 Dummy read BRCR mov w R1 R0 4 Read STBCR2 then set MSTP5 bit in the read data to 1 and write it back mov l STBCR2 R1 mov b R1 R0 or H 1 R0 mov b R0 R1 5 Twice dummy read STBCR2 mov b R1 R0 mov b R1 R0 Canceling user break controller stopped state 6 Read STBCR2 then clear MSTP5 bit in the read data to 0 and write it back mov l STBCR2 R1 mov b R1...

Page 816: ...SYNC AUDCK and AUDATA3 to AUDATA0 The pin functions and serial transfer protocol conform to the JTAG specifications 21 1 2 Block Diagram Figure 21 1 shows a block diagram of the H UDI The TAP test access port controller and control registers are reset independently of the chip reset pin by driving the pin low or setting TMS to 1 and applying TCK for at least five clock cycles The other circuits ar...

Page 817: ...IR SDDRH SDDRL SDBPR MUX TCK BRKACK TMS TDI TDO AUDSYNC AUDCK AUDATA3 0 SDINT Interrupt reset etc TAP controller Break control Decoder Shift register SDBSR Peripheral module bus Trace control Figure 21 1 Block Diagram of H UDI Circuit ...

Page 818: ...it when low must be driven low for a certain period when powering on regardless of whether or not JTAG is used This differs from the IEEE specification 2 3 Data input pin TDI Input The data input pin Data is sent to the H UDI circuit by changing this signal in synchronization with TCK Open 1 Data output pin TDO Output The data output pin Data is sent to the H UDI circuit by reading this signal in ...

Page 819: ...ept for SDBPR and SDBSR these registers are mapped in the control register space and can be referenced by the CPU Table 21 2 H UDI Registers CPU Side H UDI Side Name Abbre viation R W P4 Address Area 7 Address Access Size Initial Value 1 R W Access Size Initial Value 1 Instruction register SDIR R H FFF00000 H 1FF00000 16 H FFFF R W 32 H FFFFFFFD Fixed value 2 Data register H SDDR SDDRH R W H FFF00...

Page 820: ...ned if a reserved command is set in this register Bit 15 14 13 12 11 10 9 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R R R R R R R R Bits 15 to 8 Test Instruction Bits TI7 TI0 Bit 15 TI7 Bit 14 TI6 Bit 13 TI5 Bit 12 TI4 Bit 11 TI3 Bit 10 TI2 Bit 9 TI1 Bit 8 TI0 Description 0 0 0 0 0 0 0 0 EXTEST 0 0 0 0 ...

Page 821: ...W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Initial value R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W R W Note Undefined Bits 31 to 0 DR Data These bits store the SDDR value 21 2 3 Bypass Register SDBPR The bypass register SDBPR is a one bit register that cann...

Page 822: ...ized by or when in the Test Logic Reset state Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 INTREQ Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 15 to 1 Reserved These bits always read as 0 and should only be written with 0 Bit 0 Interrupt Request Bit INTREQ Shows the existence of an interrupt request from the H UDI interrupt command The...

Page 823: ...L 411 DRAK1 OUT 410 DRAK0 CTL 409 DRAK0 OUT 408 DACK1 CTL 407 DACK1 OUT 406 DACK0 CTL 405 DACK0 OUT 404 MD5 IN 403 MD5 CTL 402 MD5 OUT 401 MD4 IN 400 MD4 CTL 399 MD4 OUT 398 MD3 IN 397 MD3 CTL 396 MD3 OUT 395 AUDATA3 CTL 394 AUDATA3 OUT 393 AUDATA2 CTL 392 AUDATA2 OUT 391 AUDATA1 CTL 390 AUDATA1 OUT Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 824: ... IN 382 MD7 CTL 381 MD7 OUT 380 MD0 SCK2 IN 379 MD0 SCK2 CTL 378 MD0 SCK2 OUT 377 MD1 TXD2 IN 376 MD1 TXD2 CTL 375 MD1 TXD2 OUT 374 SCK IN 373 SCK CTL 372 SCK OUT 371 MD8 IN 370 MD8 CTL 369 MD8 OUT 368 TCLK IN 367 TCLK CTL 366 TCLK OUT 365 RXD IN 364 MD2 RXD2 IN 363 TXD IN 362 TXD CTL 361 TXD OUT 360 IN Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW...

Page 825: ...IN 352 IN 351 IN 350 AD0 IN 349 AD0 CTL 348 AD0 OUT 347 AD1 IN 346 AD1 CTL 345 AD1 OUT 344 AD2 IN 343 AD2 CTL 342 AD2 OUT 341 AD3 IN 340 AD3 CTL 339 AD3 OUT 338 AD4 IN 337 AD4 CTL 336 AD4 OUT 335 AD5 IN 334 AD5 CTL 333 AD5 OUT 332 AD6 IN 331 AD6 CTL 330 AD6 OUT Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 826: ... AD8 CTL 321 AD8 OUT 320 AD9 IN 319 AD9 CTL 318 AD9 OUT 317 AD10 IN 316 AD10 CTL 315 AD10 OUT 314 AD11 IN 313 AD11 CTL 312 AD11 OUT 311 AD12 IN 310 AD12 CTL 309 AD12 OUT 308 AD13 IN 307 AD13 CTL 306 AD13 OUT 305 AD14 IN 304 AD14 CTL 303 AD14 OUT 302 AD15 IN 301 AD15 CTL 300 AD15 OUT Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 827: ... OUT 296 PAR IN 295 PAR CTL 294 PAR OUT 293 IN 292 CTL 291 OUT 290 IN 289 CTL 288 OUT 287 IN 286 CTL 285 OUT 284 IN 283 CTL 282 OUT 281 IN 280 CTL 279 OUT 278 IN 277 CTL 276 OUT 275 IN 274 CTL 273 OUT 272 C IN 271 C CTL 270 C OUT Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 828: ...18 IN 262 AD18 CTL 261 AD18 OUT 260 AD19 IN 259 AD19 CTL 258 AD19 OUT 257 AD20 IN 256 AD20 CTL 255 AD20 OUT 254 AD21 IN 253 AD21 CTL 252 AD21 OUT 251 AD22 IN 250 AD22 CTL 249 AD22 OUT 248 AD23 IN 247 AD23 CTL 246 AD23 OUT 245 C IN 244 C CTL 243 C OUT 242 AD24 IN 241 AD24 CTL 240 AD24 OUT Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 829: ...D26 OUT 233 AD27 IN 232 AD27 CTL 231 AD27 OUT 230 AD28 IN 229 AD28 CTL 228 AD28 OUT 227 AD29 IN 226 AD29 CTL 225 AD29 OUT 224 AD30 IN 223 AD30 CTL 222 AD30 OUT 221 AD31 IN 220 AD31 CTL 219 AD31 OUT 218 IN 217 CTL 216 OUT 215 IN 214 CTL 213 OUT 212 CTL 211 OUT 210 PCICLK IN Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 830: ... IN 204 MD9 IN 203 MD9 CTL 202 MD9 OUT 201 MD10 IN 200 MD10 CTL 199 MD10 OUT 198 IN 197 CTL 196 OUT 195 CTL 194 OUT 193 CTL 192 OUT 191 CTL 190 OUT 189 IN 188 CTL 187 OUT 186 CTL 185 OUT 184 A25 CTL 183 A25 OUT 182 A24 CTL 181 A24 OUT 180 A23 CTL Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 831: ...73 A20 OUT 172 A19 CTL 171 A19 OUT 170 A18 CTL 169 A18 OUT 168 D31 IN 167 D31 CTL 166 D31 OUT 165 D30 IN 164 D30 CTL 163 D30 OUT 162 D29 IN 161 D29 CTL 160 D29 OUT 159 D28 IN 158 D28 CTL 157 D28 OUT 156 D27 IN 155 D27 CTL 154 D27 OUT 153 D26 IN 152 D26 CTL 151 D26 OUT 150 D25 IN Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 832: ... D23 CTL 142 D23 OUT 141 D22 IN 140 D22 CTL 139 D22 OUT 138 D21 IN 137 D21 CTL 136 D21 OUT 135 D20 IN 134 D20 CTL 133 D20 OUT 132 D19 IN 131 D19 CTL 130 D19 OUT 129 D18 IN 128 D18 CTL 127 D18 OUT 126 D17 IN 125 D17 CTL 124 D17 OUT 123 D16 IN 122 D16 CTL 121 D16 OUT 120 DQM3 CTL Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 833: ...16 CTL 113 A16 OUT 112 A15 CTL 111 A15 OUT 110 A14 CTL 109 A14 OUT 108 A13 CTL 107 A13 OUT 106 A12 CTL 105 A12 OUT 104 A11 CTL 103 A11 OUT 102 A10 CTL 101 A10 OUT 100 A9 CTL 99 A9 OUT 98 A8 CTL 97 A8 OUT 96 A7 CTL 95 A7 OUT 94 A6 CTL 93 A6 OUT 92 A5 CTL 91 A5 OUT 90 A4 CTL Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 834: ...5 A2 OUT 84 A1 CTL 83 A1 OUT 82 A0 CTL 81 A0 OUT 80 CTL 79 OUT 78 CTL 77 OUT 76 CTL 75 OUT 74 CKE CTL 73 CKE OUT 72 CTL 71 OUT 70 RD CTL 69 RD OUT 68 DQM1 CTL 67 DQM1 OUT 66 DQM0 CTL 65 DQM0 OUT 64 D15 IN 63 D15 CTL 62 D15 OUT 61 D14 IN 60 D14 CTL Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 835: ...2 IN 54 D12 CTL 53 D12 OUT 52 D11 IN 51 D11 CTL 50 D11 OUT 49 D10 IN 48 D10 CTL 47 D10 OUT 46 D9 IN 45 D9 CTL 44 D9 OUT 43 D8 IN 42 D8 CTL 41 D8 OUT 40 D7 IN 39 D7 CTL 38 D7 OUT 37 D6 IN 36 D6 CTL 35 D6 OUT 34 D5 IN 33 D5 CTL 32 D5 OUT 31 D4 IN 30 D4 CTL Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 836: ... IN 27 D3 CTL 26 D3 OUT 25 D2 IN 24 D2 CTL 23 D2 OUT 22 D1 IN 21 D1 CTL 20 D1 OUT 19 D0 IN 18 D0 CTL 17 D0 OUT 16 CTL 15 OUT 14 CTL 13 OUT 12 CTL 11 OUT 10 CTL 9 OUT 8 CTL 7 OUT 6 CTL 5 OUT 4 CTL 3 OUT 2 CTL 1 OUT to TDO Note CTL is a low active signal The relevant pin is driven to the OUT state when CTL is set LOW ...

Page 837: ...ing edge The TDO value changes at the falling edge of TCK When not in the Shift DR or Shift IR state TDO is in the high impedance state In a transition to 0 a transition is made to the Test Logic Reset state asynchronously with respect to TCK 1 0 0 0 Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Test Logic Reset 0 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 Select IR Scan...

Page 838: ...generates an interrupt by setting a command value in SDIR from the H UDI The H UDI interrupt is of general exception interrupt operation type with a branch to an address based on VBR and return effected by means of an RTE instruction The exception code stored in control register INTEVT in this case is H 600 The priority of the H UDI interrupt can be controlled with bits 3 to 0 of control register ...

Page 839: ...ower on oscillation stabilization time has elapsed The clock signal need not be supplied to the EXTAL pin after tOSC1 has elapsed For details on tOSC1 the power on oscillation stabilization time see section 23 Electrical Characteristics 6 When the SH7751 is in bypass mode the bypass register SDBPR is not fixed in the Capture DR state It is cleared to 0 in the SH7751R 21 4 Usage Notes 1 SDIR Comman...

Page 840: ...vailable Four DMA transfer channels Six 32 bit x 16 longword internal FIFO one for target reading one for target writing and four for DMA transfer Asynchronous operation of BSC bus clock and PCI bus clock available and CKIO can be used as PCI bus clock SRAM DRAM SDRAM and MPX 2 can be used as external memory for PCI bus data transfers 32 bit or 16 bit memory data bus for data transfers with PCI bu...

Page 841: ... enable signals 3 0 is possible when accepting a configuration access The SH7751 specifications however define the values of 3 0 as being ignored on the acceptance of a configuration access and that access is in longword DWORD units only 2 MPX is only supported by the SH7751R and is not supported by the SH7751 ...

Page 842: ...erface Internal peripheral module bus interface Local register FIFO 32B 2 sides 6 Data transfer control Local register Bus request Acknowledge Local register PCIC bus controller PCI clock 33 66 MHz PCICLK Local bus Feedback input clock from CKIO Local bus clock Bφ cycle Bcyc Interrupts PCIC module Internal peripheral module bus Peripheral bus Figure 22 1 PCIC Block Diagram ...

Page 843: ... C to C C 3 0 Command byte enable t s O I O I Low level output at reset 5 PAR PAR Parity t s I O I O I O I O Low level output at reset 6 Bus cycle s t s Yes O I O I 7 Initiator ready s t s Yes O I O I 8 Target ready s t s Yes I O I O 9 Transaction stop s t s Yes I O I O 10 Exclusive access control s t s Yes O I O I 11 Device select s t s Yes I O I O Bus request host function t s Yes I I 12 Bus gra...

Page 844: ...1 Terminal provided with a pull up resistor 2 The values of external pins are sampled in a power on reset by means of the pin 3 This must be fixed at Low when not in used 22 1 4 Register Configuration The PCIC has the PCI configuration registers and PCI control registers shown in table 22 2 22 3 and 22 4 Also the PCI bus address space is allocated to the internal bus for the peripheral modules mak...

Page 845: ...ration register 8 PCICONF8 R R H 00000000 H 20 H FE200020 H 1E200020 32 PCI configuration register 9 PCICONF9 R R H 00000000 H 24 H FE200024 H 1E200024 32 PCI configuration register 10 PCICONF10 R R H 00000000 H 28 H FE200028 H 1E200028 32 PCI configuration register 11 PCICONF11 R R W H xxxxxxxx H 2C H FE20002C H 1E20002C 32 PCI configuration register 12 PCICONF12 R R H 00000000 H 30 H FE200030 H ...

Page 846: ...cal address area 1 Base address local address area 1 R W R W H 1C H FE20001C H 1E20001C Reserved Reserved Reserved Reserved R R H 20 H FE200020 H 1E200020 Reserved Reserved Reserved Reserved R R H 24 H FE200024 H 1E200024 Reserved Reserved Reserved Reserved R R H 28 H FE200028 H 1E200028 Reserved Reserved Reserved Reserved R R H 2C H FE20002C H 1E20002C Subsystem ID Subsystem ID Subsystem vendor I...

Page 847: ...0011C H 1E20011C 32 Error command data register for PCI PCICLR R R H 0000000x H 120 H 20 H FE200120 H 1E200120 32 Reserved H 00000000 H 124 to H 12C H 24 to H 2C H FE200124 to H FE20012C H 1E200124 to H 1E20012C 32 PCI arbiter interrupt register PCIAINT R W R W H 00000000 H 130 H 30 H FE200130 H 1E200130 32 PCI arbiter interrupt mask register PCIAINTM R W R W H 00000000 H 134 H 34 H FE200134 H 1E2...

Page 848: ...count register 2 for PCI PCIDTC2 R W R W H 00000000 H 1A8 H A8 H FE2001A8 H 1E2001A8 32 DMA control register 2 for PCI PCIDCR2 R W R W H 00000000 H 1AC H AC H FE2001AC H 1E2001AC 32 DMA transfer PCI address register 3 for PCI PCIDPA3 R W R W H 00000000 H 1B0 H B0 H FE2001B0 H 1E2001B0 32 DMA transfer local bus starting address register 3 for PCI PCIDLA3 R W R W H 00000000 H 1B4 H B4 H FE2001B4 H 1...

Page 849: ...7777777 H FE2001F0 H 1E2001F0 32 PCIC discrete memory control register PCIMCR R W H 00000000 H FE2001F4 H 1E2001F4 32 PCIC bus control register 3 1 PCIBCR3 R W H 00000001 H FE2001F8 H 1E2001F8 32 Reserved H 00000000 H FE2001FC H 1E2001FC 32 Port control register PCIPCTR R W H 00000000 H FE200200 H 1E200200 32 Port data register PCIPDTR R W H 00000000 H FE200204 H 1E200204 32 Reserved H 00000000 H ...

Page 850: ... VNDID11 VNDID10 VNDID9 VNDID8 Initial value 0 0 0 1 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 VNDID7 VNDID6 VNDID5 VNDID4 VNDID3 VNDID2 VNDID1 VNDID0 Initial value 0 1 0 1 0 1 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note These values differ between SH7751 and SH7751R Indicated with are for the SH7751R PCI configuration register 0 PCICONF0 is a 3...

Page 851: ...UDF 66M PM Initial value 1 0 0 1 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R W R W R R R R R Bit 15 14 13 12 11 10 9 8 PBBE SER Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R W PP Bus R W R R R R R R R R W Bit 7 6 5 4 3 2 1 0 WCC PER VPS MWIE SPC BUM MES IOS Initial value 1 0 0 0 0 0 0 0 PCI R W R W R W R R R R W R W R W PP Bus R W R W R W R R R R W R W R W Note Cleared by writing WC 1 W...

Page 852: ...on the device Bit 30 System Error Output Status SSE Indicates the assert operation of the PCIC Bit 30 SSE Description 0 Device not asserting Initial value 1 Device asserting Value retained until cleared Bit 29 Master abort receive status RMA Indicates the termination of transaction by master abort when the PCIC is operating as the master Bit 29 RMA Description 0 No transaction termination using bu...

Page 853: ...en the parity error response bit bit 6 is 1 Bit 24 DPD Description 0 Data parity not detected Initial value 1 Data parity occurred Bit 23 High Speed Back To Back Status FBBC Shows whether a high speed back to back transfer to a different target can be accepted when the PCIC is operating as a target Bit 23 FBBC Description 0 The target does not have a high speed back to back transaction function fo...

Page 854: ...n 0 Allows high speed back to back control only with same target Initial value 1 Allows high speed back to back control with different target Not supported Bit 8 Output Control SER Controls the output Bit 8 SER Description 0 output disabled Hi Z Initial value 1 output enabled Bit 7 Wait Cycle Control WCC Controls the address data stepping When WCC 1 address and data are output in master write oper...

Page 855: ... execute memory write and invalidate commands not supported Bit 3 Special Cycle Control SPC Shows whether special cycles are supported when the PCIC is operating as a target Bit 3 SPC Description 0 Ignore special cycle Initial value 1 Monitor special cycle not supported Bit 2 PCI Bus Master Control BUM Controls the bus master operation Bit 2 BUM Description 0 Disable bus master operation Initial v...

Page 856: ... W R W Bit 23 22 21 20 19 18 17 16 CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8 Initial value PCI R W R R R R R R R R PP Bus R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0 Initial value PCI R W R R R R R R R R PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 REVID7 REVID6 REVID5 REVID4 REVID3 REVI...

Page 857: ...ice designed prior to class code being defined H 01 High capacity storage controller H 02 Network controller H 03 Display controller H 04 Multimedia device H 05 Memory controller H 06 Bridge device H 07 Simple communication device H 08 Basic peripheral device H 09 Input device H 0A Docking station H 0B Processor H 0C Serial bus controller H 0D to H FE Reserved H FF Device not categorized in define...

Page 858: ...t 7 6 5 4 3 2 1 0 CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 3 PCICONF3 is a 32 bit read partial write register that includes the BIST function header type latency timer and cache line size PCI configuration registers stipulated in the PCI local bus specification The BIST fu...

Page 859: ...Initial value H 1 to H F Test failed not supported Bit 23 Multifunction Status HEAD7 Shows whether the device is a multi function unit or a single function unit Bit 23 HEAD7 Description 0 Single function device Initial value 1 Device has between 2 and 8 functions not supported Bits 22 to 16 Configuration Layout Type HEAD6 to 0 These bits indicate the layout type of the configuration register Bits ...

Page 860: ... 11 10 9 8 BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BASE7 BASE6 BASE5 BASE4 BASE3 BASE2 ASI Initial value 0 0 0 0 0 0 0 1 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note These bits are read only in the SH7751 and can be read from and written to i...

Page 861: ...on reset and software reset Always write to this register prior to executing I O transfers accessing the local registers in the PCIC to or from the PCIC from the PCI bus Bits 31 to 8 Base Address of the I O Space BASE 31 to 8 Sets the base address of the local registers I O space in the PCIC In the SH7751 bits 19 to 8 are fixed to H 000 in hardware Bits 7 to 2 Base Address of the I O Space BASE 7 ...

Page 862: ... R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 BASE07 BASE06 BASE05 BASE04 LA0PREF LA0TYPE1 LA0TYPE0 LA0ASI Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 5 PCICONF5 is a 32 bit read partial write register that accommodates the memory space base address PCI configuration register stipulated in the PCI local bus specifications Th...

Page 863: ...0 BASE0 31 to 20 These bits specify the base address of the local address space 0 SH7751 Series external bus space Bits 19 to 4 Base Address of the Memory Space 0 BASE0 19 to 4 Fixed at H 0000 in hardware Bit 3 Pre fetch Control LA0PREF Shows availability of prefetching of the local address space 0 Bit 3 LA0PREF Description 0 Prefetch disabled Initial value 1 Prefetch enabled not supported Bits 2 ...

Page 864: ...0 PCI R W R W R W R W R W R R R R PP Bus R W R W R W R W R W R R R R Bit 15 14 13 12 11 10 9 8 BASE115 BASE114 BASE113 BASE112 BASE111 BASE110 BASE19 BASE18 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 BASE17 BASE16 BASE15 BASE14 LA1PREF LA1TYPE1 LA1TYPE0 LA1ASI Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R ...

Page 865: ...0000_0011 4 MB Bits 31 to 22 b 0_1111_1111 256 MB Bits 31 to 28 b 1_1111_1111 512 MB Bits 31 to 29 The PCICONF6 register is initialized to H 00000000 at a power on reset and software reset Always write to this register prior to transferring data to or from the PCIC memory from the PCI bus Bits 31 to 20 Base Address of the Memory Space 1 BASE1 31 to 20 Specifies the base address of the local addres...

Page 866: ...width not supported 1 Reserved Bit 0 Address Space Indicator LA1ASI Shows whether the base address specified by this register is an I O space or memory space Bit 0 LA1ASI Description 0 Memory space Initial value 1 I O space 22 2 8 PCI Configuration Register 7 PCICONF7 to PCI Configuration Register 10 PCICONF10 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R ...

Page 867: ... SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 Initial value PCI R W R R R R R R R R PP Bus R W R W R W R W R W R W R W R W R W The PCI configuration register 11 PCICONF11 is a 32 bit read write register that accommodates the subsystem ID and subsystem vendor ID PCI configuration registers stipulated in the PCI local bus specifications The register contains the ID of the add in board that SH7751 Series is i...

Page 868: ... 12 PCICONF12 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bits 31 to 0 Reserved These bits are always read as 0 ...

Page 869: ...PP Bus R W R R R R R R R R The PCI configuration register 13 PCICONF13 is a 32 bit read only register that accommodates the extended function pointer PCI configuration register stipulated in the PCI power management specifications The address offset of the extended function is read from bits 7 to 0 All bits are fixed in hardware Bits 31 to 8 Reserved These bits are always read as 0 Bits 7 to 0 CAP...

Page 870: ... 14 PCICONF14 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bits 31 to 0 Reserved These bits are always read as 0 ...

Page 871: ... W PP Bus R W R W R W R W R W R W R W R W R W The PCI configuration register 15 PCICONF15 is a 32 bit read partial write register that accommodates the maximum latency minimum grant interrupt pin and interrupt line PCI configuration registers stipulated in the PCI local bus specifications The interrupt pins used by the SH7751 SH7751R are read from bits 15 to 8 Bits 7 to 0 indicate to which of the ...

Page 872: ...evice not supported Bits 15 to 8 Interrupt Pin Specification IPIN7 to 0 Bits 15 to 8 IPIN7 to 0 Description H 01 used Initial value H 02 used H 03 used H 04 used H 05 to H FF Reserved bits Bits 7 to 0 Interrupt Line Specification ILIN7 to 0 Specifies an interrupt line of a system to which interrupt output used by the PCIC is connected ...

Page 873: ... 0 0 1 PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI configuration register 16 PCICONF16 is a 32 bit read partial write register than accommodates the power management function PMC next item pointer and extended function ID power management registers stipulated in the PCI power management specifications PCICONF16 is valid only when the PCIC is functioning not as the host The power man...

Page 874: ...hese bits Bit 21 DSI Specifies whether bit device specific initialization is required Bit 20 Reserved This bit always returns 0 when read Always write 0 to this bit Bit 19 PME Clock PMECLK Not supported Specifies whether a clock is required for support Bits 18 to 16 Version VER2 to 0 Specify the version of power management specifications Bits 15 to 8 Next Item Pointer NIP7 to 0 Specify the offset ...

Page 875: ...WRST0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R W R W PP Bus R W R R R R R R R W R W The PCI configuration register 17 PCICONF17 is a 32 bit read partial write register that accommodates the power management control status PMCSR bridge compatible PMCSR extended PMCSR_BSE and data power management registers stipulated in the PCI power management specifications PCICONF17 is valid only when...

Page 876: ...it 15 PME Status PMEST Not supported Shows the status of the bit This bit is set when the signal is output Bits 14 and 13 Data Scale DTATSCL1 to 0 Not supported These bits specify the scaling value for the data field value Bits 12 to 9 Data Select DATASEL3 to 0 Not supported Select the value to be output to the data field Bit 8 Enable PMEEN Not supported Controls the signal output Bits 7 to 2 Rese...

Page 877: ...nitial value 0 0 0 0 0 0 0 PCI R W R R R R R R R PP Bus R W R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Note PCI configuration addresses H 48 to H FC are reserved Bits 31 to 0 Reserved These bits always return 0 when read ...

Page 878: ...by means of the pin The PCI control register PCICR is a 32 bit register that monitors the status of the mode pin at initialization and controls the basic operation of the PCIC Bits 5 MD10 and 4 MD9 are read only bits from the PP bus Other bits are read write bits Bits 9 TRDSGL and 8 BYTESWAP are read write bits from the PCI bus Other bits are read only In PCIC host operation a software reset can b...

Page 879: ... byte is swapped when the PCIC performs PIO transfer Bit 8 BYTESWAP Description 0 Send data as is Initial value 1 Swap data byte before sending Note For details refer to section 22 4 Endians Bit 7 PCI Signal Pull up PCIUP Controls the pull up resistance of the PCI signal Regarding the pins that are subject to pull up refer to Table 22 1 Regarding the pull up control provided when the MD9 MD10 or i...

Page 880: ...is 1 When 1 is written to this bit is asserted for 1 clock This bit always returns 0 when read Used when the PCIC is not the host If used when the PCIC is the host an assert interrupt is generated for the SH7751 Series Bit 3 SERR Description 0 pin at Hi Z Initial value 1 Assert Low output Bit 2 Output INTA Software control of valid only when PCIC is not host Bit 2 INTA Description 0 pin at Hi Z dr...

Page 881: ...gister 1 0 PCILSR 1 0 Bit 31 30 29 28 27 26 25 24 PLSR28 PLSR27 PLSR26 PLSR25 PLSR24 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 PLSR23 PLSR22 PLSR21 PLSR20 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R W R W R W R W R R R R Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R...

Page 882: ...20 For example to secure a 32MB space set the value H 01F00000 If you specify all zeros a 1MB space is reserved You can specify an address space up to 512MB Refer to Table 22 6 in section 22 2 6 PCI Configuration Register 5 PCICONF5 Bits 31 to 29 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bits 28 to 20 Capacities of the Local Address Spaces 0 1 PLSR28 t...

Page 883: ...l address spaces address space 0 and address space 1 supported when performing memory read memory write operations due to target transfers to the PCIC It is a 32 bit register that can be read and written from the PP bus and is read only from the PCI bus The PCILAR 1 0 register is initialized to H 00000000 at a power on reset and software reset The valid bits of the local address specified by this ...

Page 884: ...Bits 28 to 26 of the PCI local address register 0 select the local address area Bits 25 to 20 show the address within that area Bits 31 to 29 Reserved These bits always return 0 when read Always write 0 to these bits Bits 28 to 20 Local Address LAR28 to 20 Specify bits 28 to 20 of the starting address of the local address space Bits 19 to 0 Reserved These bits always return 0 when read Always writ...

Page 885: ... WC R WC R WC R WC R WC PP Bus R W R WC R WC R WC R WC R WC R WC R WC R WC Note WC Cleared by writing 1 Writing of 0 is ignored The PCI interrupt register PCIINT is a 32 bit register that saves the error source when an error occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus or when the PCIC is the PCI master or PCI target This register can be read from bo...

Page 886: ...empt a retry within the prescribed number of PCI bus clocks 2 15 detected only in the case of memory read operations Bit 8 Master Function Disable Error Interrupt MST_DIS Indicates that an attempt was made to conduct a master operation PIO transfer DMA transfer when bit 2 BUM of the PCICONF1 was set to 0 to prohibit bus master operations Bit 7 Address Parity Error Detection Interrupt ADRPERR Addre...

Page 887: ... R R PP Bus R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R R PP Bus R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 M_LOCK ON T_TGT_A BORT TGT_RET RY MST_DIS Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R R R R R W R W PP Bus R W R W R W R R R R R W R W Bit 7 6 5 4 3 2 1 0 ADRPER R SERR_D ET T_DPER R_WT T_PERR_ DET M_TGT_A BORT M_MST_ ABORT M_DPE...

Page 888: ... to 10 Reserved These bits always return 0 when read Always write 0 to these bits Bit 9 Target Retry Timeout Interrupt Mask TGT_RETRY Bit 8 Master Function Disable Error Interrupt Mask MST_DIS Bit 7 Address Parity Error Detection Interrupt Mask ADRPERR Bit 6 Detection Interrupt Mask SERR_DET Bit 5 Target Write Data Parity Error Interrupt Mask T_DPERR_WT Bit 4 Target Read Detection Interrupt Mask T...

Page 889: ...G5 ALOG4 ALOG3 ALOG2 ALOG1 ALOG0 Initial value PCI R W R R R R R R R R PP Bus R W R R R R R R R R The PCI address data register at error PCIALR stores the PCI address data ALOG 31 0 of errors that occur on the PCI bus It is a 32 bit register that can be read from both the PP bus and PCI bus The PCIALR register is not initialized at a power on reset or software reset The initial value is undefined ...

Page 890: ... R R R The PCI command data register at error PCICLR stores the type of transfer MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3 or TGT when an error occurs on the PCI bus and the PCI command CMDLOG 3 0 It is a 32 bit register that can be read from both the PP bus and PCI bus Although bits 31 to 26 of the PCICLR register are initialized at a power on reset and a software reset bits 3 through 0 are not init...

Page 891: ... 28 DMA2 Error MSTDMA2 Error occurred in DMA channel 2 transfer Bit 27 DMA3 Error MSTDMA3 Error occurred in DMA channel 3 transfer Bit 26 Target Error TGT Error occurred in target read or target write transfer Bits 25 to 4 Reserved These bits are always read as 0 Bits 3 to 0 Command Log CMDLOG3 to 0 These bits retain the PCI transfer command information value of C line upon detection of an error I...

Page 892: ...e Cleared by writing WC 1 Writing of 0 is ignored The PCI arbiter interrupt register PCIAINT is a 32 bit register that stores the sources of PCI bus errors occurring during transfers by another PCI master device when the PCIC is operating as the host with the arbitration function The register can be read from both the PP bus and the PCI bus Also each interrupt detection bit can be cleared to its i...

Page 893: ...4 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 3 Target Abort Interrupt TGT_ABORT Indicates the termination of transaction by target abort when a device other than the PCIC is operating as the bus master Bit 2 Master Abort Interrupt MST_ABORT Indicates the termination of transaction by master abort when a device other than the PCIC is operating as the...

Page 894: ...value 0 0 0 0 0 0 0 0 PCI R W R R R R R W R W R W R W PP Bus R W R R R R R W R W R W R W The PCI arbiter interrupt mask register PCIAINTM sets interrupt masks for the individual interrupts that occur due to errors generated during PCI transfers performed by other PCI devices when the PCIC is operating as the host with the arbitration function Each bit is set to 0 to disable the respective interrup...

Page 895: ...R R R R R R R The PCI error bus master data register PCIBMLR stores the device number of the bus master at the time an error occurred in PCI transfer by another PCI device when the PCIC was operating as the host with the arbitration function It is a 32 bit register than can be read from both the PP bus and PCI bus The PCIINTM register is initialized to H 00000000 at a power on reset or software re...

Page 896: ... R W The PCI DMA transfer arbitration register PCIDMABT is a register that controls the arbitration mode in the case of DMA transfers Two types of DMA arbitration mode can be selected priority fixed and pseudo round robin This 32 bit read write register can be accessed from both the PP bus and PCI bus The PCIDMABT register is initialized to H 00000000 at a power on reset or software reset Always w...

Page 897: ...2 1 0 PDPA7 PDPA6 PDPA5 PDPA4 PDPA3 PDPA2 PDPA1 PDPA0 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W The DMA transfer PCI address register 3 0 PCIDPA 3 0 specifies the starting address at the PCI when performing DMA transfers This 32 bit read write register can be accessed from both the PP bus and PCI bus The PCIINTM register is ini...

Page 898: ...P Bus R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 PDLA15 PDLA14 PDLA13 PDLA12 PDLA11 PDLA10 PDLA9 PDLA8 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PDLA7 PDLA6 PDLA5 PDLA4 PDLA3 PDLA2 PDLA1 PDLA0 Initial value 0 0 0 0 0 0 0 0 PCI R W R W R W R W R W R W R W R W R W PP Bus R W R W R W R W R W ...

Page 899: ... PDLA28 to 0 These bits set the starting address of the local bus external address of SH for DMA transfer Bits 28 to 26 indicate the local bus area 22 2 30 PCI DMA Transfer Counter Register 3 0 PCIDTC 3 0 Bit 31 30 29 28 27 26 25 24 PTC25 PTC24 Initial value 0 0 0 0 0 0 0 0 PCI R W R R R R R R R W R W PP Bus R W R R R R R R R W R W Bit 23 22 21 20 19 18 17 16 PTC23 PTC22 PTC21 PTC20 PTC19 PTC18 PT...

Page 900: ... to 0 are used to specify the number of transfer bytes When set to H 00000000 the maximum 64MB transfer is performed Since the transfer data size corresponds only to longword data the 2 least significant bits are ignored Always write to this register prior to starting a DMA transfer Please re set this register when starting a new DMA transfer after a DMA transfer completes Bits 31 to 26 Reserved T...

Page 901: ... channels and the method of transfer etc This 32 bit read write register can be accessed from the PP bus and PCI bus The PCIDCR register is initialized to H 00000000 at a power on reset and software reset Writing 1 to bit 0 DMASTRT starts DMA transfer Always re set the value in this register before starting a new DMA transfer after completion of a DMA transfer When setting the DMASTOP bit do not w...

Page 902: ... Abnormal termination Error detection or forced DMA transfer termination Bit 7 DMA Transfer Termination Interrupt Mask DMAIM Specifies the DMA transfer termination interrupt mask Bit 7 DMAIM Description 0 Interrupt disabled Initial value 1 Interrupt enabled Bit 6 DMA Transfer Termination Interrupt Status DMAIS Indicates the DMA transfer termination interrupt status The interrupt status is set even...

Page 903: ...om PCI bus to local bus SH bus Initial value 1 Transfer from local bus SH bus to PCI bus Bit 1 Forced DMA Transfer Termination DMASTOP Forced termination of DMA transfer Bit 1 DMASTOP Description When writing 0 Writing of 0 is ignored 1 Forced termination of DMA transfer When reading When DMA transfer stops due to forced DMA transfer termination 1 is set Bit 0 DMA Transfer Start Control DMASTRT Co...

Page 904: ...R W R R The PIO address register PCIPAR is used when issuing configuration cycles on the PCI bus when the PCIC is host The PCIC supports the configuration mechanism 1 stipulated in the PCI local bus specifications This register is equivalent to the configuration register of configuration mechanism 1 This register is equivalent to the CONFIG_ADDRESS of configuration mechanism 1 The check that the i...

Page 905: ...ubject to configuration access The device No is expressed with 5 bits and takes a value from bits 0 to 31 In place of IDSEL one of bits 31 to 16 of the A D line corresponding to the device No set in this field is driven to 1 The following table shows the relationship between the device No and IDSEL A D 31 to 16 When the device No is 10h or greater A D 31 to 16 are all zeros DEVNO IDSEL DEVNO IDSEL...

Page 906: ...ister PCIMBR specifies the most significant 8 bits of the address of the PCI memory space when performing a memory read write operation using PIO transfers It also specifies locked transfers This 32 bit read write register can be accessed from the PP bus All bits of the PCIMBR register are initialized to 0 at a power on reset They are not initialized at a software reset Setting bit 0 LOCK to 1 loc...

Page 907: ...ription 0 Not locked Initial value 1 Locked 22 2 34 I O Space Base Register PCIIOBR Bit 31 30 29 28 27 26 25 24 IOBR31 IOBR30 IOBR29 IOBR28 IOBR27 IOBR26 IOBR25 IOBR24 Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 IOBR23 IOBR22 IOBR21 IOBR20 IOBR19 IOBR18 Initial value 0 0 0 0 0 0 0 0 PCI R W PP Bus R W R W R W R W R W R W R W R R Bit ...

Page 908: ...r PIO transfers while the bit remains set A locked transfer consists of the combined read and write operations Do not attempt to perform other PIO transfers during the locked combination of read and write operations Always write to this register prior to I O space read and I O space write operations by PIO transfer Bits 31 to 18 I O Space Base Address IOBR31 to 18 Sets the base register for the PC...

Page 909: ...write register can be accessed from the PP bus The PCIPINT register is initialized to H 00000000 at a power on reset It is not initialized at a software reset When an interrupt is detected the bit corresponding to the content of that interrupt is set to 1 Each interrupt detection bit can be cleared to 0 by writing 1 to it write clear The power state D0 interrupt is not generated at a power on rese...

Page 910: ... The PCIPINTM register is initialized to H 00000000 at a power on reset It is not initialized at a software reset Interrupt masks can be set for both the interrupt for a transition to the power state D3 power down mode and recovery to the power state D0 normal status Setting the respective bit to 0 disables the interrupt and setting it to 1 enables the interrupt Bits 31 to 2 Reserved These bits al...

Page 911: ...set When the PCI bus clock is input from the external input pin the PCI bus clock can be stopped by setting the PCICLKSTOP bit to 1 Likewise the local bus clock can be stopped by setting the BCLKSTOP bit to 1 When the PCI bus clock is input via the CKIO pin setting BCLKSTOP to 1 stops both the B in the PCIC and the feedback input clock from CKIO Writing to this register is valid only when bits 31 ...

Page 912: ... equivalent to the WCR3 of the BSC and PCIMCR equivalent to the MCR of the BSC Each is a 32 bit register BCR2 and BCR3 are 16 bit registers but PCIBCR2 and PCIBCR3 should be accessed by longword access The low 16 bits of PCIBCR2 and PCIBCR3 corresponds to the 16 bits of these registers respectively See section 13 Bus State Controller BSC for details of the initial values etc The PCIC BSC performs ...

Page 913: ... same settings as the corresponding bus state controller register These registers are initialized at a power on reset but not by a software reset Notes 1 This register is provided only in the SH7751R not provided in the SH7751 2 MPX is supported only in the SH7751R not supported in the SH7751 22 2 39 Port Control Register PCIPCTR Bit 31 30 29 28 27 26 25 24 Initial value 0 0 0 0 0 0 0 0 PCI R W PP...

Page 914: ...urn 0 when read Always write 0 to these bits when writing Bit 18 Port 2 Enable PORT2EN Provides the enable control for the port 2 Bit 18 PORT2EN Description 0 Do not use pins or as ports Initial value 1 Use pins or as ports Bit 17 Port 1 Enable PORT1EN Provides the enable control for the port 1 Bit 17 PORT1EN Description 0 Do not use pins or as ports Initial value 1 Use pins or as ports Bit 16 Por...

Page 915: ...itial value 1 Do not pull up pin Bit 2 Port 1 Input Output Control PB1IO Controls input or output when is used as a port Bit 2 PB1IO Description 0 Set pin for input Initial value 1 Set pin for output Bit 1 Port 0 Pull up Resistance Control PB0PUP Controls pull up resistance when pin is used as port Bit 1 PB0PUP Description 0 Pull up pin Initial value 1 Do not pull up pin Bit 0 Port 0 Input Output ...

Page 916: ...alized to H 00000000 at a power on reset It is not initialized at a software reset Data is output in sync with the local bus clock Input data is fetched at the rising edge of the local bus clock Bits 31 to 6 Reserved These bits always return 0 when read Always write 0 to these bits when writing Bit 5 Port 2 Output Data PB5DT Output data when pin is used as port pin is output only Bit 4 Port 2 Inpu...

Page 917: ...DA10 PPDA9 PPDA8 Initial value PCI R W PP Bus R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PPDA7 PPDA6 PPDA5 PPDA4 PPDA3 PPDA2 PPDA1 PPDA0 Initial value PCI R W PP Bus R W R W R W R W R W R W R W R W R W The PIO data register PCIPDR sets the data for read write in the PCI configuration cycle This 32 bit read write register can be accessed from the PP bus The PCIPDR register is not initi...

Page 918: ...tion of a power on reset Table 22 8 Operating Modes MD9 MD10 Operating Modes 0 The PCIC host functions are enabled and the external input via the PCICLK pin is the operating clock for the PCI bus 0 1 The PCIC host functions are enabled and the SH7751 Series bus clock feedback input clock from CKIO pin is the operating clock for the PCI bus 0 The PCIC host functions are disabled non host and the in...

Page 919: ...errupt acknowledge cycle X X X X Special cycle O X Dual address cycle X X X X Notes O Supported Limited support X Not issued by PCIC or no response from PCIC When PCIC Operates as Master The PCIC supports the memory read command memory write command I O read command and I O write command When the host functions are enabled the configuration command and special cycle can also be used When PCIC Oper...

Page 920: ...nabled When operating as non host the PCIC can be accessed from the PCI bus Regardless of whether the PCIC is operating as the host or non host external PCI devices cannot be accessed from the PCIC while the CFINT bit is being cleared Set the CFINIT bit to 1 before accessing an external PCIC device Be sure to initialize the following 13 registers while the CFINIT bit is being cleared configuration...

Page 921: ...ds with the data having been written to the interface register located immediately after the PCIC input register on the internal bus for peripheral modules but the data is not actually written to the local register s or PCI bus until the following clock cycle If it is necessary to check that the data has actually been written read the register to which the data was to have been written This is bec...

Page 922: ...est pins and device 2 uses and device 3 uses and and device 4 uses and When the PCIC is operating as the host device no bus privilege request signals are output from the PCIC to the PCI bus arbitration circuit Pseudo round robin mode BMABT 1 In pseudo round robin mode when a device takes the bus privilege the priority order of that device becomes lowest In the initial state the priority order is s...

Page 923: ...a configuration read write transfer for accessing the configuration register The PCIC supports the configuration mechanism stipulated in the PCI local bus spec First specify in the PCIPAR the address of the configuration register of the external PCI device to be accessed See section 22 2 PCIC Register Descriptions for how to set the PCIPAR Next read data from the PCIPDR or write data to the PCIPDR...

Page 924: ...arking Also when the PCIC is used as a target device that does not request bus privileges the pins must be fixed at the high level 22 3 7 PIO Transfers PIO transfer is a data transfer mode in which a peripheral bus is used to access the memory space and I O space of the PCI bus The following commands are supported in PIO transfer mode Memory read memory write I O read and I O write Locked transfer...

Page 925: ... again When performing locked transfers in memory transfer mode set the PCIMBR memory space lock specification bit LOCK While the LOCK bit is set the memory space is locked Note the following when performing LOCK transfers A LOCK transfer consists of one read transfer and one write transfer Always start with the read transfer The system will operate correctly if you start with a write transfer but...

Page 926: ...the I O space base register PCIIOBR are used as the most significant 14 bits of the PCI address These two addresses are combined to specify the 32 bit PCI address For transfers to the I O space first specify the most significant 14 bits of the PCI address in PCIIOBR then access the PCI I O address space If within the 256kB space you can access the PCI I O address space consecutively simply by sett...

Page 927: ...lowing commands are available for transferring data in target transfers Memory read and memory write I O read and I O write access to PCIC local registers Configuration read configuration write Locked transfer is supported High speed back to back is not supported When the PCIC is operating in non host mode no response is made on reception of special cycle commands Memory Read Memory Write Commands...

Page 928: ... and PCI local address register 1 PCILAR 1 PCICONF5 PCICONF6 PCILSR0 PCILSR1 PCILAR0 PCILAR1 31 20 19 0 31 0 31 28 20 19 0 31 28 20 19 0 31 28 0 000001111 PCI address Local address PCIC access adjudication Figure 22 4 Local Address Space Accessing Method The PCIC supports two local address spaces address space 0 and address space 1 A certain range of the address space on the PCI bus corresponds to...

Page 929: ...ess space includes areas for which no memory is installed Note that in this case it is not possible to disable target transfers to areas for which no memory is installed I O Read and I O Write Commands The local registers of the PCIC are accessed by means of a target transfer triggered by an I O read or I O write command In the SH7751 accessing the local registers by means of I O transfer is made ...

Page 930: ... for all memory accesses of the PCIC from other PCI devices Register access is however accepted Similarly while the registers are locked retry is returned for all I O accesses or configuration accesses of the PCIC from another PCI device but memory access is accepted 22 3 9 DMA Transfers DMA transfers allow the high speed transfer of data between devices connected to the local bus and PCI bus when...

Page 931: ...these registers are ignored the transfer is performed in longword units Also note that the local bus starting address set in PCIDLA is the physical address PCIDPA PCIDLA and PCIDTC are updated during data transfer If another DMA transfer is to be performed on completion of one DMA transfer new values must be set in these registers The registers controlling DMA transfers can be set from both CPU an...

Page 932: ...o round robin 0 1 31 28 PCIDLA 0 31 26 25 PCIDTC 0 31 PCIDPA 0 31 11 10 PCIDCR 0 Transfer control PCI address Transfer count Local address Area 0 H 00000000 to H 03FFFFFF Area 1 H 04000000 to H 07FFFFFF Area 2 H 0800 0000 to H 0BFFFFFF Area 3 H 0C000000 to H 0FFFFFFF Area 4 H 10000000 to H 13FFFFFF Area 5 H 14000000 to H 17FFFFFF Area 6 H 18000000 to H 1BFFFFFF 32 bits Figure 22 5 Example of DMA T...

Page 933: ...sfer When an error occurs during DMA transfer the DMA transfer is forcibly terminated on the channel in which the error occurred There is no effect on data transfers on other channels Forced termination of DMA transfer When the PCIDCR and DMASTOP bits for a channel are set data transfer on that channel is forcibly terminated However when the DMASTOP bit is set do not write 1 to the DMASTRT bit Als...

Page 934: ...ing the number of transfer bytes 4 bytes After DMA transfer completion the DMASTRT bit of the PCIDCR register is cleared to 0 and the DMAIS bit of the PCIDCR register is set to 1 DMA transfer is forcibly stopped when 1 is set in the DMASTOP bit of the PCIDCR register Do not set 1 in the DMASTRT bit at the same time Figure 22 6 Example of DMA Transfer Flowchart Termination by software reset When th...

Page 935: ... same time as a PIO transfer request the PIO transfer takes precedence over transfers on the four DMA channels regardless of the specified mode of DMA transfer priority order Fixed Priority Mode DMABT 0 In fixed priority mode the order of priority of data transfer requests is fixed and cannot be changed The order is as follows Channel 0 DMA transfer channel 1 DMA transfer channel 2 DMA transfer ch...

Page 936: ...completion of channel 2 This pattern is the same when data is transferred from the PCI bus to the local bus Pseudo round robin mode DMABT 1 In pseudo round robin mode as each time data is transferred the order of priority is changed so that the priority level of the completed data transfer becomes the lowest Regarding pseudo round robin mode operations refer to section 22 3 5 Host Functions 22 3 1...

Page 937: ...transfer a high impedance state of at least one clock is generated prior to the address phase In host mode the arbiters in the PCICs and the REQ and GNT between PCICs are connected internally Here pins MD9 MD10 and function as the REQ inputs from the external masters 1 to 4 Similarly and function as the GNT outputs to external masters 1 to 4 Including the PCIC arbitration of up to five masters is ...

Page 938: ... 1064 PCICLK AD31 AD0 PAR C C IDSEL Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr D0 Com BE0 AP DP0 LOCKed Figure 22 7 Master Write Cycle in Host Mode Single ...

Page 939: ...f 1064 PCICLK AD31 AD0 PAR C C IDSEL Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr D0 Com BE0 AP DPn LOCKed Figure 22 8 Master Read Cycle in Host Mode Single ...

Page 940: ...AD31 AD0 PAR C C IDSEL Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr D0 D1 Dn Com BE0 BE1 BEn AP DP0 DPn 1 APn Figure 22 9 Master Memory Write Cycle in Non Host Mode Burst ...

Page 941: ...AD31 AD0 PAR C C IDSEL Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr D0 D1 Dn Com BE0 BE1 BEn AP DP0 DPn 1 DPn Figure 22 10 Master Memory Read Cycle in Non Host Mode Burst ...

Page 942: ...t either a or b below a If using the data that has been read perform two read operations and use only the data from the second read operation b If not using the data that has been read if you are performing the read operation in order to determine the timing for actually writing data to the destination be sure that the read address immediately after writing is different from the write address Note...

Page 943: ...1 AD0 PAR C C IDSEL Addr D0 BE0 DP0 AP Com LOCKed At Config Access Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Disconnect Figure 22 11 Target Read Cycle in Non Host Mode Single ...

Page 944: ...1 AD0 PAR C C IDSEL Addr D0 BE0 DP0 AP Com Disconnect At Config Access LOCKed Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Figure 22 12 Target Write Cycle in Non Host Mode Single ...

Page 945: ...0 PAR C C IDSEL Addr D0 BE0 DP0 AP Com BE1 BEn D1 Dn DPn 1 DPn Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable LOCKed Disconnect Figure 22 13 Target Memory Read Cycle in Host Mode Burst ...

Page 946: ... PAR C C IDSEL Addr Dn D1 D0 BE0 DP0 AP DPn 1 DPn Com BE1 BEn Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable LOCKed Disconnect Figure 22 14 Target Memory Write Cycle in Host Mode Burst ...

Page 947: ...ve the stipulated logic level in one clock When the PCIC operates as the host it is recommended to use this function for the issuance of configuration transfers Figure 22 15 is an example of burst memory write cycle with stepping Figure 22 16 is an example of target burst read cycle with stepping PCICLK AD31 AD0 PAR C C Com BE0 BEn AP DP0 DPn 1 DPn Addr D0 Dn Addr PCI space address Dn nth data AP ...

Page 948: ... AD31 AD0 PAR Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr BEn AP DP0 DPn 1 DPn Com D0 Dn BE0 C C Figure 22 16 Target Memory Read Cycle in Host Mode Burst With Stepping ...

Page 949: ...Big endian 32 bits 32 bits 32 bits 32 bits Little endian PCI bus Big little Little big Figure 22 17 Endian Conversion Modes for Peripheral Bus 1 Byte data boundary mode Big little endian conversion is performed on the assumption that all data is on byte boundaries BYTESWAP 1 2 Word longword W LW boundary mode Big little endian conversion is performed according to the size of data accessed BYTESWAP...

Page 950: ...rd LW Longword Size Address Data Data W LW boundary mode Address memory I O Data Byte data boundary mode Long Word B0 B0 B0 4n 0 4n 0 1110 4n 0 Byte B1 B1 B1 4n 0 4n 1 1101 4n 1 B2 B2 B2 4n 0 4n 2 1011 4n 2 B3 B3 B3 4n 0 4n 3 0111 4n 3 B0 B1 B0 B1 B1 B0 4n 0 4n 0 1100 4n 0 B2 B3 B2 B3 B3 B2 4n 0 4n 2 0011 4n 2 B0 B1 B2 B3 B0 B1 B2 B3 B3 B2 B1 B0 4n 0 4n 0 0000 4n 0 Peripheral bus PCI bus Word Memo...

Page 951: ...2 bits 32 bits 32 bits 32 bits LW LW LW B W LW FIFO DMA Target RD DMA Targer WT FIFO Figure 22 19 Endian Control for Local Bus 22 4 3 Endian Control in DMA Transfers Although only the longword access size is supported in DMA transfers see table 22 11 the endian conversion mode can be selected from the following four types depending on whether the longword data consists of four byte data units or t...

Page 952: ...ndary Mode 1 to 3 Byte Data Boundary Mode Big endian Local bus PCI bus LW Yes Yes Little endian Local bus PCI bus LW Conversion not required Conversion not required B0 0000 B1 B2 B3 Size LW B3 B2 B1 B0 B3 B2 B1 B0 B2 B3 B0 B1 B0 B1 B2 B3 When local bus is big endian Local bus PCI bus Byte data boundary mode W LW boundary mode 1 W LW boundary mode 2 W LW boundary mode 3 B3 0000 B2 B1 B0 Size LW B3 ...

Page 953: ...get reads local bus to PCI bus longword only For target writes PCI bus to local bus longword word byte In target write operations the byte word and longword data in the PCIC are transferred to the local bus in one or two transfer operations depending on the type of the byte enable signal of the PCI bus For example when C b 1010 byte access to the local bus is generated twice When C b 1000 byte acc...

Page 954: ...10 0001 1111 0000 B1 B2 B3 B1 B0 B3 B2 B2 B0 B3 B1 B3 B0 B2 B1 B2 B1 B0 B3 B1 B0 B3 B2 B0 B3 B2 B1 B3 B2 B1 B0 Local bus PCI bus 31 0 31 0 Target memory write transfers local bus PCI bus when local bus is big endian BE Size LW B0 B1 B2 B3 B3 B2 B1 B0 H 0 to H F Local bus PCI bus 31 0 31 0 Target memory read transfers local bus PCI bus when local bus is big endian BE Figure 22 21 1 Data Alignment a...

Page 955: ...001 1111 0000 B1 B2 B3 B1 B0 B3 B2 B2 B0 B3 B1 B3 B0 B2 B1 B2 B1 B0 B3 B1 B0 B3 B2 B0 B3 B2 B1 B3 B2 B1 B0 Local bus PCI bus 31 0 31 0 Target memory write transfers local bus PCI bus when local bus is little endian BE Size LW B3 B2 B1 B0 B3 B2 B1 B0 H 0 to H F Local bus PCI bus 31 0 31 0 Target memory read transfers local bus PCI bus when local bus is little endian BE Figure 22 21 2 Data Alignment...

Page 956: ...Size LW Address 4n H 0000 PCI bus B3 B2 B1 B0 31 0 BE Local register B3 B2 B1 B0 31 0 Target I O read transfer data alignment local register PCI bus Target I O write transfer data alignment PCI bus local register Figure 22 22 Data Alignment at Target I O Transfer Both Big Endian and Little Endian 22 4 6 Endian Control in Target Transfers Configuration Read Configuration Write The data alignment wh...

Page 957: ... H F PCI bus B3 B2 B1 B0 31 0 BE Configuration register B3 B2 B1 B0 31 0 B0 31 0 B3 B2 B1 31 0 B3 B2 B0 31 0 B3 B2 31 0 B3 B1 B0 31 0 B3 B1 B0 31 0 B3 B1 31 0 B3 B0 31 0 B3 31 0 B2 B1 B0 31 0 B2 B1 31 0 B2 B0 31 0 B2 31 0 B1 B0 31 0 B1 31 0 B3 B2 B1 B0 31 0 31 0 B0 31 0 Target configuration read transfer data alignment configuration register PCI bus SH7751 target configuration write transfer data ...

Page 958: ...rt the input of manual reset signals via the pin No initialization therefore occurs by manual resets Software Reset Software resets are generated by setting 1 in the output control bit RSTCTL of the PCI control register PCICR The pin is asserted at the same time as the PCIC is reset While a software reset is asserted the PCIC registers cannot be accessed Assertion requires a minimum of 1ms Softwar...

Page 959: ...sserted This interrupt is generated only when the PCIC is operating as host When the PCIC is operating as non host the SERR bit in the PCI control register PCICR is used to notify the host device of the system error assertion of pin The pin can be asserted when the SERR bit is asserted and when an address parity error is detected in a target transfer When the SER bit of the PCI configuration regis...

Page 960: ...ion Interrupt PCIDMA3 The DMA termination interrupt status DMAIS bit of the DMA control register 3 PCIDCR3 is set The interrupt mask is set by the DMA termination interrupt mask DMAIM bit of the same register Power Management Interrupt Transition Request to Normal Status PCIPWON The power state D0 PWRS_D0 bit of the PCI power management interrupt register PCIPINT is set The power state D0 interrup...

Page 961: ...s operation The peripheral module clock and PCI bus clock do not need to be in sync and there is no particular limit on the frequency ratio However in PIO transfers and when registers are being accessed etc circuits operating with the peripheral module clock and circuits operating with the PCI bus clock and circuits that synchronize both clocks are used so the transfer speed depends on the frequen...

Page 962: ...ation register 1 and monitoring the pin in the PCI bus standard The PCIC supports the 66 MHz operating status 66M bit of the configuration register 1 PCICONF1 The PCIC does not have a special pin for directly monitoring the pin Also there is no control output pin for switching between 33 MHz and 66 MHz when an external oscillator is used A special external circuit is required to effect these contr...

Page 963: ...in a minimum of 16 clocks after the host device has instructed a transition to power state D3 After detecting a power state D3 power down interrupt do not therefore attempt to read or write to local registers that can be accessed from the CPU and PCI bus Because these registers operate using the PCI bus clock the read write cycle for these registers will not be completed if the clock stops 22 9 2 ...

Page 964: ... operation Not used Normal operation BCLK Stopped Stopped Stopped Stopped PCLK Stopped Stopped Stopped Stopped Clock operating status Standby PCICLK Not used Stopped Not used Stopped Transition Sleep command BCLK stopped from SH BCLK and PCICLK stopped from SH PCI command interrupt PCIC SH BCLK restarted from SH Recovery 1 Not used PME interrupt connected to IRL BCLK restarted from SH PME interrup...

Page 965: ... clock can be stopped by writing 1 to the PCICLKSTOP bit The bus clock can be stopped by writing 1 to the BCLKSTOP bit It requires a minimum of 2 clocks of the PCI bus clock for the clock to actually stop after writing to PCICLKR setting the PCICLKSTOP bit to 1 It takes a similar time for the clock to restart Bus Clock CKIO Operating Mode Both the PCI bus clock and bus clock can be stopped by writ...

Page 966: ...y and Sleep To stop all the PCIC s internal clocks the SLEEP command must be used to transit to standby mode When operating in external input pin PCICLK operating mode set the PCICLKSTOP bit to 1 to stop the PCI bus clock transit to standby then after recovering from standby clear the PCICLKSTOP bit to 0 to prevent hazards occuring in the PCI bus clock Note that the PCIC clock does not stop after ...

Page 967: ...Rev 3 0 04 02 page 928 of 1064 22 11 Version Management The PCIC version management is written in the revision ID 8 bits of the PCI configuration register 2 PCICONF2 ...

Page 968: ...VDD PLL1 2 0 3 to 2 5 0 3 to 2 1 2 V Input voltage Vin 0 3 to VDDQ 0 3 V Operating temperature Topr 20 to 75 40 to 85 1 C Storage temperature Tstg 55 to 125 C Notes The LSI may be permanently damaged if the maximum ratings are exceeded The LSI may be permanently damaged if any of the VSS pins are not connected to GND For the powering on and powering off sequences see Appendix G Power On and Power ...

Page 969: ...eep mode deep sleep mode standby mode Current dissipation Normal operation IDD 255 660 Sleep mode 140 180 mA I 240 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 100 145 Sleep mode 60 115 mA I 240 MHz B 120 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 A RTC off Input voltage NMI BRKACK CA VIH VD...

Page 970: ... 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDD is the sum of the VDD a...

Page 971: ...ep sleep mode standby mode Current dissipation Normal operation IDD 255 660 Sleep mode 140 180 mA I 240 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 85 120 Sleep mode 50 95 mA I 240 MHz B 80 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 A RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 ...

Page 972: ... 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 12 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDD is the sum of the VDD a...

Page 973: ...ep sleep mode standby mode Current dissipation Normal operation IDD 210 550 Sleep mode 115 150 mA I 200 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 85 120 Sleep mode 50 95 mA I 200 MHz B 100 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 A RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0...

Page 974: ... 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDD is the sum of the VDD a...

Page 975: ...ep sleep mode standby mode Current dissipation Normal operation IDD 210 550 Sleep mode 115 150 mA I 200 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Current dissipation Normal operation IDDQ 85 120 Sleep mode 50 95 mA I 200 MHz B 67 MHz Standby mode 400 A Ta 25 C 1 800 Ta 50 C 1 Standby mode 15 25 RTC on 2 Current dissipation IDD RTC 3 5 A RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 ...

Page 976: ... 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 12 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unloaded 3 IDD is the sum of the VDD a...

Page 977: ...ode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA I 167 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA I 167 MHz B 84 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 A RTC on Current dissipation 5 RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 3 V PCICLK...

Page 978: ...VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5...

Page 979: ...mode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA I 167 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA I 167 MHz B 84 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 A RTC on Current dissipation 5 RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 3 V PCICL...

Page 980: ...VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5...

Page 981: ...ode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA I 167 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA I 167 MHz B 84 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 A RTC on Current dissipation 5 RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 3 V PCICLK...

Page 982: ...VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5...

Page 983: ...ode Current dissipation Normal operation IDD 420 750 Sleep mode 100 130 mA I 167 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Current dissipation Normal operation IDDQ 70 100 Sleep mode 40 80 mA I 167 MHz B 84 MHz Standby mode 400 A Ta 25 C RTC on 800 Ta 50 C RTC on Standby mode IDD RTC 25 A RTC on Current dissipation 5 RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 3 V PCICLK...

Page 984: ...VDDQ 3 0 V IOL 4 mA Output voltage Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5...

Page 985: ... mode Normal operation 210 470 Sleep mode 60 80 mA I 133 MHz 200 Ta 25 C RTC on Current dissipation Standby mode IDD 300 A Ta 50 C RTC on Normal operation 35 80 Sleep mode 20 65 mA I 133 MHz B 67 MHz 200 Ta 25 C RTC on Current dissipation Standby mode IDDQ 200 A Ta 50 C RTC on Standby mode IDD RTC 25 A RTC on Current dissipation 5 RTC off Input voltage NMI BRKACK CA VIH VDDQ 0 9 VDDQ 0 3 V PCICLK ...

Page 986: ... pins VOL 0 55 VDDQ 3 0 V IOL 4 mA Other output pins 0 55 VDDQ 3 0 V IOL 2 mA Pull up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL 10 pF Notes 1 Connect VDD RTC and VDD CPG to VDDQ VDD PLL1 2 to VDD and VSS CPG VSS PLL1 2 and VSS RTC to GND regardless of whether or not the PLL circuits and RTC are used 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5...

Page 987: ...rent total IOH 40 Note To protect chip reliability do not exceed the output current values in table 23 11 23 3 AC Characteristics In principle this LSI s input should be synchronous Unless specified otherwise ensure that the setup time and hold times for each input signal are observed Table 23 12 Clock Timing HD6417751RBP240 Item Symbol Min Typ Max Unit Notes CPU FPU cache TLB f 1 240 MHz External...

Page 988: ...p Max Unit Notes CPU FPU cache TLB f 1 200 MHz External bus 1 84 Operating frequency Peripheral modules 1 50 Table 23 16 Clock Timing HD6417751BP167 I HD6417751F167 I Item Symbol Min Typ Max Unit Notes CPU FPU cache TLB f 1 167 MHz External bus 1 84 Operating frequency Peripheral modules 1 42 Table 23 17 Clock Timing HD6417751VF133 Item Symbol Min Typ Max Unit Notes CPU FPU cache TLB f 1 134 MHz E...

Page 989: ... clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 assert time tRESW 20 tcyc 23 3 23 4 23 5 23 6 PLL synchronization settling time tPLL 200 s 23 9 23 10 Standby return oscillation settling tim...

Page 990: ...level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 assert time tRESW 20 tcyc 23 3 23 4 23 5 23 6 PLL synchronization settling time tPLL 200 s 23 9 23 10 Standby return oscillation settling time 1 tOSC2 3 ms 23 4...

Page 991: ...evel pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 assert time tRESW 20 tcyc 23 3 23 4 23 5 23 6 PLL synchronization settling time tPLL 200 s 23 9 23 10 Standby return oscillation settling time 1 tOSC2 5 ms 23 4 ...

Page 992: ...evel pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 assert time tRESW 20 tcyc 23 3 23 4 23 5 23 6 PLL synchronization settling time tPLL 200 s 23 9 23 10 Standby return oscillation settling time 1 tOSC2 5 ms 23 4 ...

Page 993: ...IO clock output high level pulse width tCKOH1 1 ns 23 2 1 CKIO clock output rise time tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD...

Page 994: ...rise time tCKOr 3 ns 23 2 1 CKIO clock output fall time tCKOf 3 ns 23 2 1 CKIO clock output low level pulse width tCKOL2 3 ns 23 2 2 CKIO clock output high level pulse width tCKOH2 3 ns 23 2 2 Power on oscillation settling time tOSC1 10 ms 23 3 23 5 Power on oscillation settling time mode settling tOSCMD 10 ms 23 3 23 5 MD reset setup time tMDRS 3 tcyc MD reset hold time tMDRH 20 ns 23 3 23 5 asse...

Page 995: ... VIL VIH 1 2VDDQ Note When the clock is input from the EXTAL pin Figure 23 1 EXTAL Clock Input Timing tcyc tCKOH1 tCKOL1 tCKOr tCKOf 1 2VDDQ VOH VOH VOL VOL VOH 1 2VDDQ Figure 23 2 1 CKIO Clock Output Timing tCKOH2 1 5 V 1 5 V 1 5 V tCKOL2 Figure 23 2 2 CKIO Clock Output Timing ...

Page 996: ...tes 1 Oscillation settling time when on chip resonator is used 2 PLL2 not operating Figure 23 3 Power On Oscillation Settling Time or tRESW tOSC2 Standby Stable oscillation CKIO internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 not operating Figure 23 4 Standby Return Oscillation Settling Time Return by or ...

Page 997: ... 1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 23 5 Power On Oscillation Settling Time or tRESW tOSC2 CKIO Stable oscillation Standby Internal clock Notes 1 Oscillation settling time when on chip resonator is used 2 PLL2 operating Figure 23 6 Standby Return Oscillation Settling Time Return by or ...

Page 998: ...illation settling time when on chip resonator is used Figure 23 7 Standby Return Oscillation Settling Time Return by NMI tOSC4 Standby Stable oscillation CKIO internal clock Note Oscillation settling time when on chip resonator is used Figure 23 8 Standby Return Oscillation Settling Time Return by ...

Page 999: ...quest PLL synchronization PLL synchronization Figure 23 9 PLL Synchronization Settling Time in Case of or NMI Interrupt interrupt request tIRLSTB STATUS1 STATUS0 Note When an external clock is input from EXTAL Normal Standby Normal tPLL 2 EXTAL input PLL output CKIO output Internal clock Stable input clock Stable input clock PLL synchronization PLL synchronization Figure 23 10 PLL Synchronization ...

Page 1000: ...me tBREQH 1 5 1 5 1 5 1 5 ns 23 11 delay time tBACKD 5 3 5 3 6 6 ns 23 11 Bus tri state delay time tBOFF1 12 12 12 12 ns 23 11 Bus tri state delay time to standby mode tBOFF2 2 2 2 2 tcyc 23 12 Bus buffer on time tBON1 12 12 12 12 ns 23 11 Bus buffer on time from standby tBON2 1 1 1 1 tcyc 23 12 STATUS0 1 delay time tSTD1 5 3 5 3 6 6 ns 23 12 STATUS0 1 delay time to standby tSTD2 2 2 2 2 tcyc 23 1...

Page 1001: ...2 12 ns 23 11 Bus tri state delay time to standby mode tBOFF2 2 2 tcyc 23 12 Bus buffer on time tBON1 12 12 ns 23 11 Bus buffer on time from standby tBON2 2 2 tcyc 23 12 STATUS0 1 delay time tSTD1 9 9 ns 23 12 STATUS0 1 delay time to standby tSTD2 2 2 tcyc 23 12 Notes 1 VDDQ 3 0 to 3 6 V VDD 1 5 V typ Ta 20 to 75 C CL 30 pF PLL2 on 2 VDDQ 3 0 to 3 6 V VDD 1 8 V typ Ta 20 to 75 C CL 30 pF PLL2 on H...

Page 1002: ...on Normal operation Standby mode tSTD1 tBON2 CKIO STATUS0 STATUS1 DACKn DRAKn SCK TXD TXD2 CTS2 RTS2 Note When the PHZ bit in STBCR is set to 1 these pins go to the high impedance state except for pins being used as port pins which retain their port state A25 A0 D31 D0 tBOFF2 Standby Normal Normal tSTD2 Figure 23 12 Pin Drive Timing for Standby Mode ...

Page 1003: ... 1 5 6 1 5 6 ns Write data delay time tWDD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns setup time tRDYS 2 0 2 5 3 5 3 5 ns hold time tRDYH 1 5 1 5 1 5 1 5 ns delay time tRASD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns delay time 1 tCASD1 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns DRAM delay time 2 tCASD2 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns SDRAM CKE delay time tCKED 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns SDRAM DQM delay time tDQMD 1 5 5 3 1 5 5 3...

Page 1004: ...R hold time tDTRH 1 5 1 5 1 5 1 5 ns setup time tDBQS 2 0 2 5 3 5 3 5 ns hold time tDBQH 1 5 1 5 1 5 1 5 ns setup time tTRS 2 0 2 5 3 5 3 5 ns hold time tTRH 1 5 1 5 1 5 1 5 ns delay time tBAVD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns delay time tTDAD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns ID1 ID0 delay time tIDD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ns Note VDDQ 3 0 to 3 6 V VDD 1 5 V typ Ta 20 to 75 C CL 30 pF PLL2 on ...

Page 1005: ...to CKIO falling edge delay time tWED1 1 0 8 1 0 8 ns Write data delay time tWDD 1 0 8 1 0 8 ns setup time tRDYS 3 5 3 5 ns hold time tRDYH 1 5 1 5 ns delay time tRASD 1 0 8 1 0 8 ns delay time 1 tCASD1 1 0 8 1 0 8 ns DRAM delay time 2 tCASD2 1 0 8 1 0 8 ns SDRAM CKE delay time tCKED 1 0 8 1 0 8 ns SDRAM DQM delay time tDQMD 1 0 8 1 0 8 ns SDRAM delay time tFMD 1 0 8 1 0 8 ns MPX setup time tIO16S ...

Page 1006: ...hold time tDBQH 1 5 1 5 ns setup time tTRS 3 5 3 5 ns hold time tTRH 1 5 1 5 ns delay time tBAVD 1 0 8 1 0 8 ns delay time tTDAD 1 0 8 1 0 8 ns ID1 ID0 delay time tIDD 1 0 8 1 0 8 ns Notes 1 VDDQ 3 0 to 3 6 V VDD 1 5 V typ Ta 20 to 75 C CL 30 pF PLL2 on 2 VDDQ 3 0 to 3 6 V VDD 1 8 V typ Ta 20 to 75 C CL 30 pF PLL2 on HD6417751BP167 HD6417751F167 VDDQ 3 0 to 3 6 V VDD 1 8 V typ Ta 40 to 85 C CL 30 ...

Page 1007: ...tRDH tRDS tCSD tCSD tRWD tRWD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD tDACD tDACD tDACDF tDACDF tDACD DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 13 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 1008: ...tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 14 SRAM Bus Cycle Basic Bus Cycle One Internal Wait ...

Page 1009: ... tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 15 SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait ...

Page 1010: ...RSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CKIO A25 A0 RD D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 16 SRAM Bus Cycle Basic Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 1011: ...TB2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACKn SA IO memory DACKn DA tDACD tDACD tDACD tDACD tDACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 17 Burst ROM Bus Cycle No Wait ...

Page 1012: ... t RDYH t RDYS t RDYH t RDYS t DACD t DACD t DACD t DACD t RWD t RWD CKIO A25 A5 CSn RD WR RD D31 D0 read BS RDY A4 A0 DACKn SA IO memory DACKn DA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 18 Burst ROM Bus Cycle 1st Data One Internal Wait One External Wait 2nd 3rd 4th Data One Internal Wait ...

Page 1013: ... TB1 t AD t CSD t RWD t RDH t RSD t RDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CKIO A25 A5 RD D31 D0 read A4 A0 DACKn SA IO memory DACKn DA t DACD t DACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 19 Burst ROM Bus Cycle No Wait Address Setup Hold Time Insertion AnS 1 AnH 1 ...

Page 1014: ...S DACKn DA t DACD t DACD t DACD t BSD t BSD t BSD t BSD t RSD t RSD t RWD t CSD t RWD t CSD t DACD t DACD t RSD RD t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 20 Burst ROM Bus Cycle One Internal Wait One External Wait ...

Page 1015: ...D t RDH c1 t RDS DQMn CKE t CASD2 t CASD2 t DACD t DACD t RASD t RASD t DQMD t DQMD t RWD t RWD t BSD t BSD RD t CSD t CSD DACKn SA IO memory column Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 21 Synchronous DRAM Auto Precharge Read Bus Cycle Single RCD 1 0 01 CAS Latency 3 TPC 2 0 011 ...

Page 1016: ... RDH c1 c2 c3 c4 c5 c6 c7 c8 t RDS DQMn CKE t CASD2 t CASD2 t DACD t DACD t RASD t RASD t DQMD t DQMD t RWD t RWD t BSD t BSD RD t CSD t CSD t AD H L c1 DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 22 Synchronous DRAM Auto Precharge Read Bus Cycle Burst RCD 1 0 01 CAS Latency 3 TPC 2 0 011 ...

Page 1017: ... t AD t RDH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t CSD t CSD t RWD t RWD t RASD t RASD t BSD t BSD t DQMD t DQMD t DACD t DACD t CASD2 t CASD2 D31 D0 read DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 23 Synchronous DRAM Normal Read Bus Cycle ACT READ Commands Burst RCD 1 0 01 CAS Latency 3 ...

Page 1018: ... t AD t RDH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t CSD t CSD t RWD t RWD t RASD t RASD t BSD t BSD t DQMD t DACD t DACD t CASD2 t CASD2 t DQMD D31 D0 read DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 24 Synchronous DRAM Normal Read Bus Cycle PRE ACT READ Commands Burst RCD 1 0 01 TPC 2 0 001 CAS Latency 3 ...

Page 1019: ...DH t RDS c1 c2 c3 c4 c5 c6 c7 c8 t AD t CSD t RWD t CSD t RWD t RASD t RASD t BSD t BSD t DQMD t DQMD t CASD2 t CASD2 t DACD t DACD D31 D0 read DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 25 Synchronous DRAM Normal Read Bus Cycle READ Command Burst CAS Latency 3 ...

Page 1020: ...1 tWDD DQMn CKE tCASD2 tCASD2 tDACD tDACD tRWD tRWD tRASD tRASD tDQMD tDQMD tBSD tBSD RD tCSD tCSD D31 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 26 Synchronous DRAM Auto Precharge Write Bus Cycle Single RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 1021: ...D c2 c3 c4 c5 c6 c7 c8 DQMn CKE t CASD2 t CASD2 t CASD2 t DACD t DACD t RWD t RWD t RASD t RASD t DQMD t BSD t BSD RD t CSD t CSD D31 D0 write DACKn SA IO memory t DQMD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 27 Synchronous DRAM Auto Precharge Write Bus Cycle Burst RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 1022: ... WDD c2 c3 c4 c5 c6 c7 c8 DQMn CKE t CASD2 t CASD2 t DACD t DACD t RWD t RWD t RASD t RASD t DQMD t DQMD t BSD t BSD RD t CSD t CSD D31 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 28 Synchronous DRAM Normal Write Bus Cycle ACT WRITE Commands Burst RCD 1 0 01 TRWL 2 0 010 ...

Page 1023: ... WDD c2 c3 c4 c5 c6 c7 c8 DQMn CKE t CASD2 t CASD2 t DQMD t DQMD t DACD t RWD t RWD t RASD t RASD t DACD t BSD t BSD RD t CSD t CSD D31 D0 write DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 29 Synchronous DRAM Normal Write Bus Cycle PRE ACT WRITE Commands Burst RCD 1 0 01 TPC 2 0 001 TRWL 2 0 010 ...

Page 1024: ...n CKE RD D31 D0 write DACKn SA IO memory Normal write Single address DMA Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high In the case of SA DMA only the Tnop cycle is inserted and the DACKn signal is output as shown by the solid line In a normal write the Tnop cycle is omitted and the DACKn signal is output as shown by the dotted line Figure ...

Page 1025: ...QMn CKE tCASD2 tCASD2 tDQMD tDQMD tRWD tRWD DACKn tRASD tRASD tDACD tDACD tBSD tWDD tWDD RD tCSD tCSD D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 31 Synchronous DRAM Bus Cycle Precharge Command TPC 2 0 001 ...

Page 1026: ...KE tAD tAD tRWD tRWD tDQMD tDQMD tBSD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD tDACD D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 32 Synchronous DRAM Bus Cycle Auto Refresh TRAS 1 TRC 2 0 001 ...

Page 1027: ...D tAD tRWD tRWD tDQMD tDQMD tBSD tDACD tDACD tWDD tWDD tCASD2 tCASD2 tCASD2 tCKED tCKED tCASD2 tRASD tRASD tRASD tRASD tCSD tCSD tCSD tCSD D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 33 Synchronous DRAM Bus Cycle Self Refresh TRC 2 0 001 ...

Page 1028: ...Kn CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 34 a Synchronous DRAM Bus Cycle Mode Register Setting PALL ...

Page 1029: ...Kn CKE tAD tAD tAD tRWD tRWD tRWD tCSD tCSD tCSD tBSD tDQMD tDACD tWDD tWDD tDACD tCASD2 tCASD2 tCASD2 tCASD2 tRASD tRASD tRASD tDQMD D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 34 b Synchronous DRAM Bus Cycle Mode Register Setting SET ...

Page 1030: ... Tc1 Tc2 Tpc t AD t AD t AD Row column t WDD t WDD t WDD t CASD1 t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t CSD t CSD t DACD t DACD t DACD t RWD t RWD t RASD t RASD t RASD t RDH t RDS 1 2 DACKn SA IO memory DACKn SA IO memory D31 D0 read D31 D0 write Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 35 DRAM Bus Cycles 1 RCD 1...

Page 1031: ... t AD t CSD t AD t RASD t RWD t RASD t CASD1 t CASD1 t DACD t DACD t BSD t BSD t RDH t RDS t CASD1 t RASD t RWD t CSD t AD column Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 36 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 1032: ... CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t BSD t BSD RD t CSD t CSD t DACD t DACD t DACD t RWD t RDH t RDS Address DACKn SA IO memory D31 D0 read d1 t RDH t RDS d8 d2 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 37 DRAM Bus Cycle EDO Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 1033: ...D t RASD Row c1 c2 c8 RD t CSD t CSD t CASD1 t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD Address DACKn SA IO memory D31 D0 read Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 38 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 ...

Page 1034: ...t RASD Row c1 c2 c8 RD t CSD t CSD t CASD1 t CASD1 t CASD1 t RASD t CASD1 t CASD1 t BSD t BSD t DACD t DACD t DACD t RWD t RWD Address DACKn SA IO memory D31 D0 read Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 39 DRAM Burst Bus Cycle EDO Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cycle CAS Negate Pulse Width ...

Page 1035: ...t CASD1 t RASD t RASD t CASD1 t CASD1 t CASD1 t CASD1 d8 d2 d1 t BSD t BSD t DACD t DACD t DACD Tc1 Tc1 Tc2 Tce Tc2 Address DACKn SA IO memory D31 D0 read Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 40 DRAM Burst Bus Cycle RAS Down Mode State EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1036: ...RASD RAS down mode ended t CSD t CASD1 t CASD1 t CASD1 t CASD1 d8 d2 d1 t BSD t BSD t DACD t DACD Tc2 T2 Tc1 Tce DACKn SA IO memory D31 D0 read Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 41 DRAM Burst Bus Cycle RAS Down Mode Continuation EDO Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1037: ... t RWD t RDH t RDS d1 t WDD d1 d2 d8 t BSD t BSD t WDD d2 t RDH t WDD t RDS d8 t WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 42 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 00 AnW 2 0 000 TPC 2 0 001 ...

Page 1038: ...WDD t CSD t CSD t DACD t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tc1 Tc2 Tc2 Tcw Tpc Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 43 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 ...

Page 1039: ...t DACD t DACD t CASD1 t CASD1 t CASD1 t CASD1 t CASD1 t RASD t RASD t RASD t DACD t DACD t DACD Tcw Tc1 Tcnw Tc2 Tc1 Tpc Tc2 Tcnw Tcw Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 44 DRAM Burst Bus Cycle Fast Page Mode RCD 1 0 01 AnW 2 0 001 TPC 2 0 001 2 Cycl...

Page 1040: ...AD tAD tRWD tRWD tRDH tRDS d1 tWDD tWDD d1 d2 d8 tBSD tBSD tWDD d2 tRDH tWDD tRDS d8 tCSD tCSD tDACD tDACD tDACD tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tDACD tDACD tDACD tRASD tRASD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 45 DRAM Burst Bus Cycle RAS Down Mode State Fast Page Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1041: ...D1 tCASD1 tCASD1 tDACD tDACD Tnop Tc1 Tc2 Tc1 Tc1 Tc2 Tc2 Tc1 Tc2 Address D31 D0 read D31 D0 write DACKn SA IO memory DACKn SA IO memory RAS down mode ended Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 46 DRAM Burst Bus Cycle RAS Down Mode Continuation Fast Page Mode RCD 1 0 00 AnW 2 0 000 ...

Page 1042: ...te DACKn SA IO memory DACKn SA IO memory tAD tWDD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 47 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 000 TRC 2 0 001 ...

Page 1043: ... tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D31 D0 write DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 48 DRAM Bus Cycle DRAM CAS Before RAS Refresh TRAS 2 0 001 TRC 2 0 001 ...

Page 1044: ...DD tDACD tDACD tCSD tRWD tRASD tRASD tRASD tCASD1 tCASD1 tCASD1 A25 A0 D31 D0 write DACKn SA IO memory DACKn SA IO memory Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 49 DRAM Bus Cycle DRAM Self Refresh TRC 2 0 001 ...

Page 1045: ... t WEDF t WED1 t WEDF t DACD t RDH t RDS t RDYH t RDYS t RDYH t RDYS t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t RSD t RSD t RSD t WEDF t WED1 t WEDF t DACD TED TEH t RDH t RDS t DACD 1 2 A25 A0 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 50 PCMCIA Memory Bus Cycle 1 TED 2 0 000 TEH 2 0 000 No Wait 2 TED 2 0 00...

Page 1046: ...t RDYS t IO16H t IO16S t IO16H t IO16S t DACD t AD t AD t WDD t WDD t WDD t RWD t CSD t CSD t RWD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t DACD t RDH t RDS t DACD D15 D0 read D15 D0 write 1 2 A25 A0 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 51 PCMCIA I O Bus Cycle 1 TED 2 0 000 TEH 2 0 000 No Wait 2 TED 2 0 001 TE...

Page 1047: ...DD t WDD t WDD t WDD t RWD t RWD t AD t CSD t CSD t CSD t ICRSD t ICRSD t ICRSD t ICWSDF t ICWSDF t ICWSDF t ICWSDF t ICWSDF t RDH t RDS t RDYS t RDYH t IO16S t IO16H t RDYS t RDYH Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 52 PCMCIA I O Bus Cycle TED 2 0 001 TEH 2 0 001 One Internal Wait Bus Sizing ...

Page 1048: ...YS t RDYH t RDYS 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1 2 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set...

Page 1049: ...ta bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx B...

Page 1050: ... t RDYH t RDYH 1 2 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set t...

Page 1051: ... t WDD t WDD t RDYS t RDYH 1 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 011 Quad 8 bytes 1xx Burst 32 bytes D25 D0 Address 2 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfe...

Page 1052: ...RSD t RSD t RSD t RSD t RSD t RSD t WED1 t WED1 t WEDF t WED1 t WEDF t WED1 t WEDF t WED1 t CSD t CSD t DACD t BSD t BSD t BSD t BSD t BSD t BSD t DACD t DACD t RWD t RWD t RSD t AD t AD t RDH t RDS t RDH t RDS t RDH t RDS DACKn SA IO memory 2 3 Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 57 Memory Byte Control SRAM Bus Cycles ...

Page 1053: ...SD tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS DACKn SA IO memory tDACD tDACD Notes IO DACK device SA Single address DMA transfer DA Dual address DMA transfer DACK set to active high Figure 23 58 Memory Byte Control SRAM Bus Cycle Basic Read Cycle No Wait Address Setup Hold Time Insertion AnS 0 1 AnH 1 0 01 ...

Page 1054: ...tling time tROSC 3 3 3 3 s 23 64 SCI Input clock cycle asyn chronous tScyc 4 4 4 4 Pcyc 1 23 64 Input clock cycle syn chronous tScyc 6 6 6 6 Pcyc 1 23 64 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 0 4 0 6 tScyc 23 64 Input clock rise time tSCKr 0 8 0 8 0 8 0 8 Pcyc 1 23 64 Input clock fall time tSCKf 0 8 0 8 0 8 0 8 Pcyc 1 23 64 Transfer data delay time tTXD 1 5 5 3 1 5 5 3 1 5 6 1 5 6 ...

Page 1055: ...or sleep mode 30 30 30 30 ns 23 69 Standby mode Input clock cycle tTCKcyc 50 50 50 50 ns 23 65 23 67 Input clock pulse width high tTCKH 15 15 15 15 ns 23 65 Input clock pulse width low tTCKL 15 15 15 15 ns 23 65 Input clock rise time tTCKr 10 10 10 10 ns 23 65 Input clock fall time tTCKf 10 10 10 10 ns 23 65 setup time tASEBRKS 10 10 10 10 tcyc 23 66 hold time tASEBRKH 10 10 10 10 tcyc 23 66 TDI T...

Page 1056: ...9 Oscillation settling time tROSC 3 3 s 23 60 SCI Input clock cycle asynchronous tScyc 4 4 Pcyc 1 23 61 Input clock cycle synchronous tScyc 6 6 Pcyc 1 23 61 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 tScyc 23 61 Input clock rise time tSCKr 0 8 0 8 Pcyc 1 23 61 Input clock fall time tSCKf 0 8 0 8 Pcyc 1 23 61 Transfer data delay time tTXD 30 30 ns 23 62 Receive data setup time synchronous tRXS 0...

Page 1057: ...nput clock pulse width high tTCKH 15 15 ns 23 65 Input clock pulse width low tTCKL 15 15 ns 23 65 Input clock rise time tTCKr 10 10 ns 23 65 Input clock fall time tTCKf 10 10 ns 23 65 setup time tASEBRKS 10 10 tcyc 23 66 hold time tASEBRKH 10 10 tcyc 23 66 TDI TMS setup time tTDIS 15 15 ns 23 67 TDI TMS hold time tTDIH 15 15 ns 23 67 TDO delay time tTDO 0 12 0 10 ns 23 67 H UDI ASE PINBRK pulse wi...

Page 1058: ... Timing RTC internal clock VDD RTC Oscillation settling time tROSC VDD RTC min Figure 23 60 RTC Oscillation Settling Time at Power On SCK SCK2 tSCKf tScyc tSCKW tSCKr Figure 23 61 SCK Input Clock Timing tTXD SCK TXD RXD tTXD tRXS tRXH tScyc Figure 23 62 SCI I O Synchronous Mode Clock Timing ...

Page 1059: ...Port Input Output Timing tDRAKD tDRQH tDRQH tDRQS tDRQS CKIO DREQn DRAKn Figure 23 64 a DRAK Timing tDBQH tDBQS CKIO D31 to D0 READ DBREQ BAVL TR tBAVD tBAVD tTRH 2 tTRS tDTRH tDTRS 1 1 2CKIO cycle tDTRS 18 ns 100 MHz 2 DTR 1CKIO cycle 10 ns 100 MHz tDTRS tDTRH DTR 10 ns Figure 23 64 b Input Timing and Output Timing ...

Page 1060: ...VDDQ VIH VIH VIL VIL VIH 1 2VDDQ Note When clock is input from TCK pin Figure 23 65 TCK Input Timing BRKACK tASEBRKH tASEBRKS Figure 23 66 Hold Timing TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 23 67 H UDI Data Transfer Timing tPINBRK Figure 23 68 Pin Break Timing ...

Page 1061: ...Rev 3 0 04 02 page 1022 of 1064 NMI tNMIL tNMIH Figure 23 69 NMI Input Timing ...

Page 1062: ...me tPCIVAL 10 8 ns 23 71 Input hold time tPCIH 1 5 1 5 ns 23 72 IDSEL Input setup time tPCISU 3 3 ns 23 72 Output data delay time tPCIVAL 10 8 ns 23 71 Tri state drive delay time tPCION 10 10 ns 23 71 Tri state high impedance delay time tPCIOFF 12 12 ns 23 71 Input hold time tPCIH 1 5 1 5 ns 23 72 AD31 AD0 C C PAR Input setup time tPCISU 3 3 ns 23 72 Output data delay time tPCIVAL 10 8 ns 23 71 Tr...

Page 1063: ...CLK Clock fall time tPCIf 4 1 5 ns 23 70 Output data delay time tPCIVAL 10 10 ns 23 71 Input hold time tPCIH 1 1 ns 23 72 IDSEL Input setup time tPCISU 3 3 ns 23 72 Output data delay time tPCIVAL 10 10 ns 23 71 Tri state drive delay time tPCION 10 10 ns 23 71 Tri state high impedance delay time tPCIOFF 12 12 ns 23 71 Input hold time tPCIH 1 1 ns 23 72 AD31 AD0 C C PAR Input setup time tPCISU 3 3 n...

Page 1064: ...25 of 1064 0 5VDDQ VH VH tPCIf tPCIr VL VL 0 5VDDQ VH tPCILOW tPCIHIGH tPCICYC Figure 23 70 PCI Clock Input Timing PCICLK 0 4VDDQ 0 4VDDQ tPCION tPCIOFF tPCIVAL Output delay 3 state output Figure 23 71 Output Signal Timing ...

Page 1065: ...3 Input hold time tPCIPORTH 1 5 ns 23 73 MD9 MD10 Input setup time tPCIPORTS 3 5 ns 23 73 Output data delay time tPCIPORTD 10 ns 23 73 Table 23 33 PCIC Signal Timing With PCIREQ PCIGNT Port Settings in Non Host Mode 2 HD6417751BP167 HD6417751F167 VDDQ 3 0 to 3 6 V VDD 1 8 V Ta 20 to 75 C CL 30 pF HD6417751BP167I HD6417751F167I VDDQ 3 0 to 3 6 V VDD 1 8 V Ta 40 to 85 C CL 30 pF Pin Item Symbol Min ...

Page 1066: ...1 5 V typ Ta 20 to 75 C CL 30 pF PLL2 on Pin Item Symbol Min Max Unit Figure Output data delay time tPCIPORTD 10 ns 23 73 Input hold time tPCIPORTH 1 5 ns 23 73 MD9 MD10 Input setup time tPCIPORTS 3 5 ns 23 73 Output data delay time tPCIPORTD 10 ns 23 73 CKIO read write tPCIPORTH tPCIPORTD tPCIPORTD tPCIPORTS Figure 23 73 I O Port Input Output Timing ...

Page 1067: ...e level VSSQ 3 0 V VSSQ VDDQ for NMI and BRKACK Input rise fall time 1 ns The output load circuit is shown in figure 23 74 IOL IOH CL VREF LSI output pin DUT output Notes 1 2 CL is the total value including the capacitance of the test jig etc The capacitance of each pin is set to 30 pF IOL and IOH values are as shown in table 23 11 Permissible Output Currents Figure 23 74 Output Load Circuit ...

Page 1068: ...ue 30 pF is connected to the LSI pins When connecting an external device with a load capacitance exceeding the regulation use the chart in figure 23 74 as reference for system design Note that if the load capacitance to be connected exceeds the range shown in figure 23 75 the graph will not be a straight line 4 0 ns 3 0 ns 2 0 ns 1 0 ns 0 0 ns 0 pF 25 pF 50 pF Load capacitance Delay time Figure 23...

Page 1069: ...Rev 3 0 04 02 page 1030 of 1064 ...

Page 1070: ... 00 Held Held Held Pclk TMU TCOR3 H FE10 0008 H 1E10 0008 32 H FFFF FFFF Held Held Held Pclk TMU TCNT3 H FE10 000C H 1E10 000C 32 H FFFF FFFF Held Held Held Pclk TMU TCR3 H FE10 0010 H 1E10 0010 16 H 0000 Held Held Held Pclk TMU TCOR4 H FE10 0014 H 1E10 0014 32 H FFFF FFFF Held Held Held Pclk TMU TCNT4 H FE10 0018 H 1E10 0018 32 H FFFF FFFF Held Held Held Pclk TMU TCR4 H FE10 001C H 1E10 001C 16 H...

Page 1071: ...d Pclk PCIC PCILSR1 H FE20 0108 H 1E20 0108 32 H 00000000 Held Held Held Pclk PCIC PCILAR0 H FE20 010C H 1E20 010C 32 H 00000000 Held Held Held Pclk PCIC PCILAR1 H FE20 0110 H 1E20 0110 32 H 00000000 Held Held Held Pclk PCIC PCIINT H FE20 0114 H 1E20 0114 32 H 00000000 Held Held Held Pclk PCIC PCIINTM H FE20 0118 H 1E20 0118 32 H 00000000 Held Held Held Pclk PCIC PCIALR H FE20 011C H 1E20 011C 32 ...

Page 1072: ...ld Held Pclk PCIC PCIIOBR H FE20 01C8 H 1E20 01C8 32 Undefined Held Held Held Pclk PCIC PCIPINT H FE20 01CC H 1E20 01CC 32 H 00000000 Held Held Held Pclk PCIC PCIPINTM H FE20 01D0 H 1E20 01D0 32 H 00000000 Held Held Held Pclk PCIC PCICLKR H FE20 01D4 H 1E20 01D4 32 H 00000000 Held Held Held Pclk PCIC PCIBCR1 H FE20 01E0 H 1E20 01E0 32 H 00000000 Held Held Held Pclk PCIC PCIBCR2 H FE20 01E4 H 1E20 ...

Page 1073: ... CCN QACR0 H FF00 0038 H 1F00 0038 32 Undefined Undefined Held Held Iclk CCN QACR1 H FF00 003C H 1F00 003C 32 Undefined Undefined Held Held Iclk UBC BARA H FF20 0000 H 1F20 0000 32 Undefined Held Held Held Iclk UBC BAMRA H FF20 0004 H 1F20 0004 8 Undefined Held Held Held Iclk UBC BBRA H FF20 0008 H 1F20 0008 16 H 0000 Held Held Held Iclk UBC BARB H FF20 000C H 1F20 000C 32 Undefined Held Held Held...

Page 1074: ... Undefined Held Held Bclk DMAC DAR0 H FFA0 0004 H 1FA0 0004 32 Undefined Undefined Held Held Bclk DMAC DMATCR0 H FFA0 0008 H 1FA0 0008 32 Undefined Undefined Held Held Bclk DMAC CHCR0 H FFA0 000C H 1FA0 000C 32 H 0000 0000 H 0000 0000 Held Held Bclk DMAC SAR1 H FFA0 0010 H 1FA0 0010 32 Undefined Undefined Held Held Bclk DMAC DAR1 H FFA0 0014 H 1FA0 0014 32 Undefined Undefined Held Held Bclk DMAC D...

Page 1075: ...000 H 0000 0000 Held Held Bclk DMAC SAR7 H FFA0 0080 H 1FA0 0080 32 Undefined Undefined Held Held Bclk DMAC DAR7 H FFA0 0084 H 1FA0 0084 32 Undefined Undefined Held Held Bclk DMAC DMATCR7 H FFA0 0088 H 1FA0 0088 32 Undefined Undefined Held Held Bclk DMAC CHCR7 H FFA0 008C H 1FA0 008C 32 H 0000 0000 H 0000 0000 Held Held Bclk CPG FRQCR H FFC0 0000 H 1FC0 0000 16 2 Held Held Held Pclk CPG STBCR H FF...

Page 1076: ...0000 Held Held Pclk INTC IPRD H FFD0 0010 H 1FD0 0010 16 H DA74 H DA74 Held Held Pclk TMU TOCR H FFD8 0000 H 1FD8 0000 8 H 00 H 00 Held Held Pclk TMU TSTR H FFD8 0004 H 1FD8 0004 8 H 00 H 00 Held H 00 2 Pclk TMU TCOR0 H FFD8 0008 H 1FD8 0008 32 H FFFF FFFF H FFFF FFFF Held Held Pclk TMU TCNT0 H FFD8 000C H 1FD8 000C 32 H FFFF FFFF H FFFF FFFF Held Held Pclk TMU TCR0 H FFD8 0010 H 1FD8 0010 16 H 00...

Page 1077: ...4 8 Undefined Undefined Held Held Pclk SCIF SCFCR2 H FFE8 0018 H 1FE8 0018 16 H 0000 H 0000 Held Held Pclk SCIF SCFDR2 H FFE8 001C H 1FE8 001C 16 H 0000 H 0000 Held Held Pclk SCIF SCSPTR2 H FFE8 0020 H 1FE8 0020 16 H 0000 2 H 0000 2 Held Held Pclk SCIF SCLSR2 H FFE8 0024 H 1FE8 0024 16 H 0000 H 0000 Held Held Pclk H UDI SDIR H FFF0 0000 H 1FF0 0000 16 H FFFF 2 Held Held Held Pclk H UDI SDDR H FFF0...

Page 1078: ...ce value FP 256G Conforms 5 4 g Dimension including the plating thickness Base material dimension 30 6 0 2 28 0 4 3 95 Max 0 8 0 18 0 05 1 65 0 11 M 0 08 0 5 0 2 1 3 0 17 0 05 3 20 64 128 129 192 193 256 30 6 0 2 0 40 0 10 0 15 1 4 0 16 0 04 0 15 0 04 Unit mm Figure B 1 Package Dimensions 256 pin QFP ...

Page 1079: ...6 0 1 0 35 C C 0 20 C Details of the part A 256 φ0 75 0 15 0 30 C B A M 0 10 C M Y V T P M K H F D B W U R N L J G E C A A 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Hitachi Code JEDEC JEITA Mass reference value BP 256 3 0 g Unit mm Figure B 2 Package Dimensions 256 pin BGA ...

Page 1080: ... H 0E0A 5 1 0 1 Off On On 6 3 3 2 H 0E0A Table C 2 Clock Operating Modes SH7751R External Pin Combination Frequency vs Input Clock Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 0 On 12 On 12 3 3 H 0E1A 1 0 1 On 12 On 12 3 2 3 2 H 0E2C 2 0 On 6 On 6 2 1 H 0E13 3 0 1 1 On 12 On 12 4 2 H 0E13 4 0 On 6 On 6 3 3 2 H 0E0A 5 0 1 On 12 On 12 6...

Page 1081: ... Reserved Cannot be used Reserved Cannot be used 1 MPX interface 32 bits 1 0 0 Reserved Cannot be used Reserved Cannot be used 1 SRAM interface 8 bits 1 0 SRAM interface 16 bits 1 SRAM interface 32 bits Table C 4 Endian Pin Value MD5 Endian 0 Big endian 1 Little endian Table C 5 Master Slave Pin Value MD7 Master Slave 0 Slave 1 Master Table C 6 Clock Input Pin Value MD8 Clock Input 0 External inpu...

Page 1082: ...e Mode MD10 MD9 Mode 0 0 0 PCI host with external clock input 1 0 1 PCI host with bus clock 2 1 0 PCI non host with external clock input 3 1 1 PCI disabled Note When exiting standby mode or hardware standby mode using a power on reset do not change the PCI mode ...

Page 1083: ... Z 15 Z 15 O 5 Z 15 O 5 Z O H PZ O 6 Z Z 15 O 5 Z 15 O 5 Z RD O H PZ H Z 15 Z 15 H 7 Z 15 Z I PI PI I 14 I 14 I 14 I 14 I DQM3 O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z DQM2 O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z DQM1 O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z DQM0 O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z O H PZ O 6 Z 15 Z 15 O 5 Z 15 O 5 Z O H PZ...

Page 1084: ...Z 13 O 8 OI 13 Z 13 O 8 Z DMAC MD0 SCK2 I O I 19 I 19 I 13 I 13 OI 13 Z 13 O 8 I 13 O Z SCIF RXD I PI PI I 13 I 13 I 13 I 13 I SCI SCK I O PI PI I 13 I 13 I 13 Z 13 O 8 I 13 O Z SCI MD1 TXD2 I O I 19 I 19 Z 13 Z 13 Z 13 O 8 Z 13 O Z SCIF MD2 RXD2 I I 19 I 19 I 13 I 13 I 13 I 13 I SCIF TxD I O PZ PZ Z 13 O Z 13 O Z 13 O 8 O Z SCI MD8 RTS2 I O I 19 I 19 I 13 I 13 I 13 Z 13 O 8 I 13 O Z SCIF TCLK I O...

Page 1085: ...12 Z 12 PZ PZ Z I O PZ PZ IZ 12 IZ 12 Z 12 Z 12 PZ PZ Z I O PZ PZ IOZ 12 IOZ 12 Z 12 Z 12 PZ PZ Z I O PZ PZ IOZ 12 IOZ 12 Z 12 Z 12 PZ PZ Z I O PZ PZ IOZ 12 IOZ 12 Z 12 Z 12 PZ PZ Z I O PZ PZ IOZ 12 IOZ 12 Z 12 Z 12 PZ PZ Z I O PZ PZ IOZ 12 IOZ 12 Z 12 Z 12 PZ PZ Z I O PI PZ I 12 Z 12 IO 13 18 I 12 Z 12 IO 12 18 PI PZ IO 12 18 Z Values in paren thesis are when using PORT I PI PI I 12 I 12 I 12 I 1...

Page 1086: ... O Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z O Z Z Z Z Z Z Z O Z Z Z Z Z Z Z PCICLK Z Z Z Z Z Z Z O Z Z Z Z Z Z Z IDSEL Z Z Z Z Z Z Z Z Z Z Z Z Z Z Notes I Input O Output H High level output L Low level output Z High impedance K Output state held IZ IOZ Response to access from PCI PZ Pul...

Page 1087: ...llup depending on register setting BCR1 IPUP 15 Pullup depending on register setting BCR1 OPUP 16 Pullup depending on register setting BCR1 DPUP 17 Pullup depending on register setting BCR2 PORTEN 18 Pullup depending on register setting PCIPCTR PB2PUP to PCIPCTR PB4PUP 19 Pullup by on chip pullup resistor Note that this cannot be used for pullup of the mode pin during a power on reset Pullup or pu...

Page 1088: ...O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I O Pull up to 3 3 V I Pull up to 3 3 V O Pull up to 3 3 V O Pull up to 3 3 V PCICLK I Pull up to 3 3 V O Leave unconnected IDSEL I Pull up to 3 3 V O Leave unconnected Note When not used as a general purpose I O port ...

Page 1089: ... 8bit 4MB SH7751 Series Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1090: ...ess Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1091: ...s Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1092: ...s Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1093: ...AS Cycle Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1094: ...S Cycle Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 BANK selects bank address A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1095: ... Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 BANK selects bank address A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1096: ... Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H L A10 Address precharge setting A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used ...

Page 1097: ...Cycle CAS Cycle Synchronous DRAM Address Pins Function A15 A25 A25 A13 A14 A24 A24 A12 BANK selects bank address A13 A23 0 A11 A12 A22 H L A10 Address precharge setting A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 Not used A0 Not used ...

Page 1098: ...AS Cycle Synchronous DRAM Address Pins Function A16 A25 A25 A14 A15 A24 A24 A13 BANK selects bank address A14 A23 0 A12 A13 A22 0 A11 A12 A21 H L A10 Address precharge setting A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 Not used A0 Not used ...

Page 1099: ...S Cycle Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H L A9 Address precharge setting A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 Not used A0 Not used Note Example configurations of synchronous DRAM ...

Page 1100: ...s a case in which the instruction ADD indicated by the program counter PC and the address H 04000002 instruction prefetch are executed simultaneously It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction In this case the program flow is unpredictable and a bus access instruction prefetch to area 1 may be i...

Page 1101: ...he timing of Turn off the I O RTC CPG power supply voltage after or at the same time as turning off the internal power supply voltage Note however that the internal power supply voltage may exceed the I O RTC CPG power supply voltage by a maximum of 0 3 V only when the system is being turned off The power supply level must be lowered in compliance with the I O RTC CPG power supply voltage Note 10 ...

Page 1102: ... Name Voltage Operating Frequency Model Marking Package SH7751 1 8 V 167 MHz HD6417751BP167 256 pin BGA HD6417751F167 256 pin QFP 1 5 V 133 MHz HD6417751VF133 SH7751R 1 5 V 240 MHz HD6417751RBP240 256 pin BGA HD6417751RF240 256 pin QFP 200 MHz HD6417751RBP200 256 pin BGA HD6417751RF200 256 pin QFP ...

Page 1103: ...Rev 3 0 04 02 page 1064 of 1064 ...

Page 1104: ...April 2000 3rd Edition April 2002 Published by Business Planning Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2000 All rights reserved Printed in Japan ...

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