Rev. 3.0, 04/02, page 998 of 1064
Tr1
Tr2
Tc1
Tc2
Tc1
Tc2
Tc2
Tc1
Tc1
Tc2
Tpc
CKIO
Address
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO
→
memory)
DACKn
(SA: IO
←
memory)
t
AD
c1
Row
c2
c8
t
AD
t
AD
t
RWD
t
RWD
t
RDH
t
RDS
d1
t
WDD
d1
d2
d8
t
BSD
t
BSD
t
WDD
d2
t
RDH
t
WDD
t
RDS
d8
t
WDD
t
CSD
t
CSD
t
DACD
t
DACD
t
DACD
t
CASD1
t
CASD1
t
CASD1
t
CASD1
t
CASD1
t
RASD
t
RASD
t
RASD
t
DACD
t
DACD
t
DACD
Notes:
IO:
DACK device
SA:
Single address DMA transfer
DA:
Dual address DMA transfer
DACK set to active-high
Figure 23.42 DRAM Burst Bus Cycle
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)
Summary of Contents for SH7751
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