Rev. 3.0, 04/02, page 635 of 1064
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
SCFRDR2
(16-stage)
SCRSR2
RxD2
TxD2
SCK2
SCFTDR2
(16-stage)
SCTSR2
SCSMR2
SCLSR2
SCFDR2
SCFCR2
SCFSR2
SCBRR2
Parity generation
Parity check
Transmission/
reception
control
Baud rate
generator
Clock
External clock
P
φ
P
φ
/4
P
φ
/16
P
φ
/64
TXI
RXI
ERI
BRI
SCIF
Bus interface
Internal
data bus
SCSCR2
SCSPTR2
SCRSR2:
Receive shift register
SCFRDR2: Receive FIFO data register
SCTSR2:
Transmit shift register
SCFTDR2: Transmit FIFO data register
SCSMR2:
Serial mode register
SCSCR2:
Serial control register
SCFSR2:
Serial status register
SCBRR2:
Bit rate register
SCSPTR2: Serial port register
SCFCR2:
FIFO control register
SCFDR2:
FIFO data count register
SCLSR2:
Line status register
Figure 16.1 Block Diagram of SCIF
Summary of Contents for SH7751
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