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Bus cycle
(When Bcyc : Pcyc = 1 : 1)
CKIO
Source address
Read
Read
Read
D[31:0]
Write
Write
Write
Source address
Source address
A[25:0]
Destination address
Destination address
Destination address
CPU
DMAC
CPU
DMAC
CPU
DMAC
T1
T2
T1
T2
T1
T2
On-chip
peripheral
address bus
On-chip
peripheral
data bus
Figure 14.17 Dual Address Mode/Cycle Steal Mode
External Bus
On-Chip SCI (Level Detection)
Summary of Contents for SH7751
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