Rev. 3.0, 04/02, page 202 of 1064
(e) Flow dependency
I
D
EX
NA
S
I
D
EX
NA
S
MOV
R0,R1
ADD R2,R1
ADD
R2,R1
MOV.L @R1,R1
next
I
D
EX
NA
S
I
D
EX
MA
S
i
I
...
...
...
Zero-cycle latency
1-cycle latency
1 stall cycle
MOV.L @R1,R1
ADD
R0,R1
next
I
D
EX
MA
S
I
D
I
EX
NA
S
D
EX
NA
S
2-cycle latency
1 stall cycle
MOV.L @R1,R1
SHAD
R1,R2
next
FADD
FR1,FR2
STS
FPUL,R1
STS
FPSCR,R2
I
D
EX
NA
S
I
4-cycle latency for FPSCR
2 stall cycles
I
D
F1
F2
FS
I
D
EX
MA
S
I
D
I
2-cycle latency
2 stall cycles
EX
NA
S
d
1-cycle increase
I
I
I
D
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
F2
FS
d
F1
F2
FS
EX
NA
S
D
EX
NA
S
D
FADD DR0,DR2
7-cycle latency for lower FR
8-cycle latency for upper FR
FMOV
FR3,FR5
FMOV
FR2,FR4
FLOAT
FPUL,DR0
FMOV.S FR0,@-R15
FR3 write
FR2 write
I
D
F1
F2
FS
d
F1
F2
FS
I
D
EX
MA
S
3-cycle latency for upper/lower FR
FR1 write
FR0 write
FLDI1
FR3
FIPR
FV0,FV4
FMOV
@R1,XD14
FTRV
XMTRX,FV0
I
D
EX
NA
S
I
D
d
F0
F1
F2
FS
Zero-cycle latency
3-cycle increase
3 stall cycles
I
D
EX
MA
S
I
D
d
F0
F1
F2
FS
d
F0
F1
FS
F2
d
F0
F2
F1
FS
d
F1
F0
F2
FS
2-cycle latency
1-cycle increase
3 stall cycles
The following instruction, ADD, is not
stalled when executed after an instruction
with zero-cycle latency, even if there is
dependency.
ADD and MOV.L are not executed in
parallel, since MOV.L references the result
of ADD as its destination address.
Because MOV.L and ADD are not fetched
simultaneously in this example, ADD is
stalled for only 1 cycle even though the
latency of MOV.L is 2 cycles.
Due to the flow dependency between the
load and the SHAD/SHLD shift amount,
the latency of the load is increased to 3
cycles.
Figure 8.3 Examples of Pipelined Execution (cont)
Summary of Contents for SH7751
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