Rev. 3.0, 04/02, page 1015 of 1064
23.3.4
Peripheral Module Signal Timing
Table 23.28 Peripheral Module Signal Timing (1)
HD6417751
RBP240
HD6417751
RBP200
HD6417751
RF240
HD6417751
RF200
*
2
*
2
*
2
*
2
Module Item
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit
Figure Notes
TMU,
RTC
Timer clock
pulse width
(high)
t
TCLKWH
4
—
4
—
4
—
4
—
Pcyc*
1
23.64
Timer clock
pulse width
(low)
t
TCLKWL
4
—
4
—
4
—
4
—
Pcyc*
1
23.64
Timer clock
rise time
t
TCLKr
—
0.8
—
0.8
—
0.8
—
0.8
Pcyc*
1
23.64
Timer clock
fall time
t
TCLKf
—
0.8
—
0.8
—
0.8
—
0.8
Pcyc*
1
23.64
Oscillation
settling time
t
ROSC
—
3
—
3
—
3
—
3
s
23.64
SCI
Input clock
cycle (asyn-
chronous)
t
Scyc
4
—
4
—
4
—
4
—
Pcyc*
1
23.64
Input clock
cycle (syn-
chronous)
t
Scyc
6
—
6
—
6
—
6
—
Pcyc*
1
23.64
Input clock
pulse width
t
SCKW
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
Scyc
23.64
Input clock
rise time
t
SCKr
—
0.8
—
0.8
—
0.8
—
0.8
Pcyc*
1
23.64
Input clock
fall time
t
SCKf
—
0.8
—
0.8
—
0.8
—
0.8
Pcyc*
1
23.64
Transfer
data delay
time
t
TXD
1.5
5.3
1.5
5.3
1.5
6
1.5
6
ns
23.64
Receive
data setup
time (syn-
chronous)
t
RXS
16
—
16
—
16
—
16
—
ns
23.64
Receive
data hold
time (syn-
chronous)
t
RXH
16
—
16
—
16
—
16
—
ns
23.64
I/O
ports
Output data
delay time
t
PORTD
1.5
5.3
1.5
5.3
1.5
6
1.5
6
ns
23.64
Input data
setup time
t
PORTS
2
—
2.5
—
3.5
—
3.5
—
ns
23.64
Input data
hold time
t
PORTH
1.5
—
1.5
—
1.5
—
1.5
—
ns
23.64
Summary of Contents for SH7751
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